[PATCH 0/9] Various cleanups for Samsung clocks drivers

[PATCH 0/9] Various cleanups for Samsung clocks drivers

[Marek Szyprowski]

Hi!

While touching Samsung clock drivers I found that there is still some
legacy code left. This patchset is a quick cleanup of the issues I've
noticed so far. The most significant change is removal clkdev alias
support from generic macros used for instantiating all the clocks in
the Samsung drivers. This should reduce the total size of the clock init
structures. Required clkdev aliases can be still created using
samsung_clk_register_alias() function if given platform still needs
them.

Patches have been generated on top of linux-next with "clk: samsung:
Properly propagate flags in __PLL macro" patch applied.

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Patch summary:

Marek Szyprowski (9):
  clk: samsung: Remove support for obsolete Exynos4212 CPU clock
  clk: samsung: Remove clkdev alias support in Exynos4 clk driver
  clk: samsung: Remove double assignment to CLK_ARM_CLK id in Exynos4
    driver
  clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
  clk: samsung: Drop useless alias in Exynos5420 clk driver
  clk: samsung: Rework clkdev alias handling in Exynos5440 driver
  clk: samsung: Rework clkdev alias handling in S3C2443 driver
  clk: samsung: Add explicit MPLL and EPLL clkdev aliases in S3C2443
    driver
  clk: samsung: Remove obsolete clkdev alias support

 drivers/clk/samsung/clk-exynos4.c    | 82 +++++++-----------------------------
 drivers/clk/samsung/clk-exynos5250.c | 18 ++++----
 drivers/clk/samsung/clk-exynos5420.c |  3 +-
 drivers/clk/samsung/clk-exynos5440.c | 12 +++++-
 drivers/clk/samsung/clk-pll.c        |  9 ----
 drivers/clk/samsung/clk-s3c2443.c    | 16 ++++---
 drivers/clk/samsung/clk.c            | 33 ++-------------
 drivers/clk/samsung/clk.h            | 71 ++++++-------------------------
 include/dt-bindings/clock/s3c2443.h  |  2 +
 9 files changed, 62 insertions(+), 184 deletions(-)

-- 
2.14.2

[PATCH 1/9] clk: samsung: Remove support for obsolete Exynos4212 CPU clock

[Marek Szyprowski]

Support for Exynos 4212 SoC has been removed by commit bca9085e0ae9 ("ARM:
dts: exynos: remove Exynos4212 support (dead code)"), so there is no need
to keep dead code.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 33 ++++-----------------------------
 1 file changed, 4 insertions(+), 29 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index e40b77583c47..9a51ce9a658f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1401,24 +1401,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
 	{  0 },
 };
 
-static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
-	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
-	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
-	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
-	{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
-	{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
-	{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
-	{  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
-	{  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
-	{  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
-	{  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
-	{  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
-	{  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
-	{  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
-	{  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
-	{  0 },
-};
-
 #define E4412_CPU_DIV1(cores, hpm, copy)				\
 		(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
 
@@ -1533,17 +1515,10 @@ static void __init exynos4_clk_init(struct device_node *np,
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4x12_fixed_factor_clks,
 			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
-		if (of_machine_is_compatible("samsung,exynos4412")) {
-			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
-				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
-				e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
-				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
-		} else {
-			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
-				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
-				e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
-				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
-		}
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+			e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
+			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
 	}
 
 	samsung_clk_register_alias(ctx, exynos4_aliases,
-- 
2.14.2

[PATCH 2/9] clk: samsung: Remove clkdev alias support in Exynos4 clk driver

[Marek Szyprowski]

All Exynos4 boards have been fully converted to device-tree and use generic
dt-based CPUfreq driver, so there is no need to create any clkdev aliases
for the clocks. Drop all the code related to aliases handling.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 47 +++++++++------------------------------
 1 file changed, 10 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 9a51ce9a658f..3fbfd9ed82b7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -535,9 +535,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __
 
 /* list of mux clocks supported in all exynos4 soc's */
 static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
-	MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
-			CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
-			"mout_apll"),
+	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
 	MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
 	MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
@@ -838,11 +837,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
 
 /* list of gate clocks supported in all exynos4 soc's */
 static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
-	/*
-	 * After all Exynos4 based platforms are migrated to use device tree,
-	 * the device name and clock alias names specified below for some
-	 * of the clocks can be removed.
-	 */
 	GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
 	GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
 	GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
@@ -1190,20 +1184,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
 		0),
 };
 
-static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
-	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
-	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
-	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
-};
-
-static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
-	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
-};
-
-static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
-	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
-};
-
 /*
  * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
  * resides in chipid register space, outside of the clock controller memory
@@ -1340,14 +1320,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst =
 };
 
 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
-	[apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
-		APLL_LOCK, APLL_CON0, "fout_apll", NULL),
-	[mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
-		E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
-	[epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
-		EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
-	[vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
-		VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
+	[apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+		APLL_LOCK, APLL_CON0, NULL),
+	[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
+		E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
+	[epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+		EPLL_LOCK, EPLL_CON0, NULL),
+	[vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
+		VPLL_LOCK, VPLL_CON0, NULL),
 };
 
 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
@@ -1494,8 +1474,6 @@ static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4210_div_clks));
 		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
 			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_alias(ctx, exynos4210_aliases,
-			ARRAY_SIZE(exynos4210_aliases));
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4210_fixed_factor_clks,
 			ARRAY_SIZE(exynos4210_fixed_factor_clks));
@@ -1510,8 +1488,6 @@ static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4x12_div_clks));
 		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
 			ARRAY_SIZE(exynos4x12_gate_clks));
-		samsung_clk_register_alias(ctx, exynos4x12_aliases,
-			ARRAY_SIZE(exynos4x12_aliases));
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4x12_fixed_factor_clks,
 			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
@@ -1521,9 +1497,6 @@ static void __init exynos4_clk_init(struct device_node *np,
 			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
 	}
 
-	samsung_clk_register_alias(ctx, exynos4_aliases,
-			ARRAY_SIZE(exynos4_aliases));
-
 	if (soc == EXYNOS4X12)
 		exynos4x12_core_down_clock();
 	exynos4_clk_sleep_init();
-- 
2.14.2

[PATCH 3/9] clk: samsung: Remove double assignment to CLK_ARM_CLK id in Exynos4 driver

[Marek Szyprowski]

CLK_ARM_CLK ("armclk") clock is provided by cpu-clk subdriver, which is
instantiated after creating all divider clocks from exynos4_div_clks
array. There is no point assigning this id to "div_core2" clock and later
overwrite with proper "armcpu" clock by cpu-clk subdriver.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 3fbfd9ed82b7..3bd2d84b2a17 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -721,7 +721,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
 	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
 	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
 	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-	DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
+	DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
 	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
 	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
 	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
-- 
2.14.2

[PATCH 4/9] clk: samsung: Remove clkdev alias support in Exynos5250 clk driver

[Marek Szyprowski]

All Exynos5250 boards have been fully converted to device-tree and use
generic dt-based CPUfreq driver, so there is no need to create any clkdev
aliases for the clocks. Drop all the code related to aliases handling.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5250.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 27a227d6620c..9b073c98a891 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
 	/*
 	 * CMU_CPU
 	 */
-	MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
-					CLK_SET_RATE_PARENT, 0, "mout_apll"),
-	MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+					CLK_SET_RATE_PARENT, 0),
+	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
 
 	/*
 	 * CMU_CORE
 	 */
-	MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
+	MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
 
 	/*
 	 * CMU_TOP
@@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
 	 */
 	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+	DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
 
 	/*
 	 * CMU_TOP
@@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
 };
 
 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
-	[apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
-		APLL_LOCK, APLL_CON0, "fout_apll", NULL),
-	[mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
-		MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+		APLL_CON0, NULL),
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+		MPLL_CON0, NULL),
 	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
 		BPLL_CON0, NULL),
 	[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
-- 
2.14.2

[PATCH 5/9] clk: samsung: Drop useless alias in Exynos5420 clk driver

[Marek Szyprowski]

Drop clkdev alias for "mout_aclk400_mscl" clock. It was not used at all
and it was probably committed by accident.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 038701a2af4c..45d34f601e9e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 				TOP_SPARE2, 4, 1),
 
 	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
-	MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
-				SRC_TOP0, 4, 2, "aclk400_mscl"),
+	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
 	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
 	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
 
-- 
2.14.2

[PATCH 6/9] clk: samsung: Rework clkdev alias handling in Exynos5440 driver

[Marek Szyprowski]

Exynos5440 still uses old, non-dt CPUfreq driver, which requires clkdev
aliases to get access to proper clocks. Create those aliases using
samsung_clk_register_alias() function instead of using *_A clock macros,
which will be removed soon.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5440.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index a80f3ef20801..b08bd54c5e76 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __
 /* mux clocks */
 static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
 	MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
-	MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
-			CPU_CLK_STATUS, 0, 1, "armclk"),
+	MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
 };
 
 /* divider clocks */
@@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
 	PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
 };
 
+/*
+ * Clock aliases for legacy clkdev look-up.
+ */
+static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
+	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
+};
+
 /* register exynos5440 clocks */
 static void __init exynos5440_clk_init(struct device_node *np)
 {
@@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
 			ARRAY_SIZE(exynos5440_div_clks));
 	samsung_clk_register_gate(ctx, exynos5440_gate_clks,
 			ARRAY_SIZE(exynos5440_gate_clks));
+	samsung_clk_register_alias(ctx, exynos5440_aliases,
+						ARRAY_SIZE(exynos5440_aliases));
 
 	samsung_clk_of_add_provider(np, ctx);
 
-- 
2.14.2

[PATCH 7/9] clk: samsung: Rework clkdev alias handling in S3C2443 driver

[Marek Szyprowski]

S3C2443 SoCs still uses old, non-dt CPUfreq driver, which requires clkdev
aliases to get access to proper clocks. Create those aliases using
samsung_clk_register_alias() function instead of using *_A clock macros,
which will be removed soon.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-s3c2443.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index abb935c42916..45166033f638 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -117,8 +117,8 @@ struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
 	MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
 	MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
 	MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
-	MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"),
-	MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"),
+	MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
+	MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
 	MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
 };
 
@@ -189,6 +189,8 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
 };
 
 struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
+	ALIAS(MSYSCLK, NULL, "msysclk"),
+	ALIAS(ARMCLK, NULL, "armclk"),
 	ALIAS(HCLK, NULL, "hclk"),
 	ALIAS(HCLK_SSMC, NULL, "nand"),
 	ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
-- 
2.14.2

[PATCH 8/9] clk: samsung: Add explicit MPLL and EPLL clkdev aliases in S3C2443 driver

[Marek Szyprowski]

S3C2443 platform still use non-dt based lookup in some of its drivers to
get MPLL and EPLL clocks. Till now it worked only because PLL() macro
implicitely created aliases for all instatiated clocks. This feature will
be removed, so explicitely create aliases for MPLL and EPLL clocks.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-s3c2443.c   | 10 ++++++----
 include/dt-bindings/clock/s3c2443.h |  2 ++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index 45166033f638..d94b85a42356 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -191,6 +191,8 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
 struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
 	ALIAS(MSYSCLK, NULL, "msysclk"),
 	ALIAS(ARMCLK, NULL, "armclk"),
+	ALIAS(MPLL, NULL, "mpll"),
+	ALIAS(EPLL, NULL, "epll"),
 	ALIAS(HCLK, NULL, "hclk"),
 	ALIAS(HCLK_SSMC, NULL, "nand"),
 	ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
@@ -223,9 +225,9 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
 /* S3C2416 specific clocks */
 
 static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
-	[mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
+	[mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
 						LOCKCON0, MPLLCON, NULL),
-	[epll] = PLL(pll_6553, 0, "epll", "epllref",
+	[epll] = PLL(pll_6553, EPLL, "epll", "epllref",
 						LOCKCON1, EPLLCON, NULL),
 };
 
@@ -277,9 +279,9 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
 /* S3C2443 specific clocks */
 
 static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
-	[mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
+	[mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
 						LOCKCON0, MPLLCON, NULL),
-	[epll] = PLL(pll_2126, 0, "epll", "epllref",
+	[epll] = PLL(pll_2126, EPLL, "epll", "epllref",
 						LOCKCON1, EPLLCON, NULL),
 };
 
diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h
index 37e66b054d64..f3ba68a25ecb 100644
--- a/include/dt-bindings/clock/s3c2443.h
+++ b/include/dt-bindings/clock/s3c2443.h
@@ -26,6 +26,8 @@
 #define ARMCLK			4
 #define HCLK			5
 #define PCLK			6
+#define MPLL			7
+#define EPLL			8
 
 /* Special clocks */
 #define SCLK_HSSPI0		16
-- 
2.14.2

[PATCH 9/9] clk: samsung: Remove obsolete clkdev alias support

[Marek Szyprowski]

Remove support for obsolete clkdev alias definition in generic
helper macros for MUX, DIV, GATE and PLL clocks. clkdev aliases can be
still created using samsung_clk_register_alias() function if given
platform still needs them. All current drivers have been converted
not to use *_A-style macros and checked if there are any clients for
the PLL clocks, which had aliases created unconditionally.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-pll.c |  9 ------
 drivers/clk/samsung/clk.c     | 33 ++------------------
 drivers/clk/samsung/clk.h     | 71 ++++++++-----------------------------------
 3 files changed, 15 insertions(+), 98 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 037c61484098..137882657370 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1397,15 +1397,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	}
 
 	samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
-
-	if (!pll_clk->alias)
-		return;
-
-	ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias,
-				     pll_clk->dev_name);
-	if (ret)
-		pr_err("%s: failed to register lookup for %s : %d",
-			__func__, pll_clk->name, ret);
 }
 
 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 7ce0fa86c5ff..484abc84a352 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -181,7 +181,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
 				unsigned int nr_clk)
 {
 	struct clk_hw *clk_hw;
-	unsigned int idx, ret;
+	unsigned int idx;
 
 	for (idx = 0; idx < nr_clk; idx++, list++) {
 		clk_hw = clk_hw_register_mux(NULL, list->name,
@@ -195,15 +195,6 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
 		}
 
 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
-
-		/* register a clock lookup only if a clock alias is specified */
-		if (list->alias) {
-			ret = clk_hw_register_clkdev(clk_hw, list->alias,
-						list->dev_name);
-			if (ret)
-				pr_err("%s: failed to register lookup %s\n",
-						__func__, list->alias);
-		}
 	}
 }
 
@@ -213,7 +204,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
 				unsigned int nr_clk)
 {
 	struct clk_hw *clk_hw;
-	unsigned int idx, ret;
+	unsigned int idx;
 
 	for (idx = 0; idx < nr_clk; idx++, list++) {
 		if (list->table)
@@ -234,15 +225,6 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
 		}
 
 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
-
-		/* register a clock lookup only if a clock alias is specified */
-		if (list->alias) {
-			ret = clk_hw_register_clkdev(clk_hw, list->alias,
-						list->dev_name);
-			if (ret)
-				pr_err("%s: failed to register lookup %s\n",
-						__func__, list->alias);
-		}
 	}
 }
 
@@ -252,7 +234,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
 				unsigned int nr_clk)
 {
 	struct clk_hw *clk_hw;
-	unsigned int idx, ret;
+	unsigned int idx;
 
 	for (idx = 0; idx < nr_clk; idx++, list++) {
 		clk_hw = clk_hw_register_gate(NULL, list->name, list->parent_name,
@@ -264,15 +246,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
 			continue;
 		}
 
-		/* register a clock lookup only if a clock alias is specified */
-		if (list->alias) {
-			ret = clk_hw_register_clkdev(clk_hw, list->alias,
-							list->dev_name);
-			if (ret)
-				pr_err("%s: failed to register lookup %s\n",
-					__func__, list->alias);
-		}
-
 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
 	}
 }
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index d5f0d3f818b6..1cb03b6e2dfd 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -106,7 +106,6 @@ struct samsung_fixed_factor_clock {
 /**
  * struct samsung_mux_clock: information about mux clock
  * @id: platform specific id of the clock.
- * @dev_name: name of the device to which this clock belongs.
  * @name: name of this mux clock.
  * @parent_names: array of pointer to parent clock names.
  * @num_parents: number of parents listed in @parent_names.
@@ -115,11 +114,9 @@ struct samsung_fixed_factor_clock {
  * @shift: starting bit location of the mux control bit-field in @reg.
  * @width: width of the mux control bit-field in @reg.
  * @mux_flags: flags for mux-type clock.
- * @alias: optional clock alias name to be assigned to this clock.
  */
 struct samsung_mux_clock {
 	unsigned int		id;
-	const char		*dev_name;
 	const char		*name;
 	const char		*const *parent_names;
 	u8			num_parents;
@@ -128,13 +125,11 @@ struct samsung_mux_clock {
 	u8			shift;
 	u8			width;
 	u8			mux_flags;
-	const char		*alias;
 };
 
-#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a)	\
+#define __MUX(_id, cname, pnames, o, s, w, f, mf)		\
 	{							\
 		.id		= _id,				\
-		.dev_name	= dname,			\
 		.name		= cname,			\
 		.parent_names	= pnames,			\
 		.num_parents	= ARRAY_SIZE(pnames),		\
@@ -143,36 +138,26 @@ struct samsung_mux_clock {
 		.shift		= s,				\
 		.width		= w,				\
 		.mux_flags	= mf,				\
-		.alias		= a,				\
 	}
 
 #define MUX(_id, cname, pnames, o, s, w)			\
-	__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
-
-#define MUX_A(_id, cname, pnames, o, s, w, a)			\
-	__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
+	__MUX(_id, cname, pnames, o, s, w, 0, 0)
 
 #define MUX_F(_id, cname, pnames, o, s, w, f, mf)		\
-	__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
-
-#define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a)		\
-	__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
+	__MUX(_id, cname, pnames, o, s, w, f, mf)
 
 /**
  * @id: platform specific id of the clock.
  * struct samsung_div_clock: information about div clock
- * @dev_name: name of the device to which this clock belongs.
  * @name: name of this div clock.
  * @parent_name: name of the parent clock.
  * @flags: optional flags for basic clock.
  * @offset: offset of the register for configuring the div.
  * @shift: starting bit location of the div control bit-field in @reg.
  * @div_flags: flags for div-type clock.
- * @alias: optional clock alias name to be assigned to this clock.
  */
 struct samsung_div_clock {
 	unsigned int		id;
-	const char		*dev_name;
 	const char		*name;
 	const char		*parent_name;
 	unsigned long		flags;
@@ -180,14 +165,12 @@ struct samsung_div_clock {
 	u8			shift;
 	u8			width;
 	u8			div_flags;
-	const char		*alias;
 	struct clk_div_table	*table;
 };
 
-#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)	\
+#define __DIV(_id, cname, pname, o, s, w, f, df, t)	\
 	{							\
 		.id		= _id,				\
-		.dev_name	= dname,			\
 		.name		= cname,			\
 		.parent_name	= pname,			\
 		.flags		= f,				\
@@ -195,70 +178,51 @@ struct samsung_div_clock {
 		.shift		= s,				\
 		.width		= w,				\
 		.div_flags	= df,				\
-		.alias		= a,				\
 		.table		= t,				\
 	}
 
 #define DIV(_id, cname, pname, o, s, w)				\
-	__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
-
-#define DIV_A(_id, cname, pname, o, s, w, a)			\
-	__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
+	__DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
 
 #define DIV_F(_id, cname, pname, o, s, w, f, df)		\
-	__DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
+	__DIV(_id, cname, pname, o, s, w, f, df, NULL)
 
 #define DIV_T(_id, cname, pname, o, s, w, t)			\
-	__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
+	__DIV(_id, cname, pname, o, s, w, 0, 0, t)
 
 /**
  * struct samsung_gate_clock: information about gate clock
  * @id: platform specific id of the clock.
- * @dev_name: name of the device to which this clock belongs.
  * @name: name of this gate clock.
  * @parent_name: name of the parent clock.
  * @flags: optional flags for basic clock.
  * @offset: offset of the register for configuring the gate.
  * @bit_idx: bit index of the gate control bit-field in @reg.
  * @gate_flags: flags for gate-type clock.
- * @alias: optional clock alias name to be assigned to this clock.
  */
 struct samsung_gate_clock {
 	unsigned int		id;
-	const char		*dev_name;
 	const char		*name;
 	const char		*parent_name;
 	unsigned long		flags;
 	unsigned long		offset;
 	u8			bit_idx;
 	u8			gate_flags;
-	const char		*alias;
 };
 
-#define __GATE(_id, dname, cname, pname, o, b, f, gf, a)	\
+#define __GATE(_id, cname, pname, o, b, f, gf)			\
 	{							\
 		.id		= _id,				\
-		.dev_name	= dname,			\
 		.name		= cname,			\
 		.parent_name	= pname,			\
 		.flags		= f,				\
 		.offset		= o,				\
 		.bit_idx	= b,				\
 		.gate_flags	= gf,				\
-		.alias		= a,				\
 	}
 
 #define GATE(_id, cname, pname, o, b, f, gf)			\
-	__GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
-
-#define GATE_A(_id, cname, pname, o, b, f, gf, a)		\
-	__GATE(_id, NULL, cname, pname, o, b, f, gf, a)
-
-#define GATE_D(_id, dname, cname, pname, o, b, f, gf)		\
-	__GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
-
-#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a)	\
-	__GATE(_id, dname, cname, pname, o, b, f, gf, a)
+	__GATE(_id, cname, pname, o, b, f, gf)
 
 #define PNAME(x) static const char * const x[] __initconst
 
@@ -275,18 +239,15 @@ struct samsung_clk_reg_dump {
 /**
  * struct samsung_pll_clock: information about pll clock
  * @id: platform specific id of the clock.
- * @dev_name: name of the device to which this clock belongs.
  * @name: name of this pll clock.
  * @parent_name: name of the parent clock.
  * @flags: optional flags for basic clock.
  * @con_offset: offset of the register for configuring the PLL.
  * @lock_offset: offset of the register for locking the PLL.
  * @type: Type of PLL to be registered.
- * @alias: optional clock alias name to be assigned to this clock.
  */
 struct samsung_pll_clock {
 	unsigned int		id;
-	const char		*dev_name;
 	const char		*name;
 	const char		*parent_name;
 	unsigned long		flags;
@@ -294,31 +255,23 @@ struct samsung_pll_clock {
 	int			lock_offset;
 	enum samsung_pll_type	type;
 	const struct samsung_pll_rate_table *rate_table;
-	const char              *alias;
 };
 
-#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con,	\
-		_rtable, _alias)					\
+#define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable)	\
 	{								\
 		.id		= _id,					\
 		.type		= _typ,					\
-		.dev_name	= _dname,				\
 		.name		= _name,				\
 		.parent_name	= _pname,				\
 		.flags		= _flags,				\
 		.con_offset	= _con,					\
 		.lock_offset	= _lock,				\
 		.rate_table	= _rtable,				\
-		.alias		= _alias,				\
 	}
 
 #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable)	\
-	__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,	\
-		_lock, _con, _rtable, _name)
-
-#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
-	__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,	\
-		_lock, _con, _rtable, _alias)
+	__PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock,	\
+	      _con, _rtable)
 
 struct samsung_clock_reg_cache {
 	struct list_head node;
-- 
2.14.2

Re: [PATCH 1/9] clk: samsung: Remove support for obsolete Exynos4212 CPU clock

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Support for Exynos 4212 SoC has been removed by commit bca9085e0ae9 ("ARM:
> dts: exynos: remove Exynos4212 support (dead code)"), so there is no need
> to keep dead code.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c | 33 ++++-----------------------------
>  1 file changed, 4 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index e40b77583c47..9a51ce9a658f 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -1401,24 +1401,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
>         {  0 },
>  };
>
> -static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
> -       { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
> -       { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
> -       { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
> -       { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
> -       { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
> -       { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
> -       {  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
> -       {  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
> -       {  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
> -       {  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
> -       {  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
> -       {  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
> -       {  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
> -       {  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
> -       {  0 },
> -};
> -
>  #define E4412_CPU_DIV1(cores, hpm, copy)                               \
>                 (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
>
> @@ -1533,17 +1515,10 @@ static void __init exynos4_clk_init(struct device_node *np,
>                 samsung_clk_register_fixed_factor(ctx,
>                         exynos4x12_fixed_factor_clks,
>                         ARRAY_SIZE(exynos4x12_fixed_factor_clks));
> -               if (of_machine_is_compatible("samsung,exynos4412")) {
> -                       exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
> -                               mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
> -                               e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
> -                               CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
> -               } else {
> -                       exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
> -                               mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
> -                               e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
> -                               CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
> -               }
> +               exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
> +                       mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
> +                       e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
> +                       CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
>         }
>
>         samsung_clk_register_alias(ctx, exynos4_aliases,

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 1/9] clk: samsung: Remove support for obsolete Exynos4212 CPU clock

[Krzysztof Kozlowski]

On Tue, Oct 3, 2017 at 12:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Support for Exynos 4212 SoC has been removed by commit bca9085e0ae9 ("ARM:
> dts: exynos: remove Exynos4212 support (dead code)"), so there is no need
> to keep dead code.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c | 33 ++++-----------------------------
>  1 file changed, 4 insertions(+), 29 deletions(-)
>

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH 2/9] clk: samsung: Remove clkdev alias support in Exynos4 clk driver

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> All Exynos4 boards have been fully converted to device-tree and use generic
> dt-based CPUfreq driver, so there is no need to create any clkdev aliases
> for the clocks. Drop all the code related to aliases handling.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c | 47 +++++++++------------------------------
>  1 file changed, 10 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 9a51ce9a658f..3fbfd9ed82b7 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -535,9 +535,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __
>
>  /* list of mux clocks supported in all exynos4 soc's */
>  static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
> -       MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> -                       CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
> -                       "mout_apll"),
> +       MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> +                       CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
>         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
>         MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
>         MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
> @@ -838,11 +837,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
>
>  /* list of gate clocks supported in all exynos4 soc's */
>  static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
> -       /*
> -        * After all Exynos4 based platforms are migrated to use device tree,
> -        * the device name and clock alias names specified below for some
> -        * of the clocks can be removed.
> -        */
>         GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
>         GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
>         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
> @@ -1190,20 +1184,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
>                 0),
>  };
>
> -static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
> -       ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
> -       ALIAS(CLK_ARM_CLK, NULL, "armclk"),
> -       ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
> -};
> -
> -static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
> -       ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
> -};
> -
> -static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
> -       ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
> -};
> -
>  /*
>   * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
>   * resides in chipid register space, outside of the clock controller memory
> @@ -1340,14 +1320,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst =
>  };
>
>  static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
> -       [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
> -               APLL_LOCK, APLL_CON0, "fout_apll", NULL),
> -       [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
> -               E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
> -       [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
> -               EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
> -       [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
> -               VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
> +       [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
> +               APLL_LOCK, APLL_CON0, NULL),
> +       [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
> +               E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
> +       [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
> +               EPLL_LOCK, EPLL_CON0, NULL),
> +       [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
> +               VPLL_LOCK, VPLL_CON0, NULL),
>  };
>
>  static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
> @@ -1494,8 +1474,6 @@ static void __init exynos4_clk_init(struct device_node *np,
>                         ARRAY_SIZE(exynos4210_div_clks));
>                 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
>                         ARRAY_SIZE(exynos4210_gate_clks));
> -               samsung_clk_register_alias(ctx, exynos4210_aliases,
> -                       ARRAY_SIZE(exynos4210_aliases));
>                 samsung_clk_register_fixed_factor(ctx,
>                         exynos4210_fixed_factor_clks,
>                         ARRAY_SIZE(exynos4210_fixed_factor_clks));
> @@ -1510,8 +1488,6 @@ static void __init exynos4_clk_init(struct device_node *np,
>                         ARRAY_SIZE(exynos4x12_div_clks));
>                 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
>                         ARRAY_SIZE(exynos4x12_gate_clks));
> -               samsung_clk_register_alias(ctx, exynos4x12_aliases,
> -                       ARRAY_SIZE(exynos4x12_aliases));
>                 samsung_clk_register_fixed_factor(ctx,
>                         exynos4x12_fixed_factor_clks,
>                         ARRAY_SIZE(exynos4x12_fixed_factor_clks));
> @@ -1521,9 +1497,6 @@ static void __init exynos4_clk_init(struct device_node *np,
>                         CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
>         }
>
> -       samsung_clk_register_alias(ctx, exynos4_aliases,
> -                       ARRAY_SIZE(exynos4_aliases));
> -
>         if (soc == EXYNOS4X12)
>                 exynos4x12_core_down_clock();
>         exynos4_clk_sleep_init();

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>


Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 3/9] clk: samsung: Remove double assignment to CLK_ARM_CLK id in Exynos4 driver

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> CLK_ARM_CLK ("armclk") clock is provided by cpu-clk subdriver, which is
> instantiated after creating all divider clocks from exynos4_div_clks
> array. There is no point assigning this id to "div_core2" clock and later
> overwrite with proper "armcpu" clock by cpu-clk subdriver.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos4.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 3fbfd9ed82b7..3bd2d84b2a17 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -721,7 +721,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
>         DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
>         DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
>         DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
> -       DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
> +       DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
>         DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
>         DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
>         DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),

The exynos_register_cpu_clock() calls samsung_clk_add_lookup() which
overwrites the clk_hw. Looks good to me.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

Additionally,
IMO, samsung_clk_add_lookup() might have to check whether
'ctx->clk_data.hws[id]' is NULL or not before adding lookup_id in
order to prevent the overwriting.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 4/9] clk: samsung: Remove clkdev alias support in Exynos5250 clk driver

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> All Exynos5250 boards have been fully converted to device-tree and use
> generic dt-based CPUfreq driver, so there is no need to create any clkdev
> aliases for the clocks. Drop all the code related to aliases handling.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 27a227d6620c..9b073c98a891 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
>         /*
>          * CMU_CPU
>          */
> -       MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> -                                       CLK_SET_RATE_PARENT, 0, "mout_apll"),
> -       MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
> +       MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> +                                       CLK_SET_RATE_PARENT, 0),
> +       MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
>
>         /*
>          * CMU_CORE
>          */
> -       MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
> +       MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
>
>         /*
>          * CMU_TOP
> @@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
>          */
>         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
>         DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
> -       DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
> +       DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
>
>         /*
>          * CMU_TOP
> @@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
>  };
>
>  static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
> -       [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
> -               APLL_LOCK, APLL_CON0, "fout_apll", NULL),
> -       [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
> -               MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
> +       [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> +               APLL_CON0, NULL),
> +       [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
> +               MPLL_CON0, NULL),
>         [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
>                 BPLL_CON0, NULL),
>         [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 5/9] clk: samsung: Drop useless alias in Exynos5420 clk driver

[Chanwoo Choi]

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Drop clkdev alias for "mout_aclk400_mscl" clock. It was not used at all
> and it was probably committed by accident.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 038701a2af4c..45d34f601e9e 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>                                 TOP_SPARE2, 4, 1),
>
>         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
> -       MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
> -                               SRC_TOP0, 4, 2, "aclk400_mscl"),
> +       MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
>         MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
>         MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
>

Also, 'aclk400_mscl' is used as a duplicate on gate clock's name.
Looks good to me.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 6/9] clk: samsung: Rework clkdev alias handling in Exynos5440 driver

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Exynos5440 still uses old, non-dt CPUfreq driver, which requires clkdev
> aliases to get access to proper clocks. Create those aliases using
> samsung_clk_register_alias() function instead of using *_A clock macros,
> which will be removed soon.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5440.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
> index a80f3ef20801..b08bd54c5e76 100644
> --- a/drivers/clk/samsung/clk-exynos5440.c
> +++ b/drivers/clk/samsung/clk-exynos5440.c
> @@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __
>  /* mux clocks */
>  static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
>         MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
> -       MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
> -                       CPU_CLK_STATUS, 0, 1, "armclk"),
> +       MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
>  };
>
>  /* divider clocks */
> @@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
>         PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
>  };
>
> +/*
> + * Clock aliases for legacy clkdev look-up.
> + */
> +static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
> +       ALIAS(CLK_ARM_CLK, NULL, "armclk"),
> +};
> +
>  /* register exynos5440 clocks */
>  static void __init exynos5440_clk_init(struct device_node *np)
>  {
> @@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
>                         ARRAY_SIZE(exynos5440_div_clks));
>         samsung_clk_register_gate(ctx, exynos5440_gate_clks,
>                         ARRAY_SIZE(exynos5440_gate_clks));
> +       samsung_clk_register_alias(ctx, exynos5440_aliases,
> +                                               ARRAY_SIZE(exynos5440_aliases));
>
>         samsung_clk_of_add_provider(np, ctx);
>
> --
> 2.14.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

On this patchset, patch9 removes the *_A macro as the Marek's comment.
So, this patch looks good to me.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 7/9] clk: samsung: Rework clkdev alias handling in S3C2443 driver

[Chanwoo Choi]

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> S3C2443 SoCs still uses old, non-dt CPUfreq driver, which requires clkdev
> aliases to get access to proper clocks. Create those aliases using
> samsung_clk_register_alias() function instead of using *_A clock macros,
> which will be removed soon.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-s3c2443.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
> index abb935c42916..45166033f638 100644
> --- a/drivers/clk/samsung/clk-s3c2443.c
> +++ b/drivers/clk/samsung/clk-s3c2443.c
> @@ -117,8 +117,8 @@ struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
>         MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
>         MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
>         MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
> -       MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"),
> -       MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"),
> +       MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
> +       MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
>         MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
>  };
>
> @@ -189,6 +189,8 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
>  };
>
>  struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
> +       ALIAS(MSYSCLK, NULL, "msysclk"),
> +       ALIAS(ARMCLK, NULL, "armclk"),
>         ALIAS(HCLK, NULL, "hclk"),
>         ALIAS(HCLK_SSMC, NULL, "nand"),
>         ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 8/9] clk: samsung: Add explicit MPLL and EPLL clkdev aliases in S3C2443 driver

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> S3C2443 platform still use non-dt based lookup in some of its drivers to
> get MPLL and EPLL clocks. Till now it worked only because PLL() macro
> implicitely created aliases for all instatiated clocks. This feature will
> be removed, so explicitely create aliases for MPLL and EPLL clocks.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-s3c2443.c   | 10 ++++++----
>  include/dt-bindings/clock/s3c2443.h |  2 ++
>  2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
> index 45166033f638..d94b85a42356 100644
> --- a/drivers/clk/samsung/clk-s3c2443.c
> +++ b/drivers/clk/samsung/clk-s3c2443.c
> @@ -191,6 +191,8 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
>  struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
>         ALIAS(MSYSCLK, NULL, "msysclk"),
>         ALIAS(ARMCLK, NULL, "armclk"),
> +       ALIAS(MPLL, NULL, "mpll"),
> +       ALIAS(EPLL, NULL, "epll"),
>         ALIAS(HCLK, NULL, "hclk"),
>         ALIAS(HCLK_SSMC, NULL, "nand"),
>         ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
> @@ -223,9 +225,9 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
>  /* S3C2416 specific clocks */
>
>  static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
> -       [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
> +       [mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
>                                                 LOCKCON0, MPLLCON, NULL),
> -       [epll] = PLL(pll_6553, 0, "epll", "epllref",
> +       [epll] = PLL(pll_6553, EPLL, "epll", "epllref",
>                                                 LOCKCON1, EPLLCON, NULL),
>  };
>
> @@ -277,9 +279,9 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
>  /* S3C2443 specific clocks */
>
>  static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
> -       [mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
> +       [mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
>                                                 LOCKCON0, MPLLCON, NULL),
> -       [epll] = PLL(pll_2126, 0, "epll", "epllref",
> +       [epll] = PLL(pll_2126, EPLL, "epll", "epllref",
>                                                 LOCKCON1, EPLLCON, NULL),
>  };
>
> diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h
> index 37e66b054d64..f3ba68a25ecb 100644
> --- a/include/dt-bindings/clock/s3c2443.h
> +++ b/include/dt-bindings/clock/s3c2443.h
> @@ -26,6 +26,8 @@
>  #define ARMCLK                 4
>  #define HCLK                   5
>  #define PCLK                   6
> +#define MPLL                   7
> +#define EPLL                   8
>
>  /* Special clocks */
>  #define SCLK_HSSPI0            16


When using PLL() macro, pll uses the 'name' as for both 'name' and 'alias'.
The patch9 removes the registration of PLL's alias in the
_samsung_clk_register_pll().
So, this patch looks good to me for patch9.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 9/9] clk: samsung: Remove obsolete clkdev alias support

[Chanwoo Choi]

Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Remove support for obsolete clkdev alias definition in generic
> helper macros for MUX, DIV, GATE and PLL clocks. clkdev aliases can be
> still created using samsung_clk_register_alias() function if given
> platform still needs them. All current drivers have been converted
> not to use *_A-style macros and checked if there are any clients for
> the PLL clocks, which had aliases created unconditionally.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-pll.c |  9 ------
>  drivers/clk/samsung/clk.c     | 33 ++------------------
>  drivers/clk/samsung/clk.h     | 71 ++++++++-----------------------------------
>  3 files changed, 15 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 037c61484098..137882657370 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -1397,15 +1397,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>         }
>
>         samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
> -
> -       if (!pll_clk->alias)
> -               return;
> -
> -       ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias,
> -                                    pll_clk->dev_name);
> -       if (ret)
> -               pr_err("%s: failed to register lookup for %s : %d",
> -                       __func__, pll_clk->name, ret);
>  }
>
>  void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
> index 7ce0fa86c5ff..484abc84a352 100644
> --- a/drivers/clk/samsung/clk.c
> +++ b/drivers/clk/samsung/clk.c
> @@ -181,7 +181,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
>                                 unsigned int nr_clk)
>  {
>         struct clk_hw *clk_hw;
> -       unsigned int idx, ret;
> +       unsigned int idx;
>
>         for (idx = 0; idx < nr_clk; idx++, list++) {
>                 clk_hw = clk_hw_register_mux(NULL, list->name,
> @@ -195,15 +195,6 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
>                 }
>
>                 samsung_clk_add_lookup(ctx, clk_hw, list->id);
> -
> -               /* register a clock lookup only if a clock alias is specified */
> -               if (list->alias) {
> -                       ret = clk_hw_register_clkdev(clk_hw, list->alias,
> -                                               list->dev_name);
> -                       if (ret)
> -                               pr_err("%s: failed to register lookup %s\n",
> -                                               __func__, list->alias);
> -               }
>         }
>  }
>
> @@ -213,7 +204,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
>                                 unsigned int nr_clk)
>  {
>         struct clk_hw *clk_hw;
> -       unsigned int idx, ret;
> +       unsigned int idx;
>
>         for (idx = 0; idx < nr_clk; idx++, list++) {
>                 if (list->table)
> @@ -234,15 +225,6 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
>                 }
>
>                 samsung_clk_add_lookup(ctx, clk_hw, list->id);
> -
> -               /* register a clock lookup only if a clock alias is specified */
> -               if (list->alias) {
> -                       ret = clk_hw_register_clkdev(clk_hw, list->alias,
> -                                               list->dev_name);
> -                       if (ret)
> -                               pr_err("%s: failed to register lookup %s\n",
> -                                               __func__, list->alias);
> -               }
>         }
>  }
>
> @@ -252,7 +234,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
>                                 unsigned int nr_clk)
>  {
>         struct clk_hw *clk_hw;
> -       unsigned int idx, ret;
> +       unsigned int idx;
>
>         for (idx = 0; idx < nr_clk; idx++, list++) {
>                 clk_hw = clk_hw_register_gate(NULL, list->name, list->parent_name,
> @@ -264,15 +246,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
>                         continue;
>                 }
>
> -               /* register a clock lookup only if a clock alias is specified */
> -               if (list->alias) {
> -                       ret = clk_hw_register_clkdev(clk_hw, list->alias,
> -                                                       list->dev_name);
> -                       if (ret)
> -                               pr_err("%s: failed to register lookup %s\n",
> -                                       __func__, list->alias);
> -               }
> -
>                 samsung_clk_add_lookup(ctx, clk_hw, list->id);
>         }
>  }
> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
> index d5f0d3f818b6..1cb03b6e2dfd 100644
> --- a/drivers/clk/samsung/clk.h
> +++ b/drivers/clk/samsung/clk.h
> @@ -106,7 +106,6 @@ struct samsung_fixed_factor_clock {
>  /**
>   * struct samsung_mux_clock: information about mux clock
>   * @id: platform specific id of the clock.
> - * @dev_name: name of the device to which this clock belongs.
>   * @name: name of this mux clock.
>   * @parent_names: array of pointer to parent clock names.
>   * @num_parents: number of parents listed in @parent_names.
> @@ -115,11 +114,9 @@ struct samsung_fixed_factor_clock {
>   * @shift: starting bit location of the mux control bit-field in @reg.
>   * @width: width of the mux control bit-field in @reg.
>   * @mux_flags: flags for mux-type clock.
> - * @alias: optional clock alias name to be assigned to this clock.
>   */
>  struct samsung_mux_clock {
>         unsigned int            id;
> -       const char              *dev_name;
>         const char              *name;
>         const char              *const *parent_names;
>         u8                      num_parents;
> @@ -128,13 +125,11 @@ struct samsung_mux_clock {
>         u8                      shift;
>         u8                      width;
>         u8                      mux_flags;
> -       const char              *alias;
>  };
>
> -#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a)    \
> +#define __MUX(_id, cname, pnames, o, s, w, f, mf)              \
>         {                                                       \
>                 .id             = _id,                          \
> -               .dev_name       = dname,                        \
>                 .name           = cname,                        \
>                 .parent_names   = pnames,                       \
>                 .num_parents    = ARRAY_SIZE(pnames),           \
> @@ -143,36 +138,26 @@ struct samsung_mux_clock {
>                 .shift          = s,                            \
>                 .width          = w,                            \
>                 .mux_flags      = mf,                           \
> -               .alias          = a,                            \
>         }
>
>  #define MUX(_id, cname, pnames, o, s, w)                       \
> -       __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
> -
> -#define MUX_A(_id, cname, pnames, o, s, w, a)                  \
> -       __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
> +       __MUX(_id, cname, pnames, o, s, w, 0, 0)
>
>  #define MUX_F(_id, cname, pnames, o, s, w, f, mf)              \
> -       __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
> -
> -#define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a)          \
> -       __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
> +       __MUX(_id, cname, pnames, o, s, w, f, mf)
>
>  /**
>   * @id: platform specific id of the clock.
>   * struct samsung_div_clock: information about div clock
> - * @dev_name: name of the device to which this clock belongs.
>   * @name: name of this div clock.
>   * @parent_name: name of the parent clock.
>   * @flags: optional flags for basic clock.
>   * @offset: offset of the register for configuring the div.
>   * @shift: starting bit location of the div control bit-field in @reg.
>   * @div_flags: flags for div-type clock.
> - * @alias: optional clock alias name to be assigned to this clock.
>   */
>  struct samsung_div_clock {
>         unsigned int            id;
> -       const char              *dev_name;
>         const char              *name;
>         const char              *parent_name;
>         unsigned long           flags;
> @@ -180,14 +165,12 @@ struct samsung_div_clock {
>         u8                      shift;
>         u8                      width;
>         u8                      div_flags;
> -       const char              *alias;
>         struct clk_div_table    *table;
>  };
>
> -#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)  \
> +#define __DIV(_id, cname, pname, o, s, w, f, df, t)    \
>         {                                                       \
>                 .id             = _id,                          \
> -               .dev_name       = dname,                        \
>                 .name           = cname,                        \
>                 .parent_name    = pname,                        \
>                 .flags          = f,                            \
> @@ -195,70 +178,51 @@ struct samsung_div_clock {
>                 .shift          = s,                            \
>                 .width          = w,                            \
>                 .div_flags      = df,                           \
> -               .alias          = a,                            \
>                 .table          = t,                            \
>         }
>
>  #define DIV(_id, cname, pname, o, s, w)                                \
> -       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
> -
> -#define DIV_A(_id, cname, pname, o, s, w, a)                   \
> -       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
> +       __DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
>
>  #define DIV_F(_id, cname, pname, o, s, w, f, df)               \
> -       __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
> +       __DIV(_id, cname, pname, o, s, w, f, df, NULL)
>
>  #define DIV_T(_id, cname, pname, o, s, w, t)                   \
> -       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
> +       __DIV(_id, cname, pname, o, s, w, 0, 0, t)
>
>  /**
>   * struct samsung_gate_clock: information about gate clock
>   * @id: platform specific id of the clock.
> - * @dev_name: name of the device to which this clock belongs.
>   * @name: name of this gate clock.
>   * @parent_name: name of the parent clock.
>   * @flags: optional flags for basic clock.
>   * @offset: offset of the register for configuring the gate.
>   * @bit_idx: bit index of the gate control bit-field in @reg.
>   * @gate_flags: flags for gate-type clock.
> - * @alias: optional clock alias name to be assigned to this clock.
>   */
>  struct samsung_gate_clock {
>         unsigned int            id;
> -       const char              *dev_name;
>         const char              *name;
>         const char              *parent_name;
>         unsigned long           flags;
>         unsigned long           offset;
>         u8                      bit_idx;
>         u8                      gate_flags;
> -       const char              *alias;
>  };
>
> -#define __GATE(_id, dname, cname, pname, o, b, f, gf, a)       \
> +#define __GATE(_id, cname, pname, o, b, f, gf)                 \
>         {                                                       \
>                 .id             = _id,                          \
> -               .dev_name       = dname,                        \
>                 .name           = cname,                        \
>                 .parent_name    = pname,                        \
>                 .flags          = f,                            \
>                 .offset         = o,                            \
>                 .bit_idx        = b,                            \
>                 .gate_flags     = gf,                           \
> -               .alias          = a,                            \
>         }
>
>  #define GATE(_id, cname, pname, o, b, f, gf)                   \
> -       __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
> -
> -#define GATE_A(_id, cname, pname, o, b, f, gf, a)              \
> -       __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
> -
> -#define GATE_D(_id, dname, cname, pname, o, b, f, gf)          \
> -       __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
> -
> -#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a)      \
> -       __GATE(_id, dname, cname, pname, o, b, f, gf, a)
> +       __GATE(_id, cname, pname, o, b, f, gf)
>
>  #define PNAME(x) static const char * const x[] __initconst
>
> @@ -275,18 +239,15 @@ struct samsung_clk_reg_dump {
>  /**
>   * struct samsung_pll_clock: information about pll clock
>   * @id: platform specific id of the clock.
> - * @dev_name: name of the device to which this clock belongs.
>   * @name: name of this pll clock.
>   * @parent_name: name of the parent clock.
>   * @flags: optional flags for basic clock.
>   * @con_offset: offset of the register for configuring the PLL.
>   * @lock_offset: offset of the register for locking the PLL.
>   * @type: Type of PLL to be registered.
> - * @alias: optional clock alias name to be assigned to this clock.
>   */
>  struct samsung_pll_clock {
>         unsigned int            id;
> -       const char              *dev_name;
>         const char              *name;
>         const char              *parent_name;
>         unsigned long           flags;
> @@ -294,31 +255,23 @@ struct samsung_pll_clock {
>         int                     lock_offset;
>         enum samsung_pll_type   type;
>         const struct samsung_pll_rate_table *rate_table;
> -       const char              *alias;
>  };
>
> -#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con,   \
> -               _rtable, _alias)                                        \
> +#define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable)  \
>         {                                                               \
>                 .id             = _id,                                  \
>                 .type           = _typ,                                 \
> -               .dev_name       = _dname,                               \
>                 .name           = _name,                                \
>                 .parent_name    = _pname,                               \
>                 .flags          = _flags,                               \
>                 .con_offset     = _con,                                 \
>                 .lock_offset    = _lock,                                \
>                 .rate_table     = _rtable,                              \
> -               .alias          = _alias,                               \
>         }
>
>  #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable)    \
> -       __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
> -               _lock, _con, _rtable, _name)
> -
> -#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
> -       __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
> -               _lock, _con, _rtable, _alias)
> +       __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock,    \
> +             _con, _rtable)
>
>  struct samsung_clock_reg_cache {
>         struct list_head node;

Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 0/9] Various cleanups for Samsung clocks drivers

[Sylwester Nawrocki]

On 10/03/2017 12:00 PM, Marek Szyprowski wrote:
> Patch summary:
> 
> Marek Szyprowski (9):
>   clk: samsung: Remove support for obsolete Exynos4212 CPU clock
>   clk: samsung: Remove clkdev alias support in Exynos4 clk driver
>   clk: samsung: Remove double assignment to CLK_ARM_CLK id in Exynos4
>     driver
>   clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
>   clk: samsung: Drop useless alias in Exynos5420 clk driver
>   clk: samsung: Rework clkdev alias handling in Exynos5440 driver
>   clk: samsung: Rework clkdev alias handling in S3C2443 driver
>   clk: samsung: Add explicit MPLL and EPLL clkdev aliases in S3C2443
>     driver
>   clk: samsung: Remove obsolete clkdev alias support

I have applied this patch set, thanks.