[PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Rodrigo Vivi]

This is heavily based on a initial patch provided by Ville
plus all changes provided later by Ander.

As Geminilake, Cannonlake also supports 2 pixels per clock.

Different from Geminilake we are not implementing the 99% Wa.
But we can revisit that decision later if we find out
any limitation on later CNL SKUs.

v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
minimum acceptable cdclk instead of "minimum dotclock")'

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c   | 7 +------
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_pm.c      | 3 ++-
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index d6befabd6ed5..eabaf57b83ef 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1995,12 +1995,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
 	if (INTEL_GEN(dev_priv) >= 10)
-		/*
-		 * FIXME: Allow '2 * max_cdclk_freq'
-		 * once DDI clock voltage requirements are
-		 * handled correctly.
-		 */
-		return max_cdclk_freq;
+		return 2 * max_cdclk_freq;
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
 		 * FIXME: Limiting to 99% as a temporary workaround. See
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 026fa5460fe5..487b43ba3139 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12801,7 +12801,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
 	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(dev_priv))
+	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		max_dotclk *= 2;
 
 	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c66af09e27a7..52c4c194aa51 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *cstate)
 {
+	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	struct drm_crtc_state *crtc_state = &cstate->base;
 	struct drm_atomic_state *state = crtc_state->state;
 	struct drm_plane *plane;
@@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		dotclk *= 2;
 
 	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
-- 
2.13.5

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Re: [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Rodrigo Vivi]

On Tue, Sep 26, 2017 at 12:43 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> This is heavily based on a initial patch provided by Ville
> plus all changes provided later by Ander.
>
> As Geminilake, Cannonlake also supports 2 pixels per clock.
>
> Different from Geminilake we are not implementing the 99% Wa.
> But we can revisit that decision later if we find out
> any limitation on later CNL SKUs.
>
> v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
> minimum acceptable cdclk instead of "minimum dotclock")'
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c   | 7 +------
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c      | 3 ++-
>  3 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index d6befabd6ed5..eabaf57b83ef 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1995,12 +1995,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>         int max_cdclk_freq = dev_priv->max_cdclk_freq;
>
>         if (INTEL_GEN(dev_priv) >= 10)
> -               /*
> -                * FIXME: Allow '2 * max_cdclk_freq'
> -                * once DDI clock voltage requirements are
> -                * handled correctly.
> -                */

this actually depends on https://patchwork.freedesktop.org/series/30922/

So I will probably resend this after that patch is merged, but I'd
appreciate early reviews.

> -               return max_cdclk_freq;
> +               return 2 * max_cdclk_freq;
>         else if (IS_GEMINILAKE(dev_priv))
>                 /*
>                  * FIXME: Limiting to 99% as a temporary workaround. See
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 026fa5460fe5..487b43ba3139 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12801,7 +12801,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
>         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
>         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
>
> -       if (IS_GEMINILAKE(dev_priv))
> +       if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>                 max_dotclk *= 2;
>
>         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c66af09e27a7..52c4c194aa51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
>  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>                                   struct intel_crtc_state *cstate)
>  {
> +       struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>         struct drm_crtc_state *crtc_state = &cstate->base;
>         struct drm_atomic_state *state = crtc_state->state;
>         struct drm_plane *plane;
> @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>         crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>         dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>
> -       if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> +       if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>                 dotclk *= 2;
>
>         pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
> --
> 2.13.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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✓ Fi.CI.BAT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
URL   : https://patchwork.freedesktop.org/series/30924/
State : success

== Summary ==

Series 30924v1 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/30924/revisions/1/mbox/

Test pm_rpm:
        Subgroup basic-rte:
                dmesg-warn -> PASS       (fi-cfl-s) fdo#102294
Test drv_module_reload:
        Subgroup basic-reload-inject:
                pass       -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:437s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:474s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:426s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:518s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:511s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:493s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:497s
fi-cfl-s         total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  time:544s
fi-cnl-y         total:289  pass:257  dwarn:0   dfail:0   fail:5   skip:27  time:641s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:419s
fi-glk-1         total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  time:626s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:425s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:402s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:430s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:489s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:470s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:470s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:572s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:586s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:544s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:450s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:748s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:488s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:472s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:561s
fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:412s

c4c623d58e38d49e692dc9141250b35e39170e6b drm-tip: 2017y-09m-26d-16h-37m-12s UTC integration manifest
a12c05ce96e5 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5825/
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✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
URL   : https://patchwork.freedesktop.org/series/30924/
State : success

== Summary ==

Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912
Test kms_flip:
        Subgroup flip-vs-expired-vblank:
                fail       -> PASS       (shard-hsw) fdo#102367
        Subgroup plain-flip-ts-check-interruptible:
                fail       -> PASS       (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102367 https://bugs.freedesktop.org/show_bug.cgi?id=102367

shard-hsw        total:2429 pass:1336 dwarn:1   dfail:0   fail:9   skip:1083 time:9986s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5825/shards.html
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Re: [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Paulo Zanoni]

Em Ter, 2017-09-26 às 12:43 -0700, Rodrigo Vivi escreveu:
> This is heavily based on a initial patch provided by Ville
> plus all changes provided later by Ander.
> 
> As Geminilake, Cannonlake also supports 2 pixels per clock.
> 
> Different from Geminilake we are not implementing the 99% Wa.
> But we can revisit that decision later if we find out
> any limitation on later CNL SKUs.
> 
> v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
> minimum acceptable cdclk instead of "minimum dotclock")'

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c   | 7 +------
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c      | 3 ++-
>  3 files changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index d6befabd6ed5..eabaf57b83ef 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1995,12 +1995,7 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
>  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
>  
>  	if (INTEL_GEN(dev_priv) >= 10)
> -		/*
> -		 * FIXME: Allow '2 * max_cdclk_freq'
> -		 * once DDI clock voltage requirements are
> -		 * handled correctly.
> -		 */
> -		return max_cdclk_freq;
> +		return 2 * max_cdclk_freq;
>  	else if (IS_GEMINILAKE(dev_priv))
>  		/*
>  		 * FIXME: Limiting to 99% as a temporary workaround.
> See
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 026fa5460fe5..487b43ba3139 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12801,7 +12801,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state
>  	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
>  	max_dotclk = to_intel_atomic_state(crtc_state->base.state)-
> >cdclk.logical.cdclk;
>  
> -	if (IS_GEMINILAKE(dev_priv))
> +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		max_dotclk *= 2;
>  
>  	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index c66af09e27a7..52c4c194aa51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct
> intel_crtc_state *crtc_state)
>  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>  				  struct intel_crtc_state *cstate)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(intel_crtc-
> >base.dev);
>  	struct drm_crtc_state *crtc_state = &cstate->base;
>  	struct drm_atomic_state *state = crtc_state->state;
>  	struct drm_plane *plane;
> @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct
> intel_crtc *intel_crtc,
>  	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>  	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>  
> -	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		dotclk *= 2;
>  
>  	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk,
> pipe_downscale);
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[PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Rodrigo Vivi]

This is heavily based on a initial patch provided by Ville
plus all changes provided later by Ander.

As Geminilake, Cannonlake also supports 2 pixels per clock.

Different from Geminilake we are not implementing the 99% Wa.
But we can revisit that decision later if we find out
any limitation on later CNL SKUs.

v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
minimum acceptable cdclk instead of "minimum dotclock")'

v3: When fixing HDMI on CNL I noticed that I missed to convert
    back the doubled pixel rate to cdclk.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c   | 14 ++------------
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_pm.c      |  3 ++-
 3 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 58ee4dd07cf6..bdb95b75c9d4 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
 				     int pixel_rate)
 {
 	if (INTEL_GEN(dev_priv) >= 10)
-		/*
-		 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
-		 * once DDI clock voltage requirements are
-		 * handled correctly.
-		 */
-		return pixel_rate;
+		return DIV_ROUND_UP(pixel_rate, 2);
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
 		 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
@@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
 	if (INTEL_GEN(dev_priv) >= 10)
-		/*
-		 * FIXME: Allow '2 * max_cdclk_freq'
-		 * once DDI clock voltage requirements are
-		 * handled correctly.
-		 */
-		return max_cdclk_freq;
+		return 2 * max_cdclk_freq;
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
 		 * FIXME: Limiting to 99% as a temporary workaround. See
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b7a6ddc6a66d..644759aff069 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
 	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(dev_priv))
+	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		max_dotclk *= 2;
 
 	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 171b21f6c4ad..ede871b7982e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *cstate)
 {
+	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	struct drm_crtc_state *crtc_state = &cstate->base;
 	struct drm_atomic_state *state = crtc_state->state;
 	struct drm_plane *plane;
@@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		dotclk *= 2;
 
 	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
-- 
2.13.5

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✗ Fi.CI.BAT: failure for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
URL   : https://patchwork.freedesktop.org/series/30924/
State : failure

== Summary ==

Series 30924v2 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/30924/revisions/2/mbox/

Test kms_busy:
        Subgroup basic-flip-b:
                pass       -> DMESG-WARN (fi-skl-6700k)
Test kms_frontbuffer_tracking:
        Subgroup basic:
                pass       -> DMESG-WARN (fi-skl-6700k)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> INCOMPLETE (fi-kbl-7560u)

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:457s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:471s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:401s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:559s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:290s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:528s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:532s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:543s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:528s
fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:558s
fi-cnl-y         total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  time:609s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:429s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:598s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:438s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:420s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:464s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:507s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:473s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:502s
fi-kbl-7560u     total:245  pass:228  dwarn:0   dfail:0   fail:0   skip:16 
fi-kbl-7567u     total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  time:487s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:585s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:663s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:470s
fi-skl-6700k     total:289  pass:263  dwarn:2   dfail:0   fail:0   skip:24  time:535s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:509s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:470s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:580s
fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:427s

654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest
c879014a35c0 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5889/
_______________________________________________
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✓ Fi.CI.BAT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
URL   : https://patchwork.freedesktop.org/series/30924/
State : success

== Summary ==

Series 30924v2 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
https://patchwork.freedesktop.org/api/1.0/series/30924/revisions/2/mbox/

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:457s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:475s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:399s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:564s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:288s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:531s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:529s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:544s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:529s
fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:564s
fi-cnl-y         total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  time:616s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:436s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:591s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:440s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:417s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:468s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:507s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:478s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:501s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:573s
fi-kbl-7567u     total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  time:494s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:587s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:654s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:473s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:536s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:522s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:478s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:579s
fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:430s

654360cf73feea27f7ed5bfa2e5b2fa5ede2e8ec drm-tip: 2017y-10m-03d-17h-55m-08s UTC integration manifest
5bff72096d0d drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5890/
_______________________________________________
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✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
URL   : https://patchwork.freedesktop.org/series/30924/
State : success

== Summary ==

Test perf:
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252 +1

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hsw        total:2429 pass:1314 dwarn:7   dfail:0   fail:25  skip:1083 time:10019s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5889/shards.html
_______________________________________________
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✓ Fi.CI.IGT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. (rev2)
URL   : https://patchwork.freedesktop.org/series/30924/
State : success

== Summary ==

Test perf:
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hsw        total:2429 pass:1315 dwarn:7   dfail:0   fail:24  skip:1083 time:9997s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5890/shards.html
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Re: [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Paulo Zanoni]

Em Ter, 2017-10-03 às 15:31 -0700, Rodrigo Vivi escreveu:
> This is heavily based on a initial patch provided by Ville
> plus all changes provided later by Ander.
> 
> As Geminilake, Cannonlake also supports 2 pixels per clock.
> 
> Different from Geminilake we are not implementing the 99% Wa.
> But we can revisit that decision later if we find out
> any limitation on later CNL SKUs.
> 
> v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
> minimum acceptable cdclk instead of "minimum dotclock")'
> 
> v3: When fixing HDMI on CNL I noticed that I missed to convert
>     back the doubled pixel rate to cdclk.
> 

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c   | 14 ++------------
>  drivers/gpu/drm/i915/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c      |  3 ++-
>  3 files changed, 5 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 58ee4dd07cf6..bdb95b75c9d4 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct
> drm_i915_private *dev_priv,
>  				     int pixel_rate)
>  {
>  	if (INTEL_GEN(dev_priv) >= 10)
> -		/*
> -		 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
> -		 * once DDI clock voltage requirements are
> -		 * handled correctly.
> -		 */
> -		return pixel_rate;
> +		return DIV_ROUND_UP(pixel_rate, 2);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		/*
>  		 * FIXME: Avoid using a pixel clock that is more
> than 99% of the cdclk
> @@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
>  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
>  
>  	if (INTEL_GEN(dev_priv) >= 10)
> -		/*
> -		 * FIXME: Allow '2 * max_cdclk_freq'
> -		 * once DDI clock voltage requirements are
> -		 * handled correctly.
> -		 */
> -		return max_cdclk_freq;
> +		return 2 * max_cdclk_freq;
>  	else if (IS_GEMINILAKE(dev_priv))
>  		/*
>  		 * FIXME: Limiting to 99% as a temporary workaround.
> See
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b7a6ddc6a66d..644759aff069 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state
>  	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
>  	max_dotclk = to_intel_atomic_state(crtc_state->base.state)-
> >cdclk.logical.cdclk;
>  
> -	if (IS_GEMINILAKE(dev_priv))
> +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		max_dotclk *= 2;
>  
>  	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 171b21f6c4ad..ede871b7982e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct
> intel_crtc_state *crtc_state)
>  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>  				  struct intel_crtc_state *cstate)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(intel_crtc-
> >base.dev);
>  	struct drm_crtc_state *crtc_state = &cstate->base;
>  	struct drm_atomic_state *state = crtc_state->state;
>  	struct drm_plane *plane;
> @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct
> intel_crtc *intel_crtc,
>  	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>  	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>  
> -	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		dotclk *= 2;
>  
>  	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk,
> pipe_downscale);
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Re: [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

[Rodrigo Vivi]

On Wed, Oct 04, 2017 at 11:28:26PM +0000, Paulo Zanoni wrote:
> Em Ter, 2017-10-03 às 15:31 -0700, Rodrigo Vivi escreveu:
> > This is heavily based on a initial patch provided by Ville
> > plus all changes provided later by Ander.
> > 
> > As Geminilake, Cannonlake also supports 2 pixels per clock.
> > 
> > Different from Geminilake we are not implementing the 99% Wa.
> > But we can revisit that decision later if we find out
> > any limitation on later CNL SKUs.
> > 
> > v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
> > minimum acceptable cdclk instead of "minimum dotclock")'
> > 
> > v3: When fixing HDMI on CNL I noticed that I missed to convert
> >     back the doubled pixel rate to cdclk.
> > 
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

I just merged to dinq now that dvfs also got merged.
Thanks for reviwing.

> 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c   | 14 ++------------
> >  drivers/gpu/drm/i915/intel_display.c |  2 +-
> >  drivers/gpu/drm/i915/intel_pm.c      |  3 ++-
> >  3 files changed, 5 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 58ee4dd07cf6..bdb95b75c9d4 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct
> > drm_i915_private *dev_priv,
> >  				     int pixel_rate)
> >  {
> >  	if (INTEL_GEN(dev_priv) >= 10)
> > -		/*
> > -		 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
> > -		 * once DDI clock voltage requirements are
> > -		 * handled correctly.
> > -		 */
> > -		return pixel_rate;
> > +		return DIV_ROUND_UP(pixel_rate, 2);
> >  	else if (IS_GEMINILAKE(dev_priv))
> >  		/*
> >  		 * FIXME: Avoid using a pixel clock that is more
> > than 99% of the cdclk
> > @@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct
> > drm_i915_private *dev_priv)
> >  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >  
> >  	if (INTEL_GEN(dev_priv) >= 10)
> > -		/*
> > -		 * FIXME: Allow '2 * max_cdclk_freq'
> > -		 * once DDI clock voltage requirements are
> > -		 * handled correctly.
> > -		 */
> > -		return max_cdclk_freq;
> > +		return 2 * max_cdclk_freq;
> >  	else if (IS_GEMINILAKE(dev_priv))
> >  		/*
> >  		 * FIXME: Limiting to 99% as a temporary workaround.
> > See
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index b7a6ddc6a66d..644759aff069 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> > struct intel_crtc_state *crtc_state
> >  	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> >  	max_dotclk = to_intel_atomic_state(crtc_state->base.state)-
> > >cdclk.logical.cdclk;
> >  
> > -	if (IS_GEMINILAKE(dev_priv))
> > +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> >  		max_dotclk *= 2;
> >  
> >  	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 171b21f6c4ad..ede871b7982e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct
> > intel_crtc_state *crtc_state)
> >  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> >  				  struct intel_crtc_state *cstate)
> >  {
> > +	struct drm_i915_private *dev_priv = to_i915(intel_crtc-
> > >base.dev);
> >  	struct drm_crtc_state *crtc_state = &cstate->base;
> >  	struct drm_atomic_state *state = crtc_state->state;
> >  	struct drm_plane *plane;
> > @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct
> > intel_crtc *intel_crtc,
> >  	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> >  	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> >  
> > -	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> > +	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> >  		dotclk *= 2;
> >  
> >  	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk,
> > pipe_downscale);
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