From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, mark.rutland@arm.com, robh@kernel.org, will.deacon@arm.com, sudeep.holla@arm.com, frowand.list@gmail.com, devicetree@vger.kernel.org, Jonathan.Cameron@huawei.com, marc.zyngier@arm.com, peterz@infradead.org, mathieu.poirier@linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v7 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU Date: Fri, 6 Oct 2017 11:36:09 +0100 [thread overview] Message-ID: <20171006103610.11853-6-suzuki.poulose@arm.com> (raw) In-Reply-To: <20171006103610.11853-1-suzuki.poulose@arm.com> This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: devicetree@vger.kernel.org Cc: frowand.list@gmail.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Changes since V3: - Fixed node name in the example, suggested by Rob --- .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt new file mode 100644 index 000000000000..6efabba530f1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt @@ -0,0 +1,27 @@ +* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores +with a shared L3 memory system, control logic and external interfaces to +form a multicore cluster. The PMU enables to gather various statistics on +the operations of the DSU. The PMU provides independent 32bit counters that +can count any of the supported events, along with a 64bit cycle counter. +The PMU is accessed via CPU system registers and has no MMIO component. + +** DSU PMU required properties: + +- compatible : should be one of : + + "arm,dsu-pmu" + +- interrupts : Exactly 1 SPI must be listed. + +- cpus : List of phandles for the CPUs connected to this DSU instance. + + +** Example: + +dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&cpu_0>, <&cpu_1>; +}; -- 2.13.6
WARNING: multiple messages have this Message-ID (diff)
From: suzuki.poulose@arm.com (Suzuki K Poulose) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU Date: Fri, 6 Oct 2017 11:36:09 +0100 [thread overview] Message-ID: <20171006103610.11853-6-suzuki.poulose@arm.com> (raw) In-Reply-To: <20171006103610.11853-1-suzuki.poulose@arm.com> This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: devicetree at vger.kernel.org Cc: frowand.list at gmail.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Changes since V3: - Fixed node name in the example, suggested by Rob --- .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt new file mode 100644 index 000000000000..6efabba530f1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt @@ -0,0 +1,27 @@ +* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores +with a shared L3 memory system, control logic and external interfaces to +form a multicore cluster. The PMU enables to gather various statistics on +the operations of the DSU. The PMU provides independent 32bit counters that +can count any of the supported events, along with a 64bit cycle counter. +The PMU is accessed via CPU system registers and has no MMIO component. + +** DSU PMU required properties: + +- compatible : should be one of : + + "arm,dsu-pmu" + +- interrupts : Exactly 1 SPI must be listed. + +- cpus : List of phandles for the CPUs connected to this DSU instance. + + +** Example: + +dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&cpu_0>, <&cpu_1>; +}; -- 2.13.6
next prev parent reply other threads:[~2017-10-06 10:37 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-10-06 10:36 [PATCH v7 0/6] perf: Support for ARM DynamIQ Shared Unit Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose 2017-10-06 10:36 ` [PATCH v7 1/6] perf: Export perf_event_update_userpage Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose 2017-10-06 10:36 ` [PATCH v7 2/6] of: Add helper for mapping device node to logical CPU number Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose 2017-10-06 10:36 ` [PATCH v7 3/6] coresight: of: Use of_cpu_node_to_id helper Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose 2017-10-09 2:58 ` Leo Yan 2017-10-09 2:58 ` Leo Yan 2017-10-10 9:38 ` Suzuki K Poulose 2017-10-10 9:38 ` Suzuki K Poulose 2017-10-06 10:36 ` [PATCH v7 4/6] irqchip: gic-v3: " Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose [this message] 2017-10-06 10:36 ` [PATCH v7 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU Suzuki K Poulose 2017-10-06 10:36 ` [PATCH v7 6/6] perf: ARM DynamIQ Shared Unit PMU support Suzuki K Poulose 2017-10-06 10:36 ` Suzuki K Poulose
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