* [PATCH 2/3] drm/i915/dp: centralize max source rate conditions more
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
@ 2017-10-09 9:29 ` Jani Nikula
2017-10-10 18:35 ` Manasi Navare
2017-10-09 9:29 ` [PATCH 3/3] drm/i915/dp: limit sink rates based on rate Jani Nikula
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2017-10-09 9:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Turn intel_dp_source_supports_hbr2() into a simple helper to query the
pre-filled source rates array, and move the conditions about which
platforms support which rates to the single point of truth in
intel_dp_set_source_rates().
This also reduces the code paths you have to think about in the source
rates initialization in intel_dp_set_source_rates(), making it easier to
grasp.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca48bce23a6f..09d75df497c0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -254,15 +254,15 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
- } else {
+ } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
+ IS_BROADWELL(dev_priv)) {
source_rates = default_rates;
size = ARRAY_SIZE(default_rates);
+ } else {
+ source_rates = default_rates;
+ size = ARRAY_SIZE(default_rates) - 1;
}
- /* This depends on the fact that 5.4 is last value in the array */
- if (!intel_dp_source_supports_hbr2(intel_dp))
- size--;
-
intel_dp->source_rates = source_rates;
intel_dp->num_source_rates = size;
}
@@ -1482,14 +1482,9 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
- if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
- IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
- return true;
- else
- return false;
+ return max_rate >= 540000;
}
static void
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/3] drm/i915/dp: centralize max source rate conditions more
2017-10-09 9:29 ` [PATCH 2/3] drm/i915/dp: centralize max source rate conditions more Jani Nikula
@ 2017-10-10 18:35 ` Manasi Navare
0 siblings, 0 replies; 13+ messages in thread
From: Manasi Navare @ 2017-10-10 18:35 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Oct 09, 2017 at 12:29:58PM +0300, Jani Nikula wrote:
> Turn intel_dp_source_supports_hbr2() into a simple helper to query the
> pre-filled source rates array, and move the conditions about which
> platforms support which rates to the single point of truth in
> intel_dp_set_source_rates().
>
> This also reduces the code paths you have to think about in the source
> rates initialization in intel_dp_set_source_rates(), making it easier to
> grasp.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 19 +++++++------------
> 1 file changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ca48bce23a6f..09d75df497c0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -254,15 +254,15 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> } else if (IS_GEN9_BC(dev_priv)) {
> source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> - } else {
> + } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> + IS_BROADWELL(dev_priv)) {
> source_rates = default_rates;
> size = ARRAY_SIZE(default_rates);
> + } else {
> + source_rates = default_rates;
> + size = ARRAY_SIZE(default_rates) - 1;
> }
>
> - /* This depends on the fact that 5.4 is last value in the array */
> - if (!intel_dp_source_supports_hbr2(intel_dp))
> - size--;
> -
> intel_dp->source_rates = source_rates;
> intel_dp->num_source_rates = size;
> }
> @@ -1482,14 +1482,9 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> {
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
>
> - if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> - IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
> - return true;
> - else
> - return false;
> + return max_rate >= 540000;
> }
>
> static void
> --
> 2.11.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/3] drm/i915/dp: limit sink rates based on rate
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
2017-10-09 9:29 ` [PATCH 2/3] drm/i915/dp: centralize max source rate conditions more Jani Nikula
@ 2017-10-09 9:29 ` Jani Nikula
2017-10-10 18:38 ` Manasi Navare
2017-10-09 10:03 ` ✗ Fi.CI.BAT: warning for series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Patchwork
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2017-10-09 9:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Get rid of redundant intel_dp_num_rates(). We can simply look at the
rate and limit based on that.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 26 +++++++-------------------
1 file changed, 7 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 09d75df497c0..b0f446b68f42 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -137,32 +137,20 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_num_rates(u8 link_bw_code)
-{
- switch (link_bw_code) {
- default:
- WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
- link_bw_code);
- case DP_LINK_BW_1_62:
- return 1;
- case DP_LINK_BW_2_7:
- return 2;
- case DP_LINK_BW_5_4:
- return 3;
- }
-}
-
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
- int i, num_rates;
+ int i, max_rate;
- num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+ max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
- for (i = 0; i < num_rates; i++)
+ for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
+ if (default_rates[i] > max_rate)
+ break;
intel_dp->sink_rates[i] = default_rates[i];
+ }
- intel_dp->num_sink_rates = num_rates;
+ intel_dp->num_sink_rates = i;
}
/* Theoretical max between source and sink */
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] drm/i915/dp: limit sink rates based on rate
2017-10-09 9:29 ` [PATCH 3/3] drm/i915/dp: limit sink rates based on rate Jani Nikula
@ 2017-10-10 18:38 ` Manasi Navare
0 siblings, 0 replies; 13+ messages in thread
From: Manasi Navare @ 2017-10-10 18:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Oct 09, 2017 at 12:29:59PM +0300, Jani Nikula wrote:
> Get rid of redundant intel_dp_num_rates(). We can simply look at the
> rate and limit based on that.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 26 +++++++-------------------
> 1 file changed, 7 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 09d75df497c0..b0f446b68f42 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -137,32 +137,20 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
> enum pipe pipe);
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> -static int intel_dp_num_rates(u8 link_bw_code)
> -{
> - switch (link_bw_code) {
> - default:
> - WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
> - link_bw_code);
> - case DP_LINK_BW_1_62:
> - return 1;
> - case DP_LINK_BW_2_7:
> - return 2;
> - case DP_LINK_BW_5_4:
> - return 3;
> - }
> -}
> -
> /* update sink rates from dpcd */
> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> {
> - int i, num_rates;
> + int i, max_rate;
>
> - num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> + max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>
> - for (i = 0; i < num_rates; i++)
> + for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
> + if (default_rates[i] > max_rate)
> + break;
> intel_dp->sink_rates[i] = default_rates[i];
> + }
>
> - intel_dp->num_sink_rates = num_rates;
> + intel_dp->num_sink_rates = i;
> }
>
> /* Theoretical max between source and sink */
> --
> 2.11.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
2017-10-09 9:29 ` [PATCH 2/3] drm/i915/dp: centralize max source rate conditions more Jani Nikula
2017-10-09 9:29 ` [PATCH 3/3] drm/i915/dp: limit sink rates based on rate Jani Nikula
@ 2017-10-09 10:03 ` Patchwork
2017-10-09 10:32 ` [PATCH 1/3] " Thierry Reding
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2017-10-09 10:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
URL : https://patchwork.freedesktop.org/series/31579/
State : warning
== Summary ==
Series 31579v1 series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
https://patchwork.freedesktop.org/api/1.0/series/31579/revisions/1/mbox/
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS (fi-bdw-5557u) fdo#102473
Test drv_module_reload:
Subgroup basic-reload-inject:
pass -> DMESG-WARN (fi-skl-6770hq)
fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:456s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:467s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:389s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:566s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:284s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:518s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:521s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:540s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:517s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:556s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:612s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:435s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:596s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:436s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:421s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:500s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:478s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:504s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:488s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:593s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:656s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:469s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:654s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:528s
fi-skl-6770hq total:289 pass:268 dwarn:1 dfail:0 fail:0 skip:20 time:513s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:471s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:576s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:429s
1d09197a9f9140f4795ed109018602c9e807d957 drm-tip: 2017y-10m-09d-07h-50m-48s UTC integration manifest
b55aed70a249 drm/i915/dp: limit sink rates based on rate
6b2aea169f94 drm/i915/dp: centralize max source rate conditions more
ce72d13f6548 drm/dp: WARN about invalid/unknown link rates and bw codes
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5945/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
` (2 preceding siblings ...)
2017-10-09 10:03 ` ✗ Fi.CI.BAT: warning for series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Patchwork
@ 2017-10-09 10:32 ` Thierry Reding
2017-10-11 16:03 ` Jani Nikula
2017-10-09 11:40 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Thierry Reding @ 2017-10-09 10:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel, Alex Deucher
[-- Attachment #1.1: Type: text/plain, Size: 1623 bytes --]
On Mon, Oct 09, 2017 at 12:29:57PM +0300, Jani Nikula wrote:
> Falling back to the lowest value is likely the only thing we can do, but
> doing it silently seems like a bad thing to do. Catch it early and make
> loud noises.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Thierry Reding <treding@nvidia.com>
> Cc: Rob Clark <robdclark@gmail.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 08af8d6b844b..dca21b5a03ec 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
> u8 drm_dp_link_rate_to_bw_code(int link_rate)
> {
> switch (link_rate) {
> - case 162000:
> default:
> + WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
> + DP_LINK_BW_1_62);
> + case 162000:
> return DP_LINK_BW_1_62;
> case 270000:
> return DP_LINK_BW_2_7;
> @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
> int drm_dp_bw_code_to_link_rate(u8 link_bw)
> {
> switch (link_bw) {
> - case DP_LINK_BW_1_62:
> default:
> + WARN(1, "unknown DP link bw code %x, using 162000\n", link_bw);
Nit: "DP link BW" because it is an abbreviation. Otherwise looks good:
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 10:32 ` [PATCH 1/3] " Thierry Reding
@ 2017-10-11 16:03 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2017-10-11 16:03 UTC (permalink / raw)
To: Thierry Reding; +Cc: intel-gfx, dri-devel, Alex Deucher
On Mon, 09 Oct 2017, Thierry Reding <treding@nvidia.com> wrote:
> On Mon, Oct 09, 2017 at 12:29:57PM +0300, Jani Nikula wrote:
>> Falling back to the lowest value is likely the only thing we can do, but
>> doing it silently seems like a bad thing to do. Catch it early and make
>> loud noises.
>>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Cc: Thierry Reding <treding@nvidia.com>
>> Cc: Rob Clark <robdclark@gmail.com>
>> Cc: Sean Paul <seanpaul@chromium.org>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: dri-devel@lists.freedesktop.org
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 7 +++++--
>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index 08af8d6b844b..dca21b5a03ec 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>> u8 drm_dp_link_rate_to_bw_code(int link_rate)
>> {
>> switch (link_rate) {
>> - case 162000:
>> default:
>> + WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
>> + DP_LINK_BW_1_62);
>> + case 162000:
>> return DP_LINK_BW_1_62;
>> case 270000:
>> return DP_LINK_BW_2_7;
>> @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
>> int drm_dp_bw_code_to_link_rate(u8 link_bw)
>> {
>> switch (link_bw) {
>> - case DP_LINK_BW_1_62:
>> default:
>> + WARN(1, "unknown DP link bw code %x, using 162000\n", link_bw);
>
> Nit: "DP link BW" because it is an abbreviation. Otherwise looks good:
Thanks for the reviews everyone, pushed patch 1 with BW upcased to
drm-misc-next.
BR,
Jani.
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
` (3 preceding siblings ...)
2017-10-09 10:32 ` [PATCH 1/3] " Thierry Reding
@ 2017-10-09 11:40 ` Patchwork
2017-10-09 13:41 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2017-10-09 11:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
URL : https://patchwork.freedesktop.org/series/31579/
State : success
== Summary ==
Series 31579v1 series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
https://patchwork.freedesktop.org/api/1.0/series/31579/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:451s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:466s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:391s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:572s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:284s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:526s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:519s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:542s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:514s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:563s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:618s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:427s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:596s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:434s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:419s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:470s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:500s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:489s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:595s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:662s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:465s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:657s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:528s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:516s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:581s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:429s
7b01dd7095721ed58b8f15d98069f99095f338e8 drm-tip: 2017y-10m-09d-10h-57m-19s UTC integration manifest
562b8a010d85 drm/i915/dp: limit sink rates based on rate
baff21e8c8e1 drm/i915/dp: centralize max source rate conditions more
65b9fa080470 drm/dp: WARN about invalid/unknown link rates and bw codes
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5948/
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^ permalink raw reply [flat|nested] 13+ messages in thread* ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
` (4 preceding siblings ...)
2017-10-09 11:40 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
@ 2017-10-09 13:41 ` Patchwork
2017-10-11 19:11 ` Jani Nikula
2017-10-09 18:10 ` [PATCH 1/3] " Deucher, Alexander
2017-10-10 18:19 ` Manasi Navare
7 siblings, 1 reply; 13+ messages in thread
From: Patchwork @ 2017-10-09 13:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
URL : https://patchwork.freedesktop.org/series/31579/
State : failure
== Summary ==
Test kms_atomic_transition:
Subgroup plane-all-transition-nonblocking:
pass -> FAIL (shard-hsw) fdo#102671
Test gem_wait:
Subgroup write-wait-bsd:
pass -> SKIP (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup psr-1p-primscrn-indfb-pgflip-blt:
skip -> INCOMPLETE (shard-hsw)
fdo#102671 https://bugs.freedesktop.org/show_bug.cgi?id=102671
shard-hsw total:2392 pass:1297 dwarn:6 dfail:0 fail:9 skip:1079 time:9699s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5948/shards.html
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^ permalink raw reply [flat|nested] 13+ messages in thread* RE: [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
` (5 preceding siblings ...)
2017-10-09 13:41 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-10-09 18:10 ` Deucher, Alexander
2017-10-10 18:19 ` Manasi Navare
7 siblings, 0 replies; 13+ messages in thread
From: Deucher, Alexander @ 2017-10-09 18:10 UTC (permalink / raw)
To: 'Jani Nikula', intel-gfx; +Cc: Manasi Navare, Thierry Reding, dri-devel
> -----Original Message-----
> From: Jani Nikula [mailto:jani.nikula@intel.com]
> Sent: Monday, October 09, 2017 5:30 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: jani.nikula@intel.com; Deucher, Alexander; Thierry Reding; Rob Clark;
> Sean Paul; Manasi Navare; dri-devel@lists.freedesktop.org
> Subject: [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and
> bw codes
>
> Falling back to the lowest value is likely the only thing we can do, but
> doing it silently seems like a bad thing to do. Catch it early and make
> loud noises.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Thierry Reding <treding@nvidia.com>
> Cc: Rob Clark <robdclark@gmail.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 08af8d6b844b..dca21b5a03ec 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -137,8 +137,10 @@
> EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
> u8 drm_dp_link_rate_to_bw_code(int link_rate)
> {
> switch (link_rate) {
> - case 162000:
> default:
> + WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
> + DP_LINK_BW_1_62);
> + case 162000:
> return DP_LINK_BW_1_62;
> case 270000:
> return DP_LINK_BW_2_7;
> @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
> int drm_dp_bw_code_to_link_rate(u8 link_bw)
> {
> switch (link_bw) {
> - case DP_LINK_BW_1_62:
> default:
> + WARN(1, "unknown DP link bw code %x, using 162000\n",
> link_bw);
> + case DP_LINK_BW_1_62:
> return 162000;
> case DP_LINK_BW_2_7:
> return 270000;
> --
> 2.11.0
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes
2017-10-09 9:29 [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes Jani Nikula
` (6 preceding siblings ...)
2017-10-09 18:10 ` [PATCH 1/3] " Deucher, Alexander
@ 2017-10-10 18:19 ` Manasi Navare
7 siblings, 0 replies; 13+ messages in thread
From: Manasi Navare @ 2017-10-10 18:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel, Alex Deucher, Thierry Reding
On Mon, Oct 09, 2017 at 12:29:57PM +0300, Jani Nikula wrote:
> Falling back to the lowest value is likely the only thing we can do, but
> doing it silently seems like a bad thing to do. Catch it early and make
> loud noises.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Thierry Reding <treding@nvidia.com>
> Cc: Rob Clark <robdclark@gmail.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 08af8d6b844b..dca21b5a03ec 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
> u8 drm_dp_link_rate_to_bw_code(int link_rate)
> {
> switch (link_rate) {
> - case 162000:
> default:
> + WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
> + DP_LINK_BW_1_62);
> + case 162000:
> return DP_LINK_BW_1_62;
> case 270000:
> return DP_LINK_BW_2_7;
> @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
> int drm_dp_bw_code_to_link_rate(u8 link_bw)
> {
> switch (link_bw) {
> - case DP_LINK_BW_1_62:
> default:
> + WARN(1, "unknown DP link bw code %x, using 162000\n", link_bw);
> + case DP_LINK_BW_1_62:
> return 162000;
> case DP_LINK_BW_2_7:
> return 270000;
> --
> 2.11.0
>
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^ permalink raw reply [flat|nested] 13+ messages in thread