[PATCH] gpu: ipu-v3: Allow channel burst locking on i.MX6 only

[PATCH] gpu: ipu-v3: Allow channel burst locking on i.MX6 only

[Philipp Zabel]

The IDMAC_LOCK_EN registers on i.MX51 have a different layout, and on
i.MX53 enabling the lock feature causes bursts to get lost. Restrict
enabling the burst lock feature to i.MX6.

Reported-by: Patrick Brünn <P.Bruenn@beckhoff.com>
Fixes: 790cb4c7c954 ("drm/imx: lock scanout transfers for consecutive bursts")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/gpu/ipu-v3/ipu-common.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 6a573d21d3cc2..658fa2d3e40c2 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -405,6 +405,14 @@ int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
 		return -EINVAL;
 	}
 
+	/*
+	 * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
+	 * i.MX53 channel arbitration locking doesn't seem to work properly.
+	 * Allow enabling the lock feature on IPUv3H / i.MX6 only.
+	 */
+	if (bursts && ipu->ipu_type != IPUV3H)
+		return -EINVAL;
+
 	for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
 		if (channel->num == idmac_lock_en_info[i].chnum)
 			break;
-- 
2.11.0

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RE: [PATCH] gpu: ipu-v3: Allow channel burst locking on i.MX6 only

[Patrick Brünn]

>From: Philipp Zabel [mailto:p.zabel@pengutronix.de]
>Sent: Dienstag, 10. Oktober 2017 15:28
>
>The IDMAC_LOCK_EN registers on i.MX51 have a different layout, and on
>i.MX53 enabling the lock feature causes bursts to get lost. Restrict
>enabling the burst lock feature to i.MX6.
>
>Reported-by: Patrick Brünn <P.Bruenn@beckhoff.com>
>Fixes: 790cb4c7c954 ("drm/imx: lock scanout transfers for consecutive bursts")
>Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
>---
> drivers/gpu/ipu-v3/ipu-common.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-
>common.c
>index 6a573d21d3cc2..658fa2d3e40c2 100644
>--- a/drivers/gpu/ipu-v3/ipu-common.c
>+++ b/drivers/gpu/ipu-v3/ipu-common.c
>@@ -405,6 +405,14 @@ int ipu_idmac_lock_enable(struct ipuv3_channel
>*channel, int num_bursts)
>               return -EINVAL;
>       }
>
>+      /*
>+       * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
>+       * i.MX53 channel arbitration locking doesn't seem to work properly.
>+       * Allow enabling the lock feature on IPUv3H / i.MX6 only.
>+       */
>+      if (bursts && ipu->ipu_type != IPUV3H)
>+              return -EINVAL;
>+
>       for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
>               if (channel->num == idmac_lock_en_info[i].chnum)
>                       break;
>--
>2.11.0
I tested this patch on CX9020 (i.MX53) and can confirm the reported issue gets fixed by it.
Tested-by: Patrick Brünn <P.Bruenn@beckhoff.com>

Thanks for this super-fast fix, Philipp.

Regards,
Patrick
Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys. Hans Beckhoff
Registered office: Verl, Germany | Register court: Guetersloh HRA 7075


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