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* [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
@ 2017-10-12  6:50 Weinan Li
  2017-10-12  7:23 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Weinan Li @ 2017-10-12  6:50 UTC (permalink / raw)
  To: intel-gfx

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.

v3 : Remove unnecessary comments.
v4 : Separate VM enable patch with GVT-g implementation patch due to code
dependency

Signed-off-by: Weinan Li <weinan.z.li@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_pvinfo.h     | 1 +
 drivers/gpu/drm/i915/i915_vgpu.c       | 5 +++++
 drivers/gpu/drm/i915/i915_vgpu.h       | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++----
 drivers/gpu/drm/i915/intel_lrc.c       | 1 -
 5 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 0679a58..195203f 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -53,6 +53,7 @@ enum vgt_g2v_type {
  * VGT capabilities type
  */
 #define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_HWSP_EMULATION		BIT(3)
 
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5fe9f3f..6f713c5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -86,6 +86,11 @@ bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
 }
 
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
+{
+	return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
+}
+
 struct _balloon_info_ {
 	/*
 	 * There are up to 2 regions per mappable/unmappable graphic
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index b72bd29..cec0ec1 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -29,6 +29,7 @@
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv);
 
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a59b2a3..457ebe0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -25,6 +25,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
@@ -386,10 +387,6 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
 
 static bool csb_force_mmio(struct drm_i915_private *i915)
 {
-	/* GVT emulation depends upon intercepting CSB mmio */
-	if (intel_vgpu_active(i915))
-		return true;
-
 	/*
 	 * IOMMU adds unpredictable latency causing the CSB write (from the
 	 * GPU into the HWSP) to only be visible some time after the interrupt
@@ -398,6 +395,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
 	if (intel_vtd_active())
 		return true;
 
+	if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
+		return true;
+
 	return false;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fbfcf88..766552f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -793,7 +793,6 @@ static void intel_lrc_irq_handler(unsigned long data)
 			&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
 		unsigned int head, tail;
 
-		/* However GVT emulation depends upon intercepting CSB mmio */
 		if (unlikely(execlists->csb_use_mmio)) {
 			buf = (u32 * __force)
 				(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
  2017-10-12  6:50 [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM Weinan Li
@ 2017-10-12  7:23 ` Patchwork
  2017-10-12  8:16 ` [PATCH v4] " Chris Wilson
  2017-10-12  8:41 ` ✓ Fi.CI.IGT: success for " Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-10-12  7:23 UTC (permalink / raw)
  To: Weinan Li; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
URL   : https://patchwork.freedesktop.org/series/31789/
State : success

== Summary ==

Series 31789v1 drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
https://patchwork.freedesktop.org/api/1.0/series/31789/revisions/1/mbox/

Test gem_close_race:
        Subgroup basic-threads:
                dmesg-warn -> PASS       (fi-snb-2520m)
Test gem_ringfill:
        Subgroup basic-default-hang:
                incomplete -> DMESG-WARN (fi-blb-e6850) fdo#101600
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                incomplete -> PASS       (fi-kbl-7567u) fdo#102846
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (fi-byt-n2820) fdo#101705

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:458s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:467s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:390s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:572s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:287s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:517s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:518s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:529s
fi-byt-n2820     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:514s
fi-cfl-s         total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  time:555s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:435s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:272s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:594s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:437s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:458s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:513s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:471s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:505s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:580s
fi-kbl-7567u     total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  time:489s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:590s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:475s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:656s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:531s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:515s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:476s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:581s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:428s
fi-pnv-d510 failed to connect after reboot

6a96415ec560527f41089b246c06e7fd75991791 drm-tip: 2017y-10m-11d-19h-08m-29s UTC integration manifest
cbaeb7f04c57 drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6003/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
  2017-10-12  6:50 [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM Weinan Li
  2017-10-12  7:23 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-10-12  8:16 ` Chris Wilson
  2017-10-13  1:17   ` Li, Weinan Z
  2017-10-12  8:41 ` ✓ Fi.CI.IGT: success for " Patchwork
  2 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2017-10-12  8:16 UTC (permalink / raw)
  To: Weinan Li, intel-gfx

Quoting Weinan Li (2017-10-12 07:50:08)
> Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
> the host support this feature, need to check the BIT(3) of caps in PVINFO.
> 
> v3 : Remove unnecessary comments.
> v4 : Separate VM enable patch with GVT-g implementation patch due to code
> dependency
> 
> Signed-off-by: Weinan Li <weinan.z.li@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pvinfo.h     | 1 +
>  drivers/gpu/drm/i915/i915_vgpu.c       | 5 +++++
>  drivers/gpu/drm/i915/i915_vgpu.h       | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++----
>  drivers/gpu/drm/i915/intel_lrc.c       | 1 -
>  5 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index 0679a58..195203f 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -53,6 +53,7 @@ enum vgt_g2v_type {
>   * VGT capabilities type
>   */
>  #define VGT_CAPS_FULL_48BIT_PPGTT      BIT(2)
> +#define VGT_CAPS_HWSP_EMULATION                BIT(3)
>  
>  struct vgt_if {
>         u64 magic;              /* VGT_MAGIC */
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 5fe9f3f..6f713c5 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -86,6 +86,11 @@ bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
>         return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
>  }
>  
> +bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> +{
> +       return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
> +}

Why is this not inline? The function call is going to be more
instructions than the bit test.

>  struct _balloon_info_ {
>         /*
>          * There are up to 2 regions per mappable/unmappable graphic
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index b72bd29..cec0ec1 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -29,6 +29,7 @@
>  void i915_check_vgpu(struct drm_i915_private *dev_priv);
>  
>  bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv);
>  
>  int intel_vgt_balloon(struct drm_i915_private *dev_priv);
>  void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a59b2a3..457ebe0 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -25,6 +25,7 @@
>  #include <drm/drm_print.h>
>  
>  #include "i915_drv.h"
> +#include "i915_vgpu.h"
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> @@ -386,10 +387,6 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
>  
>  static bool csb_force_mmio(struct drm_i915_private *i915)
>  {
> -       /* GVT emulation depends upon intercepting CSB mmio */
> -       if (intel_vgpu_active(i915))
> -               return true;
> -
>         /*
>          * IOMMU adds unpredictable latency causing the CSB write (from the
>          * GPU into the HWSP) to only be visible some time after the interrupt
> @@ -398,6 +395,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
>         if (intel_vtd_active())
>                 return true;
  
/* Older GVT emulation depends upon intercepting CSB mmio */
> +       if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
> +               return true;
> +
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
  2017-10-12  6:50 [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM Weinan Li
  2017-10-12  7:23 ` ✓ Fi.CI.BAT: success for " Patchwork
  2017-10-12  8:16 ` [PATCH v4] " Chris Wilson
@ 2017-10-12  8:41 ` Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-10-12  8:41 UTC (permalink / raw)
  To: Weinan Li; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
URL   : https://patchwork.freedesktop.org/series/31789/
State : success

== Summary ==

Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912
Test kms_flip:
        Subgroup flip-vs-rmfb:
                dmesg-warn -> PASS       (shard-hsw) fdo#102614

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hsw        total:2501 pass:1410 dwarn:0   dfail:0   fail:9   skip:1082 time:9524s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6003/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
  2017-10-12  8:16 ` [PATCH v4] " Chris Wilson
@ 2017-10-13  1:17   ` Li, Weinan Z
  2017-10-13  8:45     ` Joonas Lahtinen
  0 siblings, 1 reply; 6+ messages in thread
From: Li, Weinan Z @ 2017-10-13  1:17 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

On 10/12/2017 4:16 PM, Chris Wilson wrote:
> Quoting Weinan Li (2017-10-12 07:50:08)
>> Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
>> the host support this feature, need to check the BIT(3) of caps in PVINFO.
>>
>> v3 : Remove unnecessary comments.
>> v4 : Separate VM enable patch with GVT-g implementation patch due to code
>> dependency
>>
>> Signed-off-by: Weinan Li <weinan.z.li@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_pvinfo.h     | 1 +
>>   drivers/gpu/drm/i915/i915_vgpu.c       | 5 +++++
>>   drivers/gpu/drm/i915/i915_vgpu.h       | 1 +
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++----
>>   drivers/gpu/drm/i915/intel_lrc.c       | 1 -
>>   5 files changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
>> index 0679a58..195203f 100644
>> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
>> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
>> @@ -53,6 +53,7 @@ enum vgt_g2v_type {
>>    * VGT capabilities type
>>    */
>>   #define VGT_CAPS_FULL_48BIT_PPGTT      BIT(2)
>> +#define VGT_CAPS_HWSP_EMULATION                BIT(3)
>>   
>>   struct vgt_if {
>>          u64 magic;              /* VGT_MAGIC */
>> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
>> index 5fe9f3f..6f713c5 100644
>> --- a/drivers/gpu/drm/i915/i915_vgpu.c
>> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
>> @@ -86,6 +86,11 @@ bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
>>          return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
>>   }
>>   
>> +bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
>> +{
>> +       return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
>> +}
> Why is this not inline? The function call is going to be more
> instructions than the bit test.
it is just called in init process, but yes, inline is more reasonable.
>
>>   struct _balloon_info_ {
>>          /*
>>           * There are up to 2 regions per mappable/unmappable graphic
>> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
>> index b72bd29..cec0ec1 100644
>> --- a/drivers/gpu/drm/i915/i915_vgpu.h
>> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
>> @@ -29,6 +29,7 @@
>>   void i915_check_vgpu(struct drm_i915_private *dev_priv);
>>   
>>   bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
>> +bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv);
>>   
>>   int intel_vgt_balloon(struct drm_i915_private *dev_priv);
>>   void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index a59b2a3..457ebe0 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -25,6 +25,7 @@
>>   #include <drm/drm_print.h>
>>   
>>   #include "i915_drv.h"
>> +#include "i915_vgpu.h"
>>   #include "intel_ringbuffer.h"
>>   #include "intel_lrc.h"
>>   
>> @@ -386,10 +387,6 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
>>   
>>   static bool csb_force_mmio(struct drm_i915_private *i915)
>>   {
>> -       /* GVT emulation depends upon intercepting CSB mmio */
>> -       if (intel_vgpu_active(i915))
>> -               return true;
>> -
>>          /*
>>           * IOMMU adds unpredictable latency causing the CSB write (from the
>>           * GPU into the HWSP) to only be visible some time after the interrupt
>> @@ -398,6 +395,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
>>          if (intel_vtd_active())
>>                  return true;
>    
> /* Older GVT emulation depends upon intercepting CSB mmio */
>> +       if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
>> +               return true;
>> +

_______________________________________________
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^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM
  2017-10-13  1:17   ` Li, Weinan Z
@ 2017-10-13  8:45     ` Joonas Lahtinen
  0 siblings, 0 replies; 6+ messages in thread
From: Joonas Lahtinen @ 2017-10-13  8:45 UTC (permalink / raw)
  To: Li, Weinan Z, Chris Wilson, intel-gfx

On Fri, 2017-10-13 at 09:17 +0800, Li, Weinan Z wrote:
> On 10/12/2017 4:16 PM, Chris Wilson wrote:
> > Quoting Weinan Li (2017-10-12 07:50:08)

<SNIP>

> > > @@ -398,6 +395,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
> > >          if (intel_vtd_active())
> > >                  return true;
> > 
> >    
> > /* Older GVT emulation depends upon intercepting CSB mmio */
> > > +       if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
> > > +               return true;
> > > +

You missed the request to move the comment here.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-10-13  8:45 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-12  6:50 [PATCH v4] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM Weinan Li
2017-10-12  7:23 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-10-12  8:16 ` [PATCH v4] " Chris Wilson
2017-10-13  1:17   ` Li, Weinan Z
2017-10-13  8:45     ` Joonas Lahtinen
2017-10-12  8:41 ` ✓ Fi.CI.IGT: success for " Patchwork

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