* [PATCH] drm/i915: Start tracking PSR state in crtc state
@ 2017-10-12 10:09 Ville Syrjala
2017-10-12 10:40 ` Jani Nikula
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Ville Syrjala @ 2017-10-12 10:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add the minimal amount of PSR tracking into the crtc state. This allows
precomputing the possibility of using PSR correctly, and it means we can
safely call the psr enable/disable functions for any DP endcoder.
As a nice bonus we get rid of some more crtc->config usage, which we
want to kill off eventually.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 5 +++
drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++++--------------------
3 files changed, 50 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b0f446b68f42..753404280a19 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (!HAS_DDI(dev_priv))
intel_dp_set_clock(encoder, pipe_config);
+ intel_psr_compute_config(intel_dp, pipe_config);
+
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b87946dcc53f..d61985f93d40 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -718,6 +718,9 @@ struct intel_crtc_state {
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
+ bool has_psr;
+ bool has_psr2;
+
/*
* Frequence the dpll for the port should run at. Differs from the
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
@@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
void intel_psr_init(struct drm_i915_private *dev_priv);
void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits);
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5419cda83ba8..f6149af39f02 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -376,22 +376,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
hsw_activate_psr1(intel_dp);
}
-static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_crtc *crtc = dig_port->base.base.crtc;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
- &intel_crtc->config->base.adjusted_mode;
+ &crtc_state->base.adjusted_mode;
int psr_setup_time;
- lockdep_assert_held(&dev_priv->psr.lock);
- WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
- WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
+ if (!HAS_PSR(dev_priv))
+ return;
- dev_priv->psr.source_ok = false;
+ if (!is_edp_psr(intel_dp))
+ return;
+
+ if (!i915_modparams.enable_psr) {
+ DRM_DEBUG_KMS("PSR disable by flag\n");
+ return;
+ }
/*
* HSW spec explicitly says PSR is tied to port A.
@@ -402,66 +405,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
*/
if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
- return false;
- }
-
- if (!i915_modparams.enable_psr) {
- DRM_DEBUG_KMS("PSR disable by flag\n");
- return false;
+ return;
}
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
!dev_priv->psr.link_standby) {
DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
- return false;
+ return;
}
if (IS_HASWELL(dev_priv) &&
- I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
+ I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
S3D_ENABLE) {
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
- return false;
+ return;
}
if (IS_HASWELL(dev_priv) &&
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
- return false;
+ return;
}
psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
if (psr_setup_time < 0) {
DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
intel_dp->psr_dpcd[1]);
- return false;
+ return;
}
if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
psr_setup_time);
- return false;
+ return;
+ }
+
+ /*
+ * FIXME psr2_support is messed up. It's both computed
+ * dynamically during PSR enable, and extracted from sink
+ * caps during eDP detection.
+ */
+ if (!dev_priv->psr.psr2_support) {
+ crtc_state->has_psr = true;
+ return;
}
/* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
- if (dev_priv->psr.psr2_support &&
- (intel_crtc->config->pipe_src_w > 3200 ||
- intel_crtc->config->pipe_src_h > 2000)) {
- dev_priv->psr.psr2_support = false;
- return false;
+ if (adjusted_mode->crtc_hdisplay > 3200 ||
+ adjusted_mode->crtc_vdisplay > 2000) {
+ DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
+ return;
}
/*
* FIXME:enable psr2 only for y-cordinate psr2 panels
* After gtc implementation , remove this restriction.
*/
- if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
+ if (!dev_priv->psr.y_cord_support) {
DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
- return false;
+ return;
}
- dev_priv->psr.source_ok = true;
- return true;
+ crtc_state->has_psr = true;
+ crtc_state->has_psr2 = true;
}
static void intel_psr_activate(struct intel_dp *intel_dp)
@@ -531,13 +538,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!HAS_PSR(dev_priv))
- return;
-
- if (!is_edp_psr(intel_dp)) {
- DRM_DEBUG_KMS("PSR not supported by this panel\n");
- return;
- }
+ if (!crtc_state->has_psr)
+ goto unlock;
WARN_ON(dev_priv->drrs.dp);
mutex_lock(&dev_priv->psr.lock);
@@ -546,8 +548,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- if (!intel_psr_match_conditions(intel_dp))
- goto unlock;
+ dev_priv->psr.psr2_support = crtc_state->has_psr2;
+ dev_priv->psr.source_ok = true;
dev_priv->psr.busy_frontbuffer_bits = 0;
@@ -668,7 +670,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!HAS_PSR(dev_priv))
+ if (!old_crtc_state->has_psr)
return;
mutex_lock(&dev_priv->psr.lock);
--
2.13.6
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915: Start tracking PSR state in crtc state
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
@ 2017-10-12 10:40 ` Jani Nikula
2017-10-12 12:23 ` Ville Syrjälä
2017-10-12 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2017-10-12 10:40 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 12 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the minimal amount of PSR tracking into the crtc state. This allows
> precomputing the possibility of using PSR correctly, and it means we can
> safely call the psr enable/disable functions for any DP endcoder.
>
> As a nice bonus we get rid of some more crtc->config usage, which we
> want to kill off eventually.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +
> drivers/gpu/drm/i915/intel_drv.h | 5 +++
> drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++++--------------------
> 3 files changed, 50 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b0f446b68f42..753404280a19 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (!HAS_DDI(dev_priv))
> intel_dp_set_clock(encoder, pipe_config);
>
> + intel_psr_compute_config(intel_dp, pipe_config);
> +
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b87946dcc53f..d61985f93d40 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -718,6 +718,9 @@ struct intel_crtc_state {
> struct intel_link_m_n dp_m2_n2;
> bool has_drrs;
>
> + bool has_psr;
> + bool has_psr2;
> +
> /*
> * Frequence the dpll for the port should run at. Differs from the
> * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
> @@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> void intel_psr_init(struct drm_i915_private *dev_priv);
> void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits);
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state);
>
> /* intel_runtime_pm.c */
> int intel_power_domains_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 5419cda83ba8..f6149af39f02 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -376,22 +376,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
> hsw_activate_psr1(intel_dp);
> }
>
> -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_crtc *crtc = dig_port->base.base.crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config->base.adjusted_mode;
> + &crtc_state->base.adjusted_mode;
> int psr_setup_time;
>
> - lockdep_assert_held(&dev_priv->psr.lock);
> - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> - WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
> + if (!HAS_PSR(dev_priv))
> + return;
>
> - dev_priv->psr.source_ok = false;
> + if (!is_edp_psr(intel_dp))
I guess I'd like an intel_dp_is_edp() check here or within is_edp_psr()
before touching intel_dp->psr_dpcd.
> + return;
> +
> + if (!i915_modparams.enable_psr) {
> + DRM_DEBUG_KMS("PSR disable by flag\n");
> + return;
> + }
>
> /*
> * HSW spec explicitly says PSR is tied to port A.
> @@ -402,66 +405,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> */
> if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> - return false;
> - }
> -
> - if (!i915_modparams.enable_psr) {
> - DRM_DEBUG_KMS("PSR disable by flag\n");
> - return false;
> + return;
> }
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> !dev_priv->psr.link_standby) {
> DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> - return false;
> + return;
> }
>
> if (IS_HASWELL(dev_priv) &&
> - I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> + I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> S3D_ENABLE) {
> DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> - return false;
> + return;
> }
>
> if (IS_HASWELL(dev_priv) &&
> adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> - return false;
> + return;
> }
>
> psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> if (psr_setup_time < 0) {
> DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> intel_dp->psr_dpcd[1]);
> - return false;
> + return;
> }
>
> if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> psr_setup_time);
> - return false;
> + return;
> + }
> +
> + /*
> + * FIXME psr2_support is messed up. It's both computed
> + * dynamically during PSR enable, and extracted from sink
> + * caps during eDP detection.
> + */
Agreed, yuck.
> + if (!dev_priv->psr.psr2_support) {
> + crtc_state->has_psr = true;
> + return;
> }
>
> /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
> - if (dev_priv->psr.psr2_support &&
> - (intel_crtc->config->pipe_src_w > 3200 ||
> - intel_crtc->config->pipe_src_h > 2000)) {
> - dev_priv->psr.psr2_support = false;
> - return false;
> + if (adjusted_mode->crtc_hdisplay > 3200 ||
> + adjusted_mode->crtc_vdisplay > 2000) {
> + DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
This branch doesn't set has_psr = true, shouldn't it? Maybe move that
before the if (!dev_priv->psr.psr2_support) condition from within the
block?
> + return;
> }
>
> /*
> * FIXME:enable psr2 only for y-cordinate psr2 panels
> * After gtc implementation , remove this restriction.
> */
> - if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
> + if (!dev_priv->psr.y_cord_support) {
> DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
> - return false;
> + return;
> }
>
> - dev_priv->psr.source_ok = true;
> - return true;
> + crtc_state->has_psr = true;
> + crtc_state->has_psr2 = true;
> }
>
> static void intel_psr_activate(struct intel_dp *intel_dp)
> @@ -531,13 +538,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (!HAS_PSR(dev_priv))
> - return;
> -
> - if (!is_edp_psr(intel_dp)) {
> - DRM_DEBUG_KMS("PSR not supported by this panel\n");
> - return;
> - }
> + if (!crtc_state->has_psr)
> + goto unlock;
It's not locked yet...
BR,
Jani.
>
> WARN_ON(dev_priv->drrs.dp);
> mutex_lock(&dev_priv->psr.lock);
> @@ -546,8 +548,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> goto unlock;
> }
>
> - if (!intel_psr_match_conditions(intel_dp))
> - goto unlock;
> + dev_priv->psr.psr2_support = crtc_state->has_psr2;
> + dev_priv->psr.source_ok = true;
>
> dev_priv->psr.busy_frontbuffer_bits = 0;
>
> @@ -668,7 +670,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (!HAS_PSR(dev_priv))
> + if (!old_crtc_state->has_psr)
> return;
>
> mutex_lock(&dev_priv->psr.lock);
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Start tracking PSR state in crtc state
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
2017-10-12 10:40 ` Jani Nikula
@ 2017-10-12 10:50 ` Patchwork
2017-10-12 11:51 ` ✓ Fi.CI.IGT: " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-10-12 10:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start tracking PSR state in crtc state
URL : https://patchwork.freedesktop.org/series/31802/
State : success
== Summary ==
Series 31802v1 drm/i915: Start tracking PSR state in crtc state
https://patchwork.freedesktop.org/api/1.0/series/31802/revisions/1/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:453s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:472s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:397s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:566s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:289s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:528s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:529s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:540s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:520s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:538s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:556s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:438s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:461s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:481s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:505s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:486s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:564s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:664s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:475s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:624s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:536s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:517s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:579s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:436s
fi-gdg-551 failed to connect after reboot
a869721e93a51c2bf425f322514527b4dc3944c8 drm-tip: 2017y-10m-12d-08h-30m-31s UTC integration manifest
5e14757dfa1f drm/i915: Start tracking PSR state in crtc state
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6005/
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* ✓ Fi.CI.IGT: success for drm/i915: Start tracking PSR state in crtc state
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
2017-10-12 10:40 ` Jani Nikula
2017-10-12 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-10-12 11:51 ` Patchwork
2017-10-12 13:02 ` [PATCH v2] " Ville Syrjala
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-10-12 11:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start tracking PSR state in crtc state
URL : https://patchwork.freedesktop.org/series/31802/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
dmesg-warn -> PASS (shard-hsw) fdo#102614
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
shard-hsw total:2551 pass:1437 dwarn:0 dfail:0 fail:11 skip:1103 time:9636s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6005/shards.html
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915: Start tracking PSR state in crtc state
2017-10-12 10:40 ` Jani Nikula
@ 2017-10-12 12:23 ` Ville Syrjälä
2017-10-12 12:30 ` Jani Nikula
0 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2017-10-12 12:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi
On Thu, Oct 12, 2017 at 01:40:33PM +0300, Jani Nikula wrote:
> On Thu, 12 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add the minimal amount of PSR tracking into the crtc state. This allows
> > precomputing the possibility of using PSR correctly, and it means we can
> > safely call the psr enable/disable functions for any DP endcoder.
> >
> > As a nice bonus we get rid of some more crtc->config usage, which we
> > want to kill off eventually.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 2 +
> > drivers/gpu/drm/i915/intel_drv.h | 5 +++
> > drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++++--------------------
> > 3 files changed, 50 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index b0f446b68f42..753404280a19 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > if (!HAS_DDI(dev_priv))
> > intel_dp_set_clock(encoder, pipe_config);
> >
> > + intel_psr_compute_config(intel_dp, pipe_config);
> > +
> > return true;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index b87946dcc53f..d61985f93d40 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -718,6 +718,9 @@ struct intel_crtc_state {
> > struct intel_link_m_n dp_m2_n2;
> > bool has_drrs;
> >
> > + bool has_psr;
> > + bool has_psr2;
> > +
> > /*
> > * Frequence the dpll for the port should run at. Differs from the
> > * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
> > @@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > void intel_psr_init(struct drm_i915_private *dev_priv);
> > void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits);
> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state);
> >
> > /* intel_runtime_pm.c */
> > int intel_power_domains_init(struct drm_i915_private *);
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 5419cda83ba8..f6149af39f02 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -376,22 +376,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
> > hsw_activate_psr1(intel_dp);
> > }
> >
> > -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > - struct drm_device *dev = dig_port->base.base.dev;
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > - struct drm_crtc *crtc = dig_port->base.base.crtc;
> > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> > const struct drm_display_mode *adjusted_mode =
> > - &intel_crtc->config->base.adjusted_mode;
> > + &crtc_state->base.adjusted_mode;
> > int psr_setup_time;
> >
> > - lockdep_assert_held(&dev_priv->psr.lock);
> > - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > - WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
> > + if (!HAS_PSR(dev_priv))
> > + return;
> >
> > - dev_priv->psr.source_ok = false;
> > + if (!is_edp_psr(intel_dp))
>
> I guess I'd like an intel_dp_is_edp() check here or within is_edp_psr()
> before touching intel_dp->psr_dpcd.
Hmm. I guess just stuffing it into is_edp_psr() would be a decent idea.
>
> > + return;
> > +
> > + if (!i915_modparams.enable_psr) {
> > + DRM_DEBUG_KMS("PSR disable by flag\n");
> > + return;
> > + }
> >
> > /*
> > * HSW spec explicitly says PSR is tied to port A.
> > @@ -402,66 +405,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > */
> > if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> > DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> > - return false;
> > - }
> > -
> > - if (!i915_modparams.enable_psr) {
> > - DRM_DEBUG_KMS("PSR disable by flag\n");
> > - return false;
> > + return;
> > }
> >
> > if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> > !dev_priv->psr.link_standby) {
> > DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> > - return false;
> > + return;
> > }
> >
> > if (IS_HASWELL(dev_priv) &&
> > - I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> > + I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> > S3D_ENABLE) {
> > DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> > - return false;
> > + return;
> > }
> >
> > if (IS_HASWELL(dev_priv) &&
> > adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> > - return false;
> > + return;
> > }
> >
> > psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> > if (psr_setup_time < 0) {
> > DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> > intel_dp->psr_dpcd[1]);
> > - return false;
> > + return;
> > }
> >
> > if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> > DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> > psr_setup_time);
> > - return false;
> > + return;
> > + }
> > +
> > + /*
> > + * FIXME psr2_support is messed up. It's both computed
> > + * dynamically during PSR enable, and extracted from sink
> > + * caps during eDP detection.
> > + */
>
> Agreed, yuck.
>
> > + if (!dev_priv->psr.psr2_support) {
> > + crtc_state->has_psr = true;
> > + return;
> > }
> >
> > /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
> > - if (dev_priv->psr.psr2_support &&
> > - (intel_crtc->config->pipe_src_w > 3200 ||
> > - intel_crtc->config->pipe_src_h > 2000)) {
> > - dev_priv->psr.psr2_support = false;
> > - return false;
> > + if (adjusted_mode->crtc_hdisplay > 3200 ||
> > + adjusted_mode->crtc_vdisplay > 2000) {
> > + DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
>
> This branch doesn't set has_psr = true, shouldn't it?
The original didn't set dev_priv->psr.source_ok=true until the very end.
So I guess the logic here is (for whatever reason) to disable PSR entirely
if the sink can do PSR2 but the source can't. I just tried to preserve
that behaviour.
> Maybe move that
> before the if (!dev_priv->psr.psr2_support) condition from within the
> block?
>
> > + return;
> > }
> >
> > /*
> > * FIXME:enable psr2 only for y-cordinate psr2 panels
> > * After gtc implementation , remove this restriction.
> > */
> > - if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
> > + if (!dev_priv->psr.y_cord_support) {
> > DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
> > - return false;
> > + return;
> > }
> >
> > - dev_priv->psr.source_ok = true;
> > - return true;
> > + crtc_state->has_psr = true;
> > + crtc_state->has_psr2 = true;
> > }
> >
> > static void intel_psr_activate(struct intel_dp *intel_dp)
> > @@ -531,13 +538,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> >
> > - if (!HAS_PSR(dev_priv))
> > - return;
> > -
> > - if (!is_edp_psr(intel_dp)) {
> > - DRM_DEBUG_KMS("PSR not supported by this panel\n");
> > - return;
> > - }
> > + if (!crtc_state->has_psr)
> > + goto unlock;
>
> It's not locked yet...
Doh. Will fix.
>
> BR,
> Jani.
>
> >
> > WARN_ON(dev_priv->drrs.dp);
> > mutex_lock(&dev_priv->psr.lock);
> > @@ -546,8 +548,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > goto unlock;
> > }
> >
> > - if (!intel_psr_match_conditions(intel_dp))
> > - goto unlock;
> > + dev_priv->psr.psr2_support = crtc_state->has_psr2;
> > + dev_priv->psr.source_ok = true;
> >
> > dev_priv->psr.busy_frontbuffer_bits = 0;
> >
> > @@ -668,7 +670,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> >
> > - if (!HAS_PSR(dev_priv))
> > + if (!old_crtc_state->has_psr)
> > return;
> >
> > mutex_lock(&dev_priv->psr.lock);
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915: Start tracking PSR state in crtc state
2017-10-12 12:23 ` Ville Syrjälä
@ 2017-10-12 12:30 ` Jani Nikula
0 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2017-10-12 12:30 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi
On Thu, 12 Oct 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Oct 12, 2017 at 01:40:33PM +0300, Jani Nikula wrote:
>> On Thu, 12 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Add the minimal amount of PSR tracking into the crtc state. This allows
>> > precomputing the possibility of using PSR correctly, and it means we can
>> > safely call the psr enable/disable functions for any DP endcoder.
>> >
>> > As a nice bonus we get rid of some more crtc->config usage, which we
>> > want to kill off eventually.
>> >
>> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > Cc: Jani Nikula <jani.nikula@intel.com>
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_dp.c | 2 +
>> > drivers/gpu/drm/i915/intel_drv.h | 5 +++
>> > drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++++--------------------
>> > 3 files changed, 50 insertions(+), 41 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> > index b0f446b68f42..753404280a19 100644
>> > --- a/drivers/gpu/drm/i915/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> > @@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> > if (!HAS_DDI(dev_priv))
>> > intel_dp_set_clock(encoder, pipe_config);
>> >
>> > + intel_psr_compute_config(intel_dp, pipe_config);
>> > +
>> > return true;
>> > }
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> > index b87946dcc53f..d61985f93d40 100644
>> > --- a/drivers/gpu/drm/i915/intel_drv.h
>> > +++ b/drivers/gpu/drm/i915/intel_drv.h
>> > @@ -718,6 +718,9 @@ struct intel_crtc_state {
>> > struct intel_link_m_n dp_m2_n2;
>> > bool has_drrs;
>> >
>> > + bool has_psr;
>> > + bool has_psr2;
>> > +
>> > /*
>> > * Frequence the dpll for the port should run at. Differs from the
>> > * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
>> > @@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>> > void intel_psr_init(struct drm_i915_private *dev_priv);
>> > void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
>> > unsigned frontbuffer_bits);
>> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
>> > + struct intel_crtc_state *crtc_state);
>> >
>> > /* intel_runtime_pm.c */
>> > int intel_power_domains_init(struct drm_i915_private *);
>> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> > index 5419cda83ba8..f6149af39f02 100644
>> > --- a/drivers/gpu/drm/i915/intel_psr.c
>> > +++ b/drivers/gpu/drm/i915/intel_psr.c
>> > @@ -376,22 +376,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
>> > hsw_activate_psr1(intel_dp);
>> > }
>> >
>> > -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
>> > + struct intel_crtc_state *crtc_state)
>> > {
>> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > - struct drm_device *dev = dig_port->base.base.dev;
>> > - struct drm_i915_private *dev_priv = to_i915(dev);
>> > - struct drm_crtc *crtc = dig_port->base.base.crtc;
>> > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> > const struct drm_display_mode *adjusted_mode =
>> > - &intel_crtc->config->base.adjusted_mode;
>> > + &crtc_state->base.adjusted_mode;
>> > int psr_setup_time;
>> >
>> > - lockdep_assert_held(&dev_priv->psr.lock);
>> > - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>> > - WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
>> > + if (!HAS_PSR(dev_priv))
>> > + return;
>> >
>> > - dev_priv->psr.source_ok = false;
>> > + if (!is_edp_psr(intel_dp))
>>
>> I guess I'd like an intel_dp_is_edp() check here or within is_edp_psr()
>> before touching intel_dp->psr_dpcd.
>
> Hmm. I guess just stuffing it into is_edp_psr() would be a decent idea.
>
>>
>> > + return;
>> > +
>> > + if (!i915_modparams.enable_psr) {
>> > + DRM_DEBUG_KMS("PSR disable by flag\n");
>> > + return;
>> > + }
>> >
>> > /*
>> > * HSW spec explicitly says PSR is tied to port A.
>> > @@ -402,66 +405,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>> > */
>> > if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
>> > DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
>> > - return false;
>> > - }
>> > -
>> > - if (!i915_modparams.enable_psr) {
>> > - DRM_DEBUG_KMS("PSR disable by flag\n");
>> > - return false;
>> > + return;
>> > }
>> >
>> > if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>> > !dev_priv->psr.link_standby) {
>> > DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
>> > - return false;
>> > + return;
>> > }
>> >
>> > if (IS_HASWELL(dev_priv) &&
>> > - I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
>> > + I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
>> > S3D_ENABLE) {
>> > DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
>> > - return false;
>> > + return;
>> > }
>> >
>> > if (IS_HASWELL(dev_priv) &&
>> > adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>> > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
>> > - return false;
>> > + return;
>> > }
>> >
>> > psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
>> > if (psr_setup_time < 0) {
>> > DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
>> > intel_dp->psr_dpcd[1]);
>> > - return false;
>> > + return;
>> > }
>> >
>> > if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
>> > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
>> > DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
>> > psr_setup_time);
>> > - return false;
>> > + return;
>> > + }
>> > +
>> > + /*
>> > + * FIXME psr2_support is messed up. It's both computed
>> > + * dynamically during PSR enable, and extracted from sink
>> > + * caps during eDP detection.
>> > + */
>>
>> Agreed, yuck.
>>
>> > + if (!dev_priv->psr.psr2_support) {
>> > + crtc_state->has_psr = true;
>> > + return;
>> > }
>> >
>> > /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
>> > - if (dev_priv->psr.psr2_support &&
>> > - (intel_crtc->config->pipe_src_w > 3200 ||
>> > - intel_crtc->config->pipe_src_h > 2000)) {
>> > - dev_priv->psr.psr2_support = false;
>> > - return false;
>> > + if (adjusted_mode->crtc_hdisplay > 3200 ||
>> > + adjusted_mode->crtc_vdisplay > 2000) {
>> > + DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
>>
>> This branch doesn't set has_psr = true, shouldn't it?
>
> The original didn't set dev_priv->psr.source_ok=true until the very end.
> So I guess the logic here is (for whatever reason) to disable PSR entirely
> if the sink can do PSR2 but the source can't. I just tried to preserve
> that behaviour.
Ack on preserving the behaviour.
BR,
Jani.
>
>> Maybe move that
>> before the if (!dev_priv->psr.psr2_support) condition from within the
>> block?
>>
>> > + return;
>> > }
>> >
>> > /*
>> > * FIXME:enable psr2 only for y-cordinate psr2 panels
>> > * After gtc implementation , remove this restriction.
>> > */
>> > - if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
>> > + if (!dev_priv->psr.y_cord_support) {
>> > DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
>> > - return false;
>> > + return;
>> > }
>> >
>> > - dev_priv->psr.source_ok = true;
>> > - return true;
>> > + crtc_state->has_psr = true;
>> > + crtc_state->has_psr2 = true;
>> > }
>> >
>> > static void intel_psr_activate(struct intel_dp *intel_dp)
>> > @@ -531,13 +538,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>> > struct drm_device *dev = intel_dig_port->base.base.dev;
>> > struct drm_i915_private *dev_priv = to_i915(dev);
>> >
>> > - if (!HAS_PSR(dev_priv))
>> > - return;
>> > -
>> > - if (!is_edp_psr(intel_dp)) {
>> > - DRM_DEBUG_KMS("PSR not supported by this panel\n");
>> > - return;
>> > - }
>> > + if (!crtc_state->has_psr)
>> > + goto unlock;
>>
>> It's not locked yet...
>
> Doh. Will fix.
>
>>
>> BR,
>> Jani.
>>
>> >
>> > WARN_ON(dev_priv->drrs.dp);
>> > mutex_lock(&dev_priv->psr.lock);
>> > @@ -546,8 +548,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>> > goto unlock;
>> > }
>> >
>> > - if (!intel_psr_match_conditions(intel_dp))
>> > - goto unlock;
>> > + dev_priv->psr.psr2_support = crtc_state->has_psr2;
>> > + dev_priv->psr.source_ok = true;
>> >
>> > dev_priv->psr.busy_frontbuffer_bits = 0;
>> >
>> > @@ -668,7 +670,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>> > struct drm_device *dev = intel_dig_port->base.base.dev;
>> > struct drm_i915_private *dev_priv = to_i915(dev);
>> >
>> > - if (!HAS_PSR(dev_priv))
>> > + if (!old_crtc_state->has_psr)
>> > return;
>> >
>> > mutex_lock(&dev_priv->psr.lock);
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2] drm/i915: Start tracking PSR state in crtc state
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
` (2 preceding siblings ...)
2017-10-12 11:51 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-10-12 13:02 ` Ville Syrjala
2017-10-12 13:28 ` Jani Nikula
2017-10-12 13:49 ` ✓ Fi.CI.BAT: success for drm/i915: Start tracking PSR state in crtc state (rev2) Patchwork
2017-10-12 18:54 ` ✗ Fi.CI.IGT: warning " Patchwork
5 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjala @ 2017-10-12 13:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add the minimal amount of PSR tracking into the crtc state. This allows
precomputing the possibility of using PSR correctly, and it means we can
safely call the psr enable/disable functions for any DP endcoder.
As a nice bonus we get rid of some more crtc->config usage, which we
want to kill off eventually.
v2: Fix 'goto unlock' fail in intel_psr_enable() (Jani)
Check intel_dp_is_edp() in is_edp_psr() (Jani)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 5 +++
drivers/gpu/drm/i915/intel_psr.c | 85 +++++++++++++++++++++-------------------
3 files changed, 52 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b0f446b68f42..753404280a19 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (!HAS_DDI(dev_priv))
intel_dp_set_clock(encoder, pipe_config);
+ intel_psr_compute_config(intel_dp, pipe_config);
+
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b87946dcc53f..d61985f93d40 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -718,6 +718,9 @@ struct intel_crtc_state {
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
+ bool has_psr;
+ bool has_psr2;
+
/*
* Frequence the dpll for the port should run at. Differs from the
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
@@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
void intel_psr_init(struct drm_i915_private *dev_priv);
void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits);
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5419cda83ba8..93b177cc4cbf 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -58,6 +58,9 @@
static bool is_edp_psr(struct intel_dp *intel_dp)
{
+ if (!intel_dp_is_edp(intel_dp))
+ return false;
+
return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
}
@@ -376,22 +379,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
hsw_activate_psr1(intel_dp);
}
-static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_crtc *crtc = dig_port->base.base.crtc;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
- &intel_crtc->config->base.adjusted_mode;
+ &crtc_state->base.adjusted_mode;
int psr_setup_time;
- lockdep_assert_held(&dev_priv->psr.lock);
- WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
- WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
+ if (!HAS_PSR(dev_priv))
+ return;
- dev_priv->psr.source_ok = false;
+ if (!is_edp_psr(intel_dp))
+ return;
+
+ if (!i915_modparams.enable_psr) {
+ DRM_DEBUG_KMS("PSR disable by flag\n");
+ return;
+ }
/*
* HSW spec explicitly says PSR is tied to port A.
@@ -402,66 +408,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
*/
if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
- return false;
- }
-
- if (!i915_modparams.enable_psr) {
- DRM_DEBUG_KMS("PSR disable by flag\n");
- return false;
+ return;
}
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
!dev_priv->psr.link_standby) {
DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
- return false;
+ return;
}
if (IS_HASWELL(dev_priv) &&
- I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
+ I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
S3D_ENABLE) {
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
- return false;
+ return;
}
if (IS_HASWELL(dev_priv) &&
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
- return false;
+ return;
}
psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
if (psr_setup_time < 0) {
DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
intel_dp->psr_dpcd[1]);
- return false;
+ return;
}
if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
psr_setup_time);
- return false;
+ return;
+ }
+
+ /*
+ * FIXME psr2_support is messed up. It's both computed
+ * dynamically during PSR enable, and extracted from sink
+ * caps during eDP detection.
+ */
+ if (!dev_priv->psr.psr2_support) {
+ crtc_state->has_psr = true;
+ return;
}
/* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
- if (dev_priv->psr.psr2_support &&
- (intel_crtc->config->pipe_src_w > 3200 ||
- intel_crtc->config->pipe_src_h > 2000)) {
- dev_priv->psr.psr2_support = false;
- return false;
+ if (adjusted_mode->crtc_hdisplay > 3200 ||
+ adjusted_mode->crtc_vdisplay > 2000) {
+ DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
+ return;
}
/*
* FIXME:enable psr2 only for y-cordinate psr2 panels
* After gtc implementation , remove this restriction.
*/
- if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
+ if (!dev_priv->psr.y_cord_support) {
DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
- return false;
+ return;
}
- dev_priv->psr.source_ok = true;
- return true;
+ crtc_state->has_psr = true;
+ crtc_state->has_psr2 = true;
}
static void intel_psr_activate(struct intel_dp *intel_dp)
@@ -531,14 +541,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!HAS_PSR(dev_priv))
+ if (!crtc_state->has_psr)
return;
- if (!is_edp_psr(intel_dp)) {
- DRM_DEBUG_KMS("PSR not supported by this panel\n");
- return;
- }
-
WARN_ON(dev_priv->drrs.dp);
mutex_lock(&dev_priv->psr.lock);
if (dev_priv->psr.enabled) {
@@ -546,8 +551,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- if (!intel_psr_match_conditions(intel_dp))
- goto unlock;
+ dev_priv->psr.psr2_support = crtc_state->has_psr2;
+ dev_priv->psr.source_ok = true;
dev_priv->psr.busy_frontbuffer_bits = 0;
@@ -668,7 +673,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- if (!HAS_PSR(dev_priv))
+ if (!old_crtc_state->has_psr)
return;
mutex_lock(&dev_priv->psr.lock);
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2] drm/i915: Start tracking PSR state in crtc state
2017-10-12 13:02 ` [PATCH v2] " Ville Syrjala
@ 2017-10-12 13:28 ` Jani Nikula
2017-10-12 18:11 ` Rodrigo Vivi
0 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2017-10-12 13:28 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Rodrigo Vivi
On Thu, 12 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the minimal amount of PSR tracking into the crtc state. This allows
> precomputing the possibility of using PSR correctly, and it means we can
> safely call the psr enable/disable functions for any DP endcoder.
>
> As a nice bonus we get rid of some more crtc->config usage, which we
> want to kill off eventually.
>
> v2: Fix 'goto unlock' fail in intel_psr_enable() (Jani)
> Check intel_dp_is_edp() in is_edp_psr() (Jani)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
But I think an ack from Rodrigo might be in order.
There's also some follow-up to do with untangling
dev_priv->psr.psr2_support.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +
> drivers/gpu/drm/i915/intel_drv.h | 5 +++
> drivers/gpu/drm/i915/intel_psr.c | 85 +++++++++++++++++++++-------------------
> 3 files changed, 52 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b0f446b68f42..753404280a19 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (!HAS_DDI(dev_priv))
> intel_dp_set_clock(encoder, pipe_config);
>
> + intel_psr_compute_config(intel_dp, pipe_config);
> +
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b87946dcc53f..d61985f93d40 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -718,6 +718,9 @@ struct intel_crtc_state {
> struct intel_link_m_n dp_m2_n2;
> bool has_drrs;
>
> + bool has_psr;
> + bool has_psr2;
> +
> /*
> * Frequence the dpll for the port should run at. Differs from the
> * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
> @@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> void intel_psr_init(struct drm_i915_private *dev_priv);
> void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits);
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state);
>
> /* intel_runtime_pm.c */
> int intel_power_domains_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 5419cda83ba8..93b177cc4cbf 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -58,6 +58,9 @@
>
> static bool is_edp_psr(struct intel_dp *intel_dp)
> {
> + if (!intel_dp_is_edp(intel_dp))
> + return false;
> +
> return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
> }
>
> @@ -376,22 +379,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
> hsw_activate_psr1(intel_dp);
> }
>
> -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_crtc *crtc = dig_port->base.base.crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config->base.adjusted_mode;
> + &crtc_state->base.adjusted_mode;
> int psr_setup_time;
>
> - lockdep_assert_held(&dev_priv->psr.lock);
> - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> - WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
> + if (!HAS_PSR(dev_priv))
> + return;
>
> - dev_priv->psr.source_ok = false;
> + if (!is_edp_psr(intel_dp))
> + return;
> +
> + if (!i915_modparams.enable_psr) {
> + DRM_DEBUG_KMS("PSR disable by flag\n");
> + return;
> + }
>
> /*
> * HSW spec explicitly says PSR is tied to port A.
> @@ -402,66 +408,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> */
> if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> - return false;
> - }
> -
> - if (!i915_modparams.enable_psr) {
> - DRM_DEBUG_KMS("PSR disable by flag\n");
> - return false;
> + return;
> }
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> !dev_priv->psr.link_standby) {
> DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> - return false;
> + return;
> }
>
> if (IS_HASWELL(dev_priv) &&
> - I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> + I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> S3D_ENABLE) {
> DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> - return false;
> + return;
> }
>
> if (IS_HASWELL(dev_priv) &&
> adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> - return false;
> + return;
> }
>
> psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> if (psr_setup_time < 0) {
> DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> intel_dp->psr_dpcd[1]);
> - return false;
> + return;
> }
>
> if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> psr_setup_time);
> - return false;
> + return;
> + }
> +
> + /*
> + * FIXME psr2_support is messed up. It's both computed
> + * dynamically during PSR enable, and extracted from sink
> + * caps during eDP detection.
> + */
> + if (!dev_priv->psr.psr2_support) {
> + crtc_state->has_psr = true;
> + return;
> }
>
> /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
> - if (dev_priv->psr.psr2_support &&
> - (intel_crtc->config->pipe_src_w > 3200 ||
> - intel_crtc->config->pipe_src_h > 2000)) {
> - dev_priv->psr.psr2_support = false;
> - return false;
> + if (adjusted_mode->crtc_hdisplay > 3200 ||
> + adjusted_mode->crtc_vdisplay > 2000) {
> + DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
> + return;
> }
>
> /*
> * FIXME:enable psr2 only for y-cordinate psr2 panels
> * After gtc implementation , remove this restriction.
> */
> - if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
> + if (!dev_priv->psr.y_cord_support) {
> DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
> - return false;
> + return;
> }
>
> - dev_priv->psr.source_ok = true;
> - return true;
> + crtc_state->has_psr = true;
> + crtc_state->has_psr2 = true;
> }
>
> static void intel_psr_activate(struct intel_dp *intel_dp)
> @@ -531,14 +541,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (!HAS_PSR(dev_priv))
> + if (!crtc_state->has_psr)
> return;
>
> - if (!is_edp_psr(intel_dp)) {
> - DRM_DEBUG_KMS("PSR not supported by this panel\n");
> - return;
> - }
> -
> WARN_ON(dev_priv->drrs.dp);
> mutex_lock(&dev_priv->psr.lock);
> if (dev_priv->psr.enabled) {
> @@ -546,8 +551,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> goto unlock;
> }
>
> - if (!intel_psr_match_conditions(intel_dp))
> - goto unlock;
> + dev_priv->psr.psr2_support = crtc_state->has_psr2;
> + dev_priv->psr.source_ok = true;
>
> dev_priv->psr.busy_frontbuffer_bits = 0;
>
> @@ -668,7 +673,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (!HAS_PSR(dev_priv))
> + if (!old_crtc_state->has_psr)
> return;
>
> mutex_lock(&dev_priv->psr.lock);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Start tracking PSR state in crtc state (rev2)
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
` (3 preceding siblings ...)
2017-10-12 13:02 ` [PATCH v2] " Ville Syrjala
@ 2017-10-12 13:49 ` Patchwork
2017-10-12 18:54 ` ✗ Fi.CI.IGT: warning " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-10-12 13:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start tracking PSR state in crtc state (rev2)
URL : https://patchwork.freedesktop.org/series/31802/
State : success
== Summary ==
Series 31802v2 drm/i915: Start tracking PSR state in crtc state
https://patchwork.freedesktop.org/api/1.0/series/31802/revisions/2/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:454s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:474s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:390s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:573s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:285s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:517s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:523s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:530s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:514s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:559s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:437s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:271s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:592s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:450s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:462s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:503s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:473s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:502s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:490s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:657s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:471s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:649s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:539s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:514s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:576s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:434s
a869721e93a51c2bf425f322514527b4dc3944c8 drm-tip: 2017y-10m-12d-08h-30m-31s UTC integration manifest
54e8e4ae3e27 drm/i915: Start tracking PSR state in crtc state
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6008/
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] drm/i915: Start tracking PSR state in crtc state
2017-10-12 13:28 ` Jani Nikula
@ 2017-10-12 18:11 ` Rodrigo Vivi
2017-10-12 18:33 ` Ville Syrjälä
0 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Vivi @ 2017-10-12 18:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Oct 12, 2017 at 01:28:43PM +0000, Jani Nikula wrote:
> On Thu, 12 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add the minimal amount of PSR tracking into the crtc state. This allows
> > precomputing the possibility of using PSR correctly, and it means we can
> > safely call the psr enable/disable functions for any DP endcoder.
good idea.
> >
> > As a nice bonus we get rid of some more crtc->config usage, which we
> > want to kill off eventually.
> >
> > v2: Fix 'goto unlock' fail in intel_psr_enable() (Jani)
> > Check intel_dp_is_edp() in is_edp_psr() (Jani)
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> But I think an ack from Rodrigo might be in order.
>
> There's also some follow-up to do with untangling
> dev_priv->psr.psr2_support.
+Vathsala just in case ;)
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 2 +
> > drivers/gpu/drm/i915/intel_drv.h | 5 +++
> > drivers/gpu/drm/i915/intel_psr.c | 85 +++++++++++++++++++++-------------------
> > 3 files changed, 52 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index b0f446b68f42..753404280a19 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > if (!HAS_DDI(dev_priv))
> > intel_dp_set_clock(encoder, pipe_config);
> >
> > + intel_psr_compute_config(intel_dp, pipe_config);
> > +
> > return true;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index b87946dcc53f..d61985f93d40 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -718,6 +718,9 @@ struct intel_crtc_state {
> > struct intel_link_m_n dp_m2_n2;
> > bool has_drrs;
> >
> > + bool has_psr;
> > + bool has_psr2;
> > +
> > /*
> > * Frequence the dpll for the port should run at. Differs from the
> > * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
> > @@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > void intel_psr_init(struct drm_i915_private *dev_priv);
> > void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits);
> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state);
> >
> > /* intel_runtime_pm.c */
> > int intel_power_domains_init(struct drm_i915_private *);
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 5419cda83ba8..93b177cc4cbf 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -58,6 +58,9 @@
> >
> > static bool is_edp_psr(struct intel_dp *intel_dp)
> > {
> > + if (!intel_dp_is_edp(intel_dp))
> > + return false;
> > +
> > return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
> > }
> >
> > @@ -376,22 +379,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
> > hsw_activate_psr1(intel_dp);
> > }
> >
> > -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > - struct drm_device *dev = dig_port->base.base.dev;
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > - struct drm_crtc *crtc = dig_port->base.base.crtc;
> > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> > const struct drm_display_mode *adjusted_mode =
> > - &intel_crtc->config->base.adjusted_mode;
> > + &crtc_state->base.adjusted_mode;
> > int psr_setup_time;
> >
> > - lockdep_assert_held(&dev_priv->psr.lock);
> > - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > - WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
> > + if (!HAS_PSR(dev_priv))
> > + return;
> >
> > - dev_priv->psr.source_ok = false;
> > + if (!is_edp_psr(intel_dp))
> > + return;
> > +
> > + if (!i915_modparams.enable_psr) {
> > + DRM_DEBUG_KMS("PSR disable by flag\n");
> > + return;
> > + }
> >
> > /*
> > * HSW spec explicitly says PSR is tied to port A.
> > @@ -402,66 +408,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > */
> > if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> > DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> > - return false;
> > - }
> > -
> > - if (!i915_modparams.enable_psr) {
> > - DRM_DEBUG_KMS("PSR disable by flag\n");
> > - return false;
> > + return;
> > }
> >
> > if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> > !dev_priv->psr.link_standby) {
> > DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> > - return false;
> > + return;
> > }
> >
> > if (IS_HASWELL(dev_priv) &&
> > - I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> > + I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> > S3D_ENABLE) {
> > DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> > - return false;
> > + return;
> > }
> >
> > if (IS_HASWELL(dev_priv) &&
> > adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> > - return false;
> > + return;
> > }
> >
> > psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> > if (psr_setup_time < 0) {
> > DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> > intel_dp->psr_dpcd[1]);
> > - return false;
> > + return;
> > }
> >
> > if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> > DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> > psr_setup_time);
> > - return false;
> > + return;
> > + }
> > +
> > + /*
> > + * FIXME psr2_support is messed up. It's both computed
> > + * dynamically during PSR enable, and extracted from sink
> > + * caps during eDP detection.
> > + */
+Vathsala
> > + if (!dev_priv->psr.psr2_support) {
> > + crtc_state->has_psr = true;
> > + return;
> > }
> >
> > /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
> > - if (dev_priv->psr.psr2_support &&
> > - (intel_crtc->config->pipe_src_w > 3200 ||
> > - intel_crtc->config->pipe_src_h > 2000)) {
> > - dev_priv->psr.psr2_support = false;
> > - return false;
> > + if (adjusted_mode->crtc_hdisplay > 3200 ||
> > + adjusted_mode->crtc_vdisplay > 2000) {
> > + DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
> > + return;
> > }
> >
> > /*
> > * FIXME:enable psr2 only for y-cordinate psr2 panels
> > * After gtc implementation , remove this restriction.
> > */
> > - if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
> > + if (!dev_priv->psr.y_cord_support) {
> > DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
> > - return false;
> > + return;
> > }
> >
> > - dev_priv->psr.source_ok = true;
> > - return true;
> > + crtc_state->has_psr = true;
> > + crtc_state->has_psr2 = true;
> > }
> >
> > static void intel_psr_activate(struct intel_dp *intel_dp)
> > @@ -531,14 +541,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> >
> > - if (!HAS_PSR(dev_priv))
> > + if (!crtc_state->has_psr)
> > return;
> >
> > - if (!is_edp_psr(intel_dp)) {
> > - DRM_DEBUG_KMS("PSR not supported by this panel\n");
> > - return;
> > - }
> > -
> > WARN_ON(dev_priv->drrs.dp);
> > mutex_lock(&dev_priv->psr.lock);
> > if (dev_priv->psr.enabled) {
> > @@ -546,8 +551,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > goto unlock;
> > }
> >
> > - if (!intel_psr_match_conditions(intel_dp))
> > - goto unlock;
> > + dev_priv->psr.psr2_support = crtc_state->has_psr2;
> > + dev_priv->psr.source_ok = true;
> >
> > dev_priv->psr.busy_frontbuffer_bits = 0;
> >
> > @@ -668,7 +673,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> >
> > - if (!HAS_PSR(dev_priv))
> > + if (!old_crtc_state->has_psr)
> > return;
> >
> > mutex_lock(&dev_priv->psr.lock);
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] drm/i915: Start tracking PSR state in crtc state
2017-10-12 18:11 ` Rodrigo Vivi
@ 2017-10-12 18:33 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2017-10-12 18:33 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx
On Thu, Oct 12, 2017 at 11:11:45AM -0700, Rodrigo Vivi wrote:
> On Thu, Oct 12, 2017 at 01:28:43PM +0000, Jani Nikula wrote:
> > On Thu, 12 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Add the minimal amount of PSR tracking into the crtc state. This allows
> > > precomputing the possibility of using PSR correctly, and it means we can
> > > safely call the psr enable/disable functions for any DP endcoder.
>
> good idea.
>
> > >
> > > As a nice bonus we get rid of some more crtc->config usage, which we
> > > want to kill off eventually.
> > >
> > > v2: Fix 'goto unlock' fail in intel_psr_enable() (Jani)
> > > Check intel_dp_is_edp() in is_edp_psr() (Jani)
> > >
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thank you both. Patch pushed to dinq.
>
> >
> > But I think an ack from Rodrigo might be in order.
> >
> > There's also some follow-up to do with untangling
> > dev_priv->psr.psr2_support.
>
> +Vathsala just in case ;)
>
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_dp.c | 2 +
> > > drivers/gpu/drm/i915/intel_drv.h | 5 +++
> > > drivers/gpu/drm/i915/intel_psr.c | 85 +++++++++++++++++++++-------------------
> > > 3 files changed, 52 insertions(+), 40 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index b0f446b68f42..753404280a19 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -1832,6 +1832,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > > if (!HAS_DDI(dev_priv))
> > > intel_dp_set_clock(encoder, pipe_config);
> > >
> > > + intel_psr_compute_config(intel_dp, pipe_config);
> > > +
> > > return true;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index b87946dcc53f..d61985f93d40 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -718,6 +718,9 @@ struct intel_crtc_state {
> > > struct intel_link_m_n dp_m2_n2;
> > > bool has_drrs;
> > >
> > > + bool has_psr;
> > > + bool has_psr2;
> > > +
> > > /*
> > > * Frequence the dpll for the port should run at. Differs from the
> > > * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
> > > @@ -1764,6 +1767,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > > void intel_psr_init(struct drm_i915_private *dev_priv);
> > > void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
> > > unsigned frontbuffer_bits);
> > > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state);
> > >
> > > /* intel_runtime_pm.c */
> > > int intel_power_domains_init(struct drm_i915_private *);
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > > index 5419cda83ba8..93b177cc4cbf 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -58,6 +58,9 @@
> > >
> > > static bool is_edp_psr(struct intel_dp *intel_dp)
> > > {
> > > + if (!intel_dp_is_edp(intel_dp))
> > > + return false;
> > > +
> > > return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
> > > }
> > >
> > > @@ -376,22 +379,25 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
> > > hsw_activate_psr1(intel_dp);
> > > }
> > >
> > > -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state)
> > > {
> > > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > > - struct drm_device *dev = dig_port->base.base.dev;
> > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > - struct drm_crtc *crtc = dig_port->base.base.crtc;
> > > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> > > const struct drm_display_mode *adjusted_mode =
> > > - &intel_crtc->config->base.adjusted_mode;
> > > + &crtc_state->base.adjusted_mode;
> > > int psr_setup_time;
> > >
> > > - lockdep_assert_held(&dev_priv->psr.lock);
> > > - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > > - WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
> > > + if (!HAS_PSR(dev_priv))
> > > + return;
> > >
> > > - dev_priv->psr.source_ok = false;
> > > + if (!is_edp_psr(intel_dp))
> > > + return;
> > > +
> > > + if (!i915_modparams.enable_psr) {
> > > + DRM_DEBUG_KMS("PSR disable by flag\n");
> > > + return;
> > > + }
> > >
> > > /*
> > > * HSW spec explicitly says PSR is tied to port A.
> > > @@ -402,66 +408,70 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > > */
> > > if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> > > DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> > > - return false;
> > > - }
> > > -
> > > - if (!i915_modparams.enable_psr) {
> > > - DRM_DEBUG_KMS("PSR disable by flag\n");
> > > - return false;
> > > + return;
> > > }
> > >
> > > if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> > > !dev_priv->psr.link_standby) {
> > > DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> > > - return false;
> > > + return;
> > > }
> > >
> > > if (IS_HASWELL(dev_priv) &&
> > > - I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> > > + I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> > > S3D_ENABLE) {
> > > DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> > > - return false;
> > > + return;
> > > }
> > >
> > > if (IS_HASWELL(dev_priv) &&
> > > adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> > > - return false;
> > > + return;
> > > }
> > >
> > > psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> > > if (psr_setup_time < 0) {
> > > DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> > > intel_dp->psr_dpcd[1]);
> > > - return false;
> > > + return;
> > > }
> > >
> > > if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> > > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> > > DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> > > psr_setup_time);
> > > - return false;
> > > + return;
> > > + }
> > > +
> > > + /*
> > > + * FIXME psr2_support is messed up. It's both computed
> > > + * dynamically during PSR enable, and extracted from sink
> > > + * caps during eDP detection.
> > > + */
>
> +Vathsala
>
> > > + if (!dev_priv->psr.psr2_support) {
> > > + crtc_state->has_psr = true;
> > > + return;
> > > }
> > >
> > > /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
> > > - if (dev_priv->psr.psr2_support &&
> > > - (intel_crtc->config->pipe_src_w > 3200 ||
> > > - intel_crtc->config->pipe_src_h > 2000)) {
> > > - dev_priv->psr.psr2_support = false;
> > > - return false;
> > > + if (adjusted_mode->crtc_hdisplay > 3200 ||
> > > + adjusted_mode->crtc_vdisplay > 2000) {
> > > + DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n");
> > > + return;
> > > }
> > >
> > > /*
> > > * FIXME:enable psr2 only for y-cordinate psr2 panels
> > > * After gtc implementation , remove this restriction.
> > > */
> > > - if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
> > > + if (!dev_priv->psr.y_cord_support) {
> > > DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
> > > - return false;
> > > + return;
> > > }
> > >
> > > - dev_priv->psr.source_ok = true;
> > > - return true;
> > > + crtc_state->has_psr = true;
> > > + crtc_state->has_psr2 = true;
> > > }
> > >
> > > static void intel_psr_activate(struct intel_dp *intel_dp)
> > > @@ -531,14 +541,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > > struct drm_device *dev = intel_dig_port->base.base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > >
> > > - if (!HAS_PSR(dev_priv))
> > > + if (!crtc_state->has_psr)
> > > return;
> > >
> > > - if (!is_edp_psr(intel_dp)) {
> > > - DRM_DEBUG_KMS("PSR not supported by this panel\n");
> > > - return;
> > > - }
> > > -
> > > WARN_ON(dev_priv->drrs.dp);
> > > mutex_lock(&dev_priv->psr.lock);
> > > if (dev_priv->psr.enabled) {
> > > @@ -546,8 +551,8 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> > > goto unlock;
> > > }
> > >
> > > - if (!intel_psr_match_conditions(intel_dp))
> > > - goto unlock;
> > > + dev_priv->psr.psr2_support = crtc_state->has_psr2;
> > > + dev_priv->psr.source_ok = true;
> > >
> > > dev_priv->psr.busy_frontbuffer_bits = 0;
> > >
> > > @@ -668,7 +673,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> > > struct drm_device *dev = intel_dig_port->base.base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > >
> > > - if (!HAS_PSR(dev_priv))
> > > + if (!old_crtc_state->has_psr)
> > > return;
> > >
> > > mutex_lock(&dev_priv->psr.lock);
> >
> > --
> > Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Start tracking PSR state in crtc state (rev2)
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
` (4 preceding siblings ...)
2017-10-12 13:49 ` ✓ Fi.CI.BAT: success for drm/i915: Start tracking PSR state in crtc state (rev2) Patchwork
@ 2017-10-12 18:54 ` Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-10-12 18:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start tracking PSR state in crtc state (rev2)
URL : https://patchwork.freedesktop.org/series/31802/
State : warning
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
dmesg-warn -> PASS (shard-hsw) fdo#102614
Test kms_universal_plane:
Subgroup disable-primary-vs-flip-pipe-A:
pass -> DMESG-WARN (shard-hsw)
Test prime_self_import:
Subgroup reimport-vs-gem_close-race:
fail -> PASS (shard-hsw) fdo#102655
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2551 pass:1438 dwarn:1 dfail:0 fail:9 skip:1103 time:9661s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6008/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-10-12 18:54 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-12 10:09 [PATCH] drm/i915: Start tracking PSR state in crtc state Ville Syrjala
2017-10-12 10:40 ` Jani Nikula
2017-10-12 12:23 ` Ville Syrjälä
2017-10-12 12:30 ` Jani Nikula
2017-10-12 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-10-12 11:51 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-12 13:02 ` [PATCH v2] " Ville Syrjala
2017-10-12 13:28 ` Jani Nikula
2017-10-12 18:11 ` Rodrigo Vivi
2017-10-12 18:33 ` Ville Syrjälä
2017-10-12 13:49 ` ✓ Fi.CI.BAT: success for drm/i915: Start tracking PSR state in crtc state (rev2) Patchwork
2017-10-12 18:54 ` ✗ Fi.CI.IGT: warning " Patchwork
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