[PATCH igt 1/2] lib/sw_sync: Cleanup up error message for sw_sync_timeline_inc()

[PATCH igt 1/2] lib/sw_sync: Cleanup up error message for sw_sync_timeline_inc()

[Chris Wilson]

do_ioctl() generates an incompressible error string, replace with a
functio so that the assert is readable.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/sw_sync.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/lib/sw_sync.c b/lib/sw_sync.c
index 9b36dd85..e691952b 100644
--- a/lib/sw_sync.c
+++ b/lib/sw_sync.c
@@ -152,9 +152,21 @@ int sw_sync_timeline_create_fence(int fd, uint32_t seqno)
 	return fence;
 }
 
+static int __sw_sync_timeline_inc(int fd, uint32_t count)
+{
+	int err;
+
+	err = 0;
+	if (igt_ioctl(fd, INT_SYNC_IOC_INC, &count))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
 void sw_sync_timeline_inc(int fd, uint32_t count)
 {
-	do_ioctl(fd, INT_SYNC_IOC_INC, &count);
+	igt_assert_eq(__sw_sync_timeline_inc(fd, count), 0);
 }
 
 int sync_fence_merge(int fd1, int fd2)
-- 
2.15.0.rc0

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[PATCH igt 2/2] igt/gem_eio: Exercise set-wedging against request submission

[Chris Wilson]

Build up a large stockpile of requests, ~500,000, and feed them into the
system at 20KHz whilst simultaneously triggering set-wedged in order to
try and race i915_gem_set_wedged() against the engine->submit_request()
callback.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_eio.c | 205 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 205 insertions(+)

diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index 899cb627..864b6d16 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -34,12 +34,14 @@
 #include <fcntl.h>
 #include <inttypes.h>
 #include <errno.h>
+#include <signal.h>
 #include <sys/ioctl.h>
 
 #include <drm.h>
 
 #include "igt.h"
 #include "igt_sysfs.h"
+#include "igt_vgem.h"
 #include "sw_sync.h"
 
 IGT_TEST_DESCRIPTION("Test that specific ioctls report a wedged GPU (EIO).");
@@ -411,6 +413,203 @@ static void test_inflight_internal(int fd)
 	trigger_reset(fd);
 }
 
+struct cork {
+	int device;
+	uint32_t handle;
+	uint32_t fence;
+};
+
+static void plug(int fd, struct cork *c)
+{
+	struct vgem_bo bo;
+	int dmabuf;
+
+	c->device = drm_open_driver(DRIVER_VGEM);
+
+	bo.width = bo.height = 1;
+	bo.bpp = 4;
+	vgem_create(c->device, &bo);
+	c->fence = vgem_fence_attach(c->device, &bo, VGEM_FENCE_WRITE);
+
+	dmabuf = prime_handle_to_fd(c->device, bo.handle);
+	c->handle = prime_fd_to_handle(fd, dmabuf);
+	close(dmabuf);
+}
+
+static void unplug(struct cork *c)
+{
+	vgem_fence_signal(c->device, c->fence);
+	close(c->device);
+}
+
+static void alarm_handler(int sig)
+{
+}
+
+static int __execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+	int err = 0;
+	if (ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf))
+		err = -errno;
+	return err;
+}
+
+static unsigned int measure_ring_size(int fd, unsigned int ring)
+{
+	struct sigaction sa = { .sa_handler = alarm_handler };
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_execbuffer2 execbuf;
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	unsigned int count, last;
+	struct itimerval itv;
+	struct cork c;
+
+	memset(obj, 0, sizeof(obj));
+	obj[1].handle = gem_create(fd, 4096);
+	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj + 1);
+	execbuf.buffer_count = 1;
+	execbuf.flags = ring;
+	gem_execbuf(fd, &execbuf);
+	gem_sync(fd, obj[1].handle);
+
+	plug(fd, &c);
+	obj[0].handle = c.handle;
+
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = 2;
+	execbuf.rsvd1 = gem_context_create(fd);
+
+	sigaction(SIGALRM, &sa, NULL);
+	itv.it_interval.tv_sec = 0;
+	itv.it_interval.tv_usec = 100;
+	itv.it_value.tv_sec = 0;
+	itv.it_value.tv_usec = 1000;
+	setitimer(ITIMER_REAL, &itv, NULL);
+
+	last = -1;
+	count = 0;
+	do {
+		if (__execbuf(fd, &execbuf) == 0) {
+			count++;
+			continue;
+		}
+
+		if (last == count)
+			break;
+
+		last = count;
+	} while (1);
+
+	memset(&itv, 0, sizeof(itv));
+	setitimer(ITIMER_REAL, &itv, NULL);
+
+	unplug(&c);
+	gem_close(fd, obj[1].handle);
+	gem_context_destroy(fd, execbuf.rsvd1);
+
+	return count;
+}
+
+static void notify(union sigval arg)
+{
+	int timeline = arg.sival_int;
+
+	sw_sync_timeline_inc(timeline, 1); /* only now submit our batches */
+}
+
+static void wedgeme(int drm_fd)
+{
+	int dir = igt_debugfs_dir(drm_fd);
+
+	igt_sysfs_set(dir, "i915_wedged", "-1");
+
+	close(dir);
+}
+
+static void test_set_wedged(int fd)
+{
+#define NCTX 4096
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	const int ring_size = measure_ring_size(fd, 0) - 1;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 obj;
+	struct itimerspec its;
+	struct sigevent sev;
+	uint32_t *contexts;
+	timer_t timer;
+	int timeline;
+	int syncpt;
+
+	contexts = calloc(NCTX, sizeof(*contexts));
+	igt_assert(contexts);
+
+	for (int n = 0; n < NCTX; n++)
+		contexts[n] = gem_context_create(fd);
+
+	timeline = sw_sync_timeline_create();
+
+	memset(&obj, 0, sizeof(obj));
+	obj.handle = gem_create(fd, 4096);
+	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(&obj);
+	execbuf.buffer_count = 1;
+	execbuf.flags = I915_EXEC_FENCE_IN;
+
+	/* Build up a large orderly queue of requests */
+	syncpt = 1;
+	for (int n = 0; n < NCTX; n++) {
+		execbuf.rsvd1 = contexts[n];
+		for (int m = 0; m < ring_size; m++) {
+			execbuf.rsvd2 =
+				sw_sync_timeline_create_fence(timeline, syncpt);
+			gem_execbuf(fd, &execbuf);
+			close(execbuf.rsvd2);
+
+			syncpt++;
+		}
+	}
+	igt_debug("Queued %d requests\n", syncpt);
+
+	igt_require(i915_reset_control(false));
+
+	/* Feed each request in at 20KHz */
+	memset(&sev, 0, sizeof(sev));
+	sev.sigev_notify = SIGEV_THREAD;
+	sev.sigev_value.sival_int = timeline;
+	sev.sigev_notify_function = notify;
+	igt_assert(timer_create(CLOCK_MONOTONIC, &sev, &timer) == 0);
+
+	memset(&its, 0, sizeof(its));
+	its.it_value.tv_sec = 0;
+	its.it_value.tv_nsec = 20000;
+	its.it_interval.tv_sec = 0;
+	its.it_interval.tv_nsec = 5000;
+	igt_assert(timer_settime(timer, 0, &its, NULL) == 0);
+
+	igt_debug("Triggering wedge\n");
+	wedgeme(fd);
+
+	igt_debug("Cleaning up\n");
+	timer_delete(timer);
+	close(timeline);
+
+	for (int n = 0; n < NCTX; n++)
+		gem_context_destroy(fd, contexts[n]);
+	free(contexts);
+
+	gem_sync(fd, obj.handle);
+	gem_close(fd, obj.handle);
+
+	igt_assert(i915_reset_control(true));
+	trigger_reset(fd);
+#undef NCTX
+}
+
 #define HAVE_EXECLISTS 0x1
 #define HAVE_GUC 0x2
 #define HAVE_SEMAPHORES 0x4
@@ -502,4 +701,10 @@ igt_main
 
 	igt_subtest("in-flight-suspend")
 		test_inflight_suspend(fd);
+
+	igt_subtest("set-wedged-racing") {
+		igt_require(caps & HAVE_EXECLISTS);
+		igt_require_sw_sync();
+		test_set_wedged(fd);
+	}
 }
-- 
2.15.0.rc0

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✓ Fi.CI.BAT: success for series starting with [1/2] lib/sw_sync: Cleanup up error message for sw_sync_timeline_inc()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] lib/sw_sync: Cleanup up error message for sw_sync_timeline_inc()
URL   : https://patchwork.freedesktop.org/series/31934/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
58616272b23efce1e62a3ee0d37e13de6ffc012f igt/gem_eio: Check hang/eio recovery during suspend

with latest DRM-Tip kernel build CI_DRM_3235
5a6dc55bd5e6 drm-tip: 2017y-10m-13d-18h-14m-47s UTC integration manifest

Testlist changes:
+igt@gem_eio@set-wedged-racing

Test drv_module_reload:
        Subgroup basic-reload-inject:
                dmesg-warn -> INCOMPLETE (fi-cfl-s) fdo#103206

fdo#103206 https://bugs.freedesktop.org/show_bug.cgi?id=103206

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:454s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:476s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:394s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:574s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:289s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:526s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:528s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:540s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:532s
fi-cfl-s         total:288  pass:253  dwarn:3   dfail:0   fail:0   skip:31 
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:437s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:282s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:599s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:443s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:468s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:514s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:476s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:507s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:490s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:599s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:655s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:490s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:662s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:537s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:520s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:477s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:585s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:433s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_355/
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✓ Fi.CI.IGT: success for series starting with [1/2] lib/sw_sync: Cleanup up error message for sw_sync_timeline_inc()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] lib/sw_sync: Cleanup up error message for sw_sync_timeline_inc()
URL   : https://patchwork.freedesktop.org/series/31934/
State : success

== Summary ==

Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912
Test gem_exec_schedule:
        Subgroup preempt-other-bsd1:
                incomplete -> SKIP       (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw        total:2554 pass:1440 dwarn:1   dfail:0   fail:8   skip:1105 time:9711s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_355/shards.html
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