All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mark Rutland <mark.rutland@arm.com>
To: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: will.deacon@arm.com, jonathan.cameron@huawei.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	linuxarm@huawei.com, Anurup M <anurup.m@huawei.com>
Subject: Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
Date: Tue, 17 Oct 2017 16:18:26 +0100	[thread overview]
Message-ID: <20171017151826.acumob5ldoueiyg6@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <1503389277-134131-5-git-send-email-zhangshaokun@hisilicon.com>

On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
> SoC. This patch adds support for HHA PMU driver, Each HHA has own
> control, counter and interrupt registers and is an separate PMU. For
> each HHA PMU, it has 16-programable counters and each counter is
> free-running. Interrupt is supported to handle counter (48-bits)
> overflow.

My comments here are the same as for the L3C PMU driver.

Thanks,
Mark.

WARNING: multiple messages have this Message-ID (diff)
From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
Date: Tue, 17 Oct 2017 16:18:26 +0100	[thread overview]
Message-ID: <20171017151826.acumob5ldoueiyg6@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <1503389277-134131-5-git-send-email-zhangshaokun@hisilicon.com>

On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
> SoC. This patch adds support for HHA PMU driver, Each HHA has own
> control, counter and interrupt registers and is an separate PMU. For
> each HHA PMU, it has 16-programable counters and each counter is
> free-running. Interrupt is supported to handle counter (48-bits)
> overflow.

My comments here are the same as for the L3C PMU driver.

Thanks,
Mark.

  reply	other threads:[~2017-10-17 15:18 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-22  8:07 [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver Shaokun Zhang
2017-08-22  8:07 ` Shaokun Zhang
2017-08-22  8:07 ` [PATCH v5 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver Shaokun Zhang
2017-08-22  8:07   ` Shaokun Zhang
2017-08-22  8:07 ` [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore " Shaokun Zhang
2017-08-22  8:07   ` Shaokun Zhang
2017-10-17 15:06   ` Mark Rutland
2017-10-17 15:06     ` Mark Rutland
2017-10-18 13:19     ` Zhangshaokun
2017-10-18 13:19       ` Zhangshaokun
2017-08-22  8:07 ` [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C " Shaokun Zhang
2017-08-22  8:07   ` Shaokun Zhang
2017-10-17 15:16   ` Mark Rutland
2017-10-17 15:16     ` Mark Rutland
2017-10-18 13:33     ` Zhangshaokun
2017-10-18 13:33       ` Zhangshaokun
2017-10-18 13:55       ` Mark Rutland
2017-10-18 13:55         ` Mark Rutland
2017-10-18 14:08         ` Zhangshaokun
2017-10-18 14:08           ` Zhangshaokun
2017-08-22  8:07 ` [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA " Shaokun Zhang
2017-08-22  8:07   ` Shaokun Zhang
2017-10-17 15:18   ` Mark Rutland [this message]
2017-10-17 15:18     ` Mark Rutland
2017-10-18 13:35     ` Zhangshaokun
2017-10-18 13:35       ` Zhangshaokun
2017-08-22  8:07 ` [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC " Shaokun Zhang
2017-08-22  8:07   ` Shaokun Zhang
2017-10-17 15:21   ` Mark Rutland
2017-10-17 15:21     ` Mark Rutland
2017-10-18 13:37     ` Zhangshaokun
2017-10-18 13:37       ` Zhangshaokun
2017-08-22  8:07 ` [PATCH v5 6/6] arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support Shaokun Zhang
2017-08-22  8:07   ` Shaokun Zhang
2017-08-29 12:28 ` [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver Zhangshaokun
2017-08-29 12:28   ` Zhangshaokun
2017-09-21 10:40 ` Zhangshaokun
2017-09-21 10:40   ` Zhangshaokun
2017-10-09  8:17   ` Zhangshaokun
2017-10-09  8:17     ` Zhangshaokun

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20171017151826.acumob5ldoueiyg6@lakrids.cambridge.arm.com \
    --to=mark.rutland@arm.com \
    --cc=anurup.m@huawei.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linuxarm@huawei.com \
    --cc=will.deacon@arm.com \
    --cc=zhangshaokun@hisilicon.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.