* [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
@ 2017-10-16 23:44 Rodrigo Vivi
2017-10-17 0:03 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-10-16 23:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
DDIA Lane capability control 4 lane bit is not being set by firmware during
clone mode boot. This occurs when multiple monitors are connected during
boot. The driver will configure the port for 2 lane maximum width if this
bit is not set.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a9c0c16e3838..0ad915d71132 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
+ if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
+ port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
- DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
+ DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
max_lanes = 4;
}
--
2.13.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2)
2017-10-16 23:44 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Rodrigo Vivi
@ 2017-10-17 0:03 ` Patchwork
2017-10-17 8:04 ` [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Jani Nikula
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-10-17 0:03 UTC (permalink / raw)
To: Clint Taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2)
URL : https://patchwork.freedesktop.org/series/28204/
State : success
== Summary ==
Series 28204v2 drm/i915/cnl: DDIA Lane capability bit not set in clone mode
https://patchwork.freedesktop.org/api/1.0/series/28204/revisions/2/mbox/
Test gem_sync:
Subgroup basic-store-all:
pass -> FAIL (fi-ivb-3520m) fdo#100007
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:438s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:369s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:527s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:264s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:497s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:491s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:496s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:476s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:419s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:249s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:574s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:422s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:428s
fi-ivb-3520m total:289 pass:259 dwarn:0 dfail:0 fail:1 skip:29 time:489s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:459s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:492s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:576s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:475s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:582s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:545s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:449s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:646s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:526s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:492s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:455s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:577s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:421s
0673a9da7359e1575ac4581254110a0b4bc06c96 drm-tip: 2017y-10m-16d-20h-13m-40s UTC integration manifest
21b047663119 drm/i915/cnl: DDIA Lane capability bit not set in clone mode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6060/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-10-16 23:44 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Rodrigo Vivi
2017-10-17 0:03 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
@ 2017-10-17 8:04 ` Jani Nikula
2017-10-17 16:35 ` Rodrigo Vivi
2017-10-17 12:10 ` Ville Syrjälä
2017-10-17 13:57 ` ✗ Fi.CI.IGT: failure for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
3 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2017-10-17 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
On Mon, 16 Oct 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> DDIA Lane capability control 4 lane bit is not being set by firmware during
> clone mode boot. This occurs when multiple monitors are connected during
> boot. The driver will configure the port for 2 lane maximum width if this
> bit is not set.
Please be more specific about what you mean with clone mode.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a9c0c16e3838..0ad915d71132 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
The comment above needs updating too. Also, it doesn't say anything
about cloning.
BR,
Jani.
> - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> + if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> + port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> max_lanes = 4;
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-10-16 23:44 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Rodrigo Vivi
2017-10-17 0:03 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
2017-10-17 8:04 ` [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Jani Nikula
@ 2017-10-17 12:10 ` Ville Syrjälä
2017-10-17 16:02 ` Ville Syrjälä
2017-10-17 16:27 ` Rodrigo Vivi
2017-10-17 13:57 ` ✗ Fi.CI.IGT: failure for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
3 siblings, 2 replies; 12+ messages in thread
From: Ville Syrjälä @ 2017-10-17 12:10 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Mon, Oct 16, 2017 at 04:44:49PM -0700, Rodrigo Vivi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> DDIA Lane capability control 4 lane bit is not being set by firmware during
> clone mode boot. This occurs when multiple monitors are connected during
> boot. The driver will configure the port for 2 lane maximum width if this
> bit is not set.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a9c0c16e3838..0ad915d71132 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> + if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> + port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> max_lanes = 4;
> }
CNL has DDI E so this doesn't make sense. If there are CNLs out there
that don't actually use DDI E but forget to configure the bifurcation
coreectly, then we'll need a fancier way to detect that. Ie. we need to
be sure DDI E isn't going to be used before we can force DDI A to use
4 lanes.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2)
2017-10-16 23:44 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Rodrigo Vivi
` (2 preceding siblings ...)
2017-10-17 12:10 ` Ville Syrjälä
@ 2017-10-17 13:57 ` Patchwork
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-10-17 13:57 UTC (permalink / raw)
To: Clint Taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2)
URL : https://patchwork.freedesktop.org/series/28204/
State : failure
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu:
skip -> INCOMPLETE (shard-hsw)
Test kms_flip:
Subgroup flip-vs-modeset-interruptible:
pass -> DMESG-WARN (shard-hsw) fdo#102557
Test gem_exec_params:
Subgroup invalid-bsd2-flag-on-render:
pass -> INCOMPLETE (shard-hsw)
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-hsw) fdo#102254
fdo#102557 https://bugs.freedesktop.org/show_bug.cgi?id=102557
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
shard-hsw total:2349 pass:1262 dwarn:1 dfail:0 fail:9 skip:978 time:8125s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6060/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-10-17 12:10 ` Ville Syrjälä
@ 2017-10-17 16:02 ` Ville Syrjälä
2017-10-17 16:27 ` Rodrigo Vivi
1 sibling, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2017-10-17 16:02 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Oct 17, 2017 at 03:10:16PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 16, 2017 at 04:44:49PM -0700, Rodrigo Vivi wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> >
> > DDIA Lane capability control 4 lane bit is not being set by firmware during
> > clone mode boot. This occurs when multiple monitors are connected during
> > boot. The driver will configure the port for 2 lane maximum width if this
> > bit is not set.
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a9c0c16e3838..0ad915d71132 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > * configuration so that we use the proper lane count for our
> > * calculations.
> > */
> > - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > + if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > + port == PORT_A) {
> > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > max_lanes = 4;
> > }
>
> CNL has DDI E so this doesn't make sense. If there are CNLs out there
> that don't actually use DDI E but forget to configure the bifurcation
> coreectly, then we'll need a fancier way to detect that. Ie. we need to
> be sure DDI E isn't going to be used before we can force DDI A to use
> 4 lanes.
Oh, we'd really need some way to make sure all four lanes from DDI A are
really connected to the panel. Otherwise link training would surely
fail if we try to use four lanes.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-10-17 12:10 ` Ville Syrjälä
2017-10-17 16:02 ` Ville Syrjälä
@ 2017-10-17 16:27 ` Rodrigo Vivi
2017-10-17 16:35 ` Ville Syrjälä
1 sibling, 1 reply; 12+ messages in thread
From: Rodrigo Vivi @ 2017-10-17 16:27 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Oct 17, 2017 at 12:10:16PM +0000, Ville Syrjälä wrote:
> On Mon, Oct 16, 2017 at 04:44:49PM -0700, Rodrigo Vivi wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> >
> > DDIA Lane capability control 4 lane bit is not being set by firmware during
> > clone mode boot. This occurs when multiple monitors are connected during
> > boot. The driver will configure the port for 2 lane maximum width if this
> > bit is not set.
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a9c0c16e3838..0ad915d71132 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > * configuration so that we use the proper lane count for our
> > * calculations.
> > */
> > - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > + if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > + port == PORT_A) {
> > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > max_lanes = 4;
> > }
>
> CNL has DDI E so this doesn't make sense. If there are CNLs out there
> that don't actually use DDI E but forget to configure the bifurcation
> coreectly, then we'll need a fancier way to detect that. Ie. we need to
> be sure DDI E isn't going to be used before we can force DDI A to use
> 4 lanes.
We got the confirmation that DDI E is not there for any of the current SKUs
what support is currently merged.
DDI E is only available on the SKUs that posted yesterday... the one that
supports DDI F that is the proper split. Also when DDI F is in use DDI E
cannot be used because the interrupts handling.
So apparently this is not going to be used at all. But I agree that it
would be good if we could have a smarter way to detect it... Any idea?
Thanks,
Rodrigo.
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-10-17 8:04 ` [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Jani Nikula
@ 2017-10-17 16:35 ` Rodrigo Vivi
0 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-10-17 16:35 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 17, 2017 at 08:04:04AM +0000, Jani Nikula wrote:
> On Mon, 16 Oct 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> >
> > DDIA Lane capability control 4 lane bit is not being set by firmware during
> > clone mode boot. This occurs when multiple monitors are connected during
> > boot. The driver will configure the port for 2 lane maximum width if this
> > bit is not set.
>
> Please be more specific about what you mean with clone mode.
Oh... yes, we need to change the comment.
I didn't see any relation here to the clone mode.
If eDP comes back on boot and HDMI comes later everything worked.
If HDMI is also present during boot at some point during initialization
we have probably a long pulse on edp that hits our check of max_level
and change that to 2, because this bit is unset as we were expecting.
I will grab more information here on the flow and proper update the commit message.
>
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a9c0c16e3838..0ad915d71132 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > * configuration so that we use the proper lane count for our
> > * calculations.
> > */
>
> The comment above needs updating too. Also, it doesn't say anything
> about cloning.
I will update this comment also. But also not related to clone mode I believe.
>
> BR,
> Jani.
>
> > - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > + if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > + port == PORT_A) {
> > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > max_lanes = 4;
> > }
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-10-17 16:27 ` Rodrigo Vivi
@ 2017-10-17 16:35 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2017-10-17 16:35 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Oct 17, 2017 at 09:27:39AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 17, 2017 at 12:10:16PM +0000, Ville Syrjälä wrote:
> > On Mon, Oct 16, 2017 at 04:44:49PM -0700, Rodrigo Vivi wrote:
> > > From: Clint Taylor <clinton.a.taylor@intel.com>
> > >
> > > DDIA Lane capability control 4 lane bit is not being set by firmware during
> > > clone mode boot. This occurs when multiple monitors are connected during
> > > boot. The driver will configure the port for 2 lane maximum width if this
> > > bit is not set.
> > >
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index a9c0c16e3838..0ad915d71132 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> > > * configuration so that we use the proper lane count for our
> > > * calculations.
> > > */
> > > - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > > + if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > > + port == PORT_A) {
> > > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > > - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > > + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> > > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > > max_lanes = 4;
> > > }
> >
> > CNL has DDI E so this doesn't make sense. If there are CNLs out there
> > that don't actually use DDI E but forget to configure the bifurcation
> > coreectly, then we'll need a fancier way to detect that. Ie. we need to
> > be sure DDI E isn't going to be used before we can force DDI A to use
> > 4 lanes.
>
> We got the confirmation that DDI E is not there for any of the current SKUs
> what support is currently merged.
>
> DDI E is only available on the SKUs that posted yesterday... the one that
> supports DDI F that is the proper split. Also when DDI F is in use DDI E
> cannot be used because the interrupts handling.
>
> So apparently this is not going to be used at all. But I agree that it
> would be good if we could have a smarter way to detect it... Any idea?
Looks like DDI E doesn't have a hardware strap, so I suppose you could
just check vbt.ddi_port_info. That still doesn't protect us against
accidentally using 4 lanes when we should have used 2. Not sure there's
anything in VBT that could help us there.
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-08-01 20:23 ` Vivi, Rodrigo
@ 2017-08-08 19:53 ` Rodrigo Vivi
0 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2017-08-08 19:53 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, Runyan, Arthur J
we confirmed that with current supported CNL skus using IS_CANNONLAKE
is enogh for now.
So feel free to change that if and use
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
on the v2....
On Tue, Aug 1, 2017 at 1:23 PM, Vivi, Rodrigo <rodrigo.vivi@intel.com> wrote:
> + Art, couple questions below
>
> On Tue, 2017-08-01 at 09:56 -0700, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> DDIA Lane capability control 4 lane bit is not being set by firmware during
>> clone mode boot. This occurs when multiple monitors are connected during
>> boot. The driver will configure the port for 2 lane maximum width if this
>> bit is not set.
>>
>> Once DDIA/E lane split is supported in vbt and the i915 driver we will need
>> to revisit this code.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 494fbe0..e7644b4 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2713,9 +2713,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>
> we would need to fix more comment lines:
>
> /*
> * Bspec says that DDI_A_4_LANES is the only supported
> configuration
> * for Broxton. Yet some BIOS fail to set this bit on port A if
> eDP
> * wasn't lit up at boot. Force this bit on in our internal
>> * configuration so that we use the proper lane count for our
>> * calculations.
>> */
>
> But I believe the approach we currently have with this might not be
> optimal. If BIOS is not bringing the port A up why should we expect it
> to set this bit ever? We probably need to be able to do it by ourselves,
> without expecting others to do...
>
> However, I've never seen a production BIOS that never brings port A when
> it is present. And it is also true that spec tells: "This field must be
> programmed at system boot based on board configuration and may not be
> changed afterwards."
>
> So I have kind of mixed feelings here on this bit.
>
> For BXT it is so clear: "Not supported on Broxton."
>
> Also few other future cases the 0 won't be valid, but not entirely sure
> if this is always true. Art?
>
> I just noticed on spec that DDI E for CNL-U and CNL-Y are marked as "not
> supported", what means that for that SKU we should be able to add this
> workaround here, but at same time means that we need to remove the power
> wells support for DDI-E for these SKUs probably.
>
> Art, could/should we set this bit blindly for all CNL?
>
> and if yes:
>
> Art, will it always be a decision based by SKUs now on? Or should we
> really rely on BIOS?
>
> Is there another way to detect the port E presence? I don't believe VBT
> has that info in a reliable way, does it? Otherwise we would be using it
> already for the missed straps...
>
>
> Thanks,
> Rodrigo.
>
>> - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
>> + if ((IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
>> + port == PORT_A) {
>> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
>> - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
>> + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
>> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>> max_lanes = 4;
>> }
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
2017-08-01 16:56 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode clinton.a.taylor
@ 2017-08-01 20:23 ` Vivi, Rodrigo
2017-08-08 19:53 ` Rodrigo Vivi
0 siblings, 1 reply; 12+ messages in thread
From: Vivi, Rodrigo @ 2017-08-01 20:23 UTC (permalink / raw)
To: Runyan, Arthur J, Taylor, Clinton A; +Cc: intel-gfx
+ Art, couple questions below
On Tue, 2017-08-01 at 09:56 -0700, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> DDIA Lane capability control 4 lane bit is not being set by firmware during
> clone mode boot. This occurs when multiple monitors are connected during
> boot. The driver will configure the port for 2 lane maximum width if this
> bit is not set.
>
> Once DDIA/E lane split is supported in vbt and the i915 driver we will need
> to revisit this code.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 494fbe0..e7644b4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2713,9 +2713,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
we would need to fix more comment lines:
/*
* Bspec says that DDI_A_4_LANES is the only supported
configuration
* for Broxton. Yet some BIOS fail to set this bit on port A if
eDP
* wasn't lit up at boot. Force this bit on in our internal
> * configuration so that we use the proper lane count for our
> * calculations.
> */
But I believe the approach we currently have with this might not be
optimal. If BIOS is not bringing the port A up why should we expect it
to set this bit ever? We probably need to be able to do it by ourselves,
without expecting others to do...
However, I've never seen a production BIOS that never brings port A when
it is present. And it is also true that spec tells: "This field must be
programmed at system boot based on board configuration and may not be
changed afterwards."
So I have kind of mixed feelings here on this bit.
For BXT it is so clear: "Not supported on Broxton."
Also few other future cases the 0 won't be valid, but not entirely sure
if this is always true. Art?
I just noticed on spec that DDI E for CNL-U and CNL-Y are marked as "not
supported", what means that for that SKU we should be able to add this
workaround here, but at same time means that we need to remove the power
wells support for DDI-E for these SKUs probably.
Art, could/should we set this bit blindly for all CNL?
and if yes:
Art, will it always be a decision based by SKUs now on? Or should we
really rely on BIOS?
Is there another way to detect the port E presence? I don't believe VBT
has that info in a reliable way, does it? Otherwise we would be using it
already for the missed straps...
Thanks,
Rodrigo.
> - if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> + if ((IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> + port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> max_lanes = 4;
> }
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode
@ 2017-08-01 16:56 clinton.a.taylor
2017-08-01 20:23 ` Vivi, Rodrigo
0 siblings, 1 reply; 12+ messages in thread
From: clinton.a.taylor @ 2017-08-01 16:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
DDIA Lane capability control 4 lane bit is not being set by firmware during
clone mode boot. This occurs when multiple monitors are connected during
boot. The driver will configure the port for 2 lane maximum width if this
bit is not set.
Once DDIA/E lane split is supported in vbt and the i915 driver we will need
to revisit this code.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 494fbe0..e7644b4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2713,9 +2713,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
+ if ((IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
+ port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
- DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
+ DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
max_lanes = 4;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-10-17 16:36 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-16 23:44 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Rodrigo Vivi
2017-10-17 0:03 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
2017-10-17 8:04 ` [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode Jani Nikula
2017-10-17 16:35 ` Rodrigo Vivi
2017-10-17 12:10 ` Ville Syrjälä
2017-10-17 16:02 ` Ville Syrjälä
2017-10-17 16:27 ` Rodrigo Vivi
2017-10-17 16:35 ` Ville Syrjälä
2017-10-17 13:57 ` ✗ Fi.CI.IGT: failure for drm/i915/cnl: DDIA Lane capability bit not set in clone mode (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-08-01 16:56 [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode clinton.a.taylor
2017-08-01 20:23 ` Vivi, Rodrigo
2017-08-08 19:53 ` Rodrigo Vivi
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