* [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support
@ 2017-10-23 20:10 Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 01/27] imx_fec: Do not link to netdev Andrey Smirnov
` (23 more replies)
0 siblings, 24 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Hi everyone,
This v2 of the patch series containing the work that I've done in
order to enable support for i.MX7 emulation in QEMU.
As the one before last commit in the series states the supported i.MX7
features are:
* up to 2 Cortex A9 cores (SMP works with PSCI)
* A7 MPCORE (identical to A15 MPCORE)
* 4 GPTs modules
* 7 GPIO controllers
* 2 IOMUXC controllers
* 1 CCM module
* 1 SVNS module
* 1 SRC module
* 1 GPCv2 controller
* 4 eCSPI controllers
* 4 I2C controllers
* 7 i.MX UART controllers
* 2 FlexCAN controllers
* 2 Ethernet controllers (FEC)
* 3 SD controllers (USDHC)
* 4 WDT modules
* 1 SDMA module
* 1 GPR module
* 2 USBMISC modules
* 2 ADC modules
* 1 PCIe controller
Feedback is welcome!
Changes since [v1]:
- Patchset no longer relies on "ignore_memory_transaction_failures = false"
for its functionality
- As a consequnce of implementing the above a number of patches
implementing dummy IP block emulation as well as PCIe emulation
patches that I alluded to in [v1] are now included in this patch
series
- "has_el3" property is no longer being set to "false" as a part
of intialization of A7 CPU. I couldn't reproduce the issues that
I thought I was having, so I just dropped that code.
- A number of smaller feedback items from Peter and other has been
incorporated into the patches.
Peter, I didn't hear anything from you about the code of
mcimx7d_add_psci_node(), as discussed here:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg486874.html
so I kept the original code intact. As I mentioned before, my goal was
to be able to boot into vanilla Linux kerenel and have working SMP
without needing to use a PSCI implementing bootloader. If that is
something that new board code shouldn't do, please let me know.
Thanks,
Andrey Smirnov
[v1] https://lists.gnu.org/archive/html/qemu-devel/2017-09/msg04770.html
P.S.: I don't know the best way to specify mailing list message
archives, so if I did it wrong please let me know.
Andrey Smirnov (27):
imx_fec: Do not link to netdev
imx_fec: Refactor imx_eth_enable_rx()
imx_fec: Change queue flushing heuristics
imx_fec: Use ENET_FTRL to determine truncation length
imx_fec: Use MIN instead of explicit ternary operator
imx_fec: Emulate SHIFT16 in ENETx_RACC
imx_fec: Add support for multiple Tx DMA rings
imx_fec: Use correct length for packet size
imx_fec: Fix a typo in imx_enet_receive()
imx_fec: Reserve full 4K page for the register file
sdhci: Add i.MX specific subtype of SDHCI
sdhci: Implement write method of ACMD12ERRSTS register
i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks
i.MX: Add code to emulate i.MX2 watchdog IP block
i.MX: Add code to emulate i.MX7 SNVS IP-block
i.MX: Add code to emulate GPCv2 IP block
i.MX: Add code to emulate i.MX7 IOMUXC IP block
i.MX: Add i.MX7 GPT variant
i.MX: Add code to emulate SDMA IP block
i.MX: Add code to emulate FlexCAN IP block
i.MX: Add implementation of i.MX7 GPR IP block
pci: Add support for Designware IP block
i.MX: Add code to emulate i.MX7 USBMISC IP block
i.MX: Add code to emulate i.MX7 ADC IP block
i.MX: Add code to emulate i.MX7 SRC IP-block
i.MX: Add i.MX7 SOC implementation.
Implement support for i.MX7 Sabre board
default-configs/arm-softmmu.mak | 3 +
hw/arm/Makefile.objs | 2 +
hw/arm/fsl-imx6.c | 1 +
hw/arm/fsl-imx7.c | 596 +++++++++++++++++++++++++++++++++++++
hw/arm/mcimx7d-sabre.c | 101 +++++++
hw/dma/Makefile.objs | 1 +
hw/dma/imx_sdma.c | 99 +++++++
hw/intc/Makefile.objs | 2 +-
hw/intc/imx_gpcv2.c | 125 ++++++++
hw/misc/Makefile.objs | 8 +
hw/misc/imx2_wdt.c | 88 ++++++
hw/misc/imx7_adc.c | 99 +++++++
hw/misc/imx7_ccm.c | 233 +++++++++++++++
hw/misc/imx7_gpr.c | 119 ++++++++
hw/misc/imx7_iomuxc.c | 99 +++++++
hw/misc/imx7_snvs.c | 83 ++++++
hw/misc/imx7_src.c | 93 ++++++
hw/misc/imx_flexcan.c | 99 +++++++
hw/net/imx_fec.c | 163 ++++++++---
hw/pci-host/Makefile.objs | 2 +
hw/pci-host/designware.c | 614 +++++++++++++++++++++++++++++++++++++++
hw/sd/sdhci-internal.h | 15 +
hw/sd/sdhci.c | 130 ++++++++-
hw/timer/imx_gpt.c | 25 ++
hw/usb/Makefile.objs | 1 +
hw/usb/imx-usbmisc.c | 99 +++++++
include/hw/arm/fsl-imx7.h | 217 ++++++++++++++
include/hw/dma/imx_sdma.h | 22 ++
include/hw/intc/imx_gpcv2.h | 22 ++
include/hw/misc/imx2_wdt.h | 34 +++
include/hw/misc/imx7_adc.h | 22 ++
include/hw/misc/imx7_ccm.h | 130 +++++++++
include/hw/misc/imx7_gpr.h | 28 ++
include/hw/misc/imx7_iomuxc.h | 22 ++
include/hw/misc/imx7_snvs.h | 35 +++
include/hw/misc/imx7_src.h | 22 ++
include/hw/misc/imx_flexcan.h | 22 ++
include/hw/net/imx_fec.h | 24 +-
include/hw/pci-host/designware.h | 92 ++++++
include/hw/pci/pci_ids.h | 2 +
include/hw/sd/sdhci.h | 8 +
include/hw/timer/imx_gpt.h | 1 +
include/hw/usb/imx-usbmisc.h | 22 ++
43 files changed, 3581 insertions(+), 44 deletions(-)
create mode 100644 hw/arm/fsl-imx7.c
create mode 100644 hw/arm/mcimx7d-sabre.c
create mode 100644 hw/dma/imx_sdma.c
create mode 100644 hw/intc/imx_gpcv2.c
create mode 100644 hw/misc/imx2_wdt.c
create mode 100644 hw/misc/imx7_adc.c
create mode 100644 hw/misc/imx7_ccm.c
create mode 100644 hw/misc/imx7_gpr.c
create mode 100644 hw/misc/imx7_iomuxc.c
create mode 100644 hw/misc/imx7_snvs.c
create mode 100644 hw/misc/imx7_src.c
create mode 100644 hw/misc/imx_flexcan.c
create mode 100644 hw/pci-host/designware.c
create mode 100644 hw/usb/imx-usbmisc.c
create mode 100644 include/hw/arm/fsl-imx7.h
create mode 100644 include/hw/dma/imx_sdma.h
create mode 100644 include/hw/intc/imx_gpcv2.h
create mode 100644 include/hw/misc/imx2_wdt.h
create mode 100644 include/hw/misc/imx7_adc.h
create mode 100644 include/hw/misc/imx7_ccm.h
create mode 100644 include/hw/misc/imx7_gpr.h
create mode 100644 include/hw/misc/imx7_iomuxc.h
create mode 100644 include/hw/misc/imx7_snvs.h
create mode 100644 include/hw/misc/imx7_src.h
create mode 100644 include/hw/misc/imx_flexcan.h
create mode 100644 include/hw/pci-host/designware.h
create mode 100644 include/hw/usb/imx-usbmisc.h
--
2.13.5
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 01/27] imx_fec: Do not link to netdev
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 02/27] imx_fec: Refactor imx_eth_enable_rx() Andrey Smirnov
` (22 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Binding to a particular netdev doesn't seem to belong to this layer
and should probably be done as a part of board or SoC specific code.
Convert all of the users of this IP block to use
qdev_set_nic_properties() instead.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/arm/fsl-imx6.c | 1 +
hw/net/imx_fec.c | 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 26fd214004..2ed7146c52 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -385,6 +385,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
spi_table[i].irq));
}
+ qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
if (err) {
error_propagate(errp, err);
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 90e6ee35ba..88b4b049d7 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1171,8 +1171,6 @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
qemu_macaddr_default_if_unset(&s->conf.macaddr);
- s->conf.peers.ncs[0] = nd_table[0].netdev;
-
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
object_get_typename(OBJECT(dev)),
DEVICE(dev)->id, s);
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 02/27] imx_fec: Refactor imx_eth_enable_rx()
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 01/27] imx_fec: Do not link to netdev Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 03/27] imx_fec: Change queue flushing heuristics Andrey Smirnov
` (21 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Refactor imx_eth_enable_rx() to have more meaningfull variable name
than 'tmp' and to reduce number of logical negations done.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 88b4b049d7..8b2e4b8ffe 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -536,19 +536,19 @@ static void imx_eth_do_tx(IMXFECState *s)
static void imx_eth_enable_rx(IMXFECState *s)
{
IMXFECBufDesc bd;
- bool tmp;
+ bool rx_ring_full;
imx_fec_read_bd(&bd, s->rx_descriptor);
- tmp = ((bd.flags & ENET_BD_E) != 0);
+ rx_ring_full = !(bd.flags & ENET_BD_E);
- if (!tmp) {
+ if (rx_ring_full) {
FEC_PRINTF("RX buffer full\n");
} else if (!s->regs[ENET_RDAR]) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
- s->regs[ENET_RDAR] = tmp ? ENET_RDAR_RDAR : 0;
+ s->regs[ENET_RDAR] = rx_ring_full ? 0 : ENET_RDAR_RDAR;
}
static void imx_eth_reset(DeviceState *d)
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 03/27] imx_fec: Change queue flushing heuristics
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 01/27] imx_fec: Do not link to netdev Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 02/27] imx_fec: Refactor imx_eth_enable_rx() Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 04/27] imx_fec: Use ENET_FTRL to determine truncation length Andrey Smirnov
` (20 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
In current implementation, packet queue flushing logic seem to suffer
from a deadlock like scenario if a packet is received by the interface
before before Rx ring is initialized by Guest's driver. Consider the
following sequence of events:
1. A QEMU instance is started against a TAP device on Linux
host, running Linux guest, e. g., something to the effect
of:
qemu-system-arm \
-net nic,model=imx.fec,netdev=lan0 \
netdev tap,id=lan0,ifname=tap0,script=no,downscript=no \
... rest of the arguments ...
2. Once QEMU starts, but before guest reaches the point where
FEC deriver is done initializing the HW, Guest, via TAP
interface, receives a number of multicast MDNS packets from
Host (not necessarily true for every OS, but it happens at
least on Fedora 25)
3. Recieving a packet in such a state results in
imx_eth_can_receive() returning '0', which in turn causes
tap_send() to disable corresponding event (tap.c:203)
4. Once Guest's driver reaches the point where it is ready to
recieve packets it prepares Rx ring descriptors and writes
ENET_RDAR_RDAR to ENET_RDAR register to indicate to HW that
more descriptors are ready. And at this points emulation
layer does this:
s->regs[index] = ENET_RDAR_RDAR;
imx_eth_enable_rx(s);
which, combined with:
if (!s->regs[ENET_RDAR]) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
results in Rx queue never being flushed and corresponding
I/O event beign disabled.
To prevent the problem, change the code to always flush packet queue
when ENET_RDAR transitions 0 -> ENET_RDAR_RDAR.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 12 ++++++------
include/hw/net/imx_fec.h | 1 +
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 8b2e4b8ffe..eb034ffd0c 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -533,7 +533,7 @@ static void imx_eth_do_tx(IMXFECState *s)
}
}
-static void imx_eth_enable_rx(IMXFECState *s)
+static void imx_eth_enable_rx(IMXFECState *s, bool flush)
{
IMXFECBufDesc bd;
bool rx_ring_full;
@@ -544,7 +544,7 @@ static void imx_eth_enable_rx(IMXFECState *s)
if (rx_ring_full) {
FEC_PRINTF("RX buffer full\n");
- } else if (!s->regs[ENET_RDAR]) {
+ } else if (flush) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
@@ -807,7 +807,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
if (!s->regs[index]) {
s->regs[index] = ENET_RDAR_RDAR;
- imx_eth_enable_rx(s);
+ imx_eth_enable_rx(s, true);
}
} else {
s->regs[index] = 0;
@@ -930,7 +930,7 @@ static int imx_eth_can_receive(NetClientState *nc)
FEC_PRINTF("\n");
- return s->regs[ENET_RDAR] ? 1 : 0;
+ return !!s->regs[ENET_RDAR];
}
static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
@@ -1020,7 +1020,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
}
}
s->rx_descriptor = addr;
- imx_eth_enable_rx(s);
+ imx_eth_enable_rx(s, false);
imx_eth_update(s);
return len;
}
@@ -1116,7 +1116,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
}
}
s->rx_descriptor = addr;
- imx_eth_enable_rx(s);
+ imx_eth_enable_rx(s, false);
imx_eth_update(s);
return len;
}
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index 62ad473b05..4bc8f03ec2 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -252,6 +252,7 @@ typedef struct IMXFECState {
uint32_t phy_int_mask;
bool is_fec;
+ bool needs_flush;
} IMXFECState;
#endif
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 04/27] imx_fec: Use ENET_FTRL to determine truncation length
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (2 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 03/27] imx_fec: Change queue flushing heuristics Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 05/27] imx_fec: Use MIN instead of explicit ternary operator Andrey Smirnov
` (19 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Frame truncation length, TRUNC_FL, is determined by the contents of
ENET_FTRL register, so convert the code to use it instead of a
hardcoded constant.
To avoid the case where TRUNC_FL is greater that ENET_MAX_FRAME_SIZE,
increase the value of the latter to its theoretical maximum of 16K.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 4 ++--
include/hw/net/imx_fec.h | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index eb034ffd0c..dda0816fb3 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1052,8 +1052,8 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
crc_ptr = (uint8_t *) &crc;
/* Huge frames are truncted. */
- if (size > ENET_MAX_FRAME_SIZE) {
- size = ENET_MAX_FRAME_SIZE;
+ if (size > s->regs[ENET_FTRL]) {
+ size = s->regs[ENET_FTRL];
flags |= ENET_BD_TR | ENET_BD_LG;
}
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index 4bc8f03ec2..0fcc4f0c71 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -86,7 +86,6 @@
#define ENET_TCCR3 393
#define ENET_MAX 400
-#define ENET_MAX_FRAME_SIZE 2032
/* EIR and EIMR */
#define ENET_INT_HB (1 << 31)
@@ -155,6 +154,8 @@
#define ENET_RCR_NLC (1 << 30)
#define ENET_RCR_GRS (1 << 31)
+#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
+
/* TCR */
#define ENET_TCR_GTS (1 << 0)
#define ENET_TCR_FDEN (1 << 2)
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 05/27] imx_fec: Use MIN instead of explicit ternary operator
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (3 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 04/27] imx_fec: Use ENET_FTRL to determine truncation length Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 06/27] imx_fec: Emulate SHIFT16 in ENETx_RACC Andrey Smirnov
` (18 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index dda0816fb3..18de508e8c 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1076,7 +1076,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
TYPE_IMX_FEC, __func__);
break;
}
- buf_len = (size <= s->regs[ENET_MRBR]) ? size : s->regs[ENET_MRBR];
+ buf_len = MIN(size, s->regs[ENET_MRBR]);
bd.length = buf_len;
size -= buf_len;
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 06/27] imx_fec: Emulate SHIFT16 in ENETx_RACC
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (4 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 05/27] imx_fec: Use MIN instead of explicit ternary operator Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 07/27] imx_fec: Add support for multiple Tx DMA rings Andrey Smirnov
` (17 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Needed to support latest Linux kernel driver which relies on that
functionality.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 23 +++++++++++++++++++++++
include/hw/net/imx_fec.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 18de508e8c..131e7fd734 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1037,6 +1037,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
uint8_t *crc_ptr;
unsigned int buf_len;
size_t size = len;
+ bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16;
FEC_PRINTF("len %d\n", (int)size);
@@ -1051,6 +1052,10 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
crc = cpu_to_be32(crc32(~0, buf, size));
crc_ptr = (uint8_t *) &crc;
+ if (shift16) {
+ size += 2;
+ }
+
/* Huge frames are truncted. */
if (size > s->regs[ENET_FTRL]) {
size = s->regs[ENET_FTRL];
@@ -1087,6 +1092,24 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
buf_len += size - 4;
}
buf_addr = bd.data;
+
+ if (shift16) {
+ /*
+ * If SHIFT16 bit of ENETx_RACC register is set we need to
+ * align the payload to 4-byte boundary.
+ */
+ const uint8_t zeros[2] = { 0 };
+
+ dma_memory_write(&address_space_memory, buf_addr,
+ zeros, sizeof(zeros));
+
+ buf_addr += sizeof(zeros);
+ buf_len -= sizeof(zeros);
+
+ /* We only do this once per Ethernet frame */
+ shift16 = false;
+ }
+
dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
buf += buf_len;
if (size < 4) {
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index 0fcc4f0c71..e482d1c13b 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -170,6 +170,8 @@
#define ENET_TWFR_TFWR_LENGTH (6)
#define ENET_TWFR_STRFWD (1 << 8)
+#define ENET_RACC_SHIFT16 BIT(7)
+
/* Buffer Descriptor. */
typedef struct {
uint16_t length;
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 07/27] imx_fec: Add support for multiple Tx DMA rings
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (5 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 06/27] imx_fec: Emulate SHIFT16 in ENETx_RACC Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 08/27] imx_fec: Use correct length for packet size Andrey Smirnov
` (16 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
More recent version of the IP block support more than one Tx DMA ring,
so add the code implementing that feature.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 106 ++++++++++++++++++++++++++++++++++++++---------
include/hw/net/imx_fec.h | 18 +++++++-
2 files changed, 102 insertions(+), 22 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 131e7fd734..38d8c27dcd 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -198,13 +198,13 @@ static const char *imx_eth_reg_name(IMXFECState *s, uint32_t index)
static const VMStateDescription vmstate_imx_eth = {
.name = TYPE_IMX_FEC,
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
VMSTATE_UINT32(rx_descriptor, IMXFECState),
- VMSTATE_UINT32(tx_descriptor, IMXFECState),
-
+ VMSTATE_UINT32_ARRAY(tx_descriptor, IMXFECState, ENET_TX_RING_NUM),
+ VMSTATE_UINT32(tx_ring_num, IMXFECState),
VMSTATE_UINT32(phy_status, IMXFECState),
VMSTATE_UINT32(phy_control, IMXFECState),
VMSTATE_UINT32(phy_advertise, IMXFECState),
@@ -407,7 +407,7 @@ static void imx_fec_do_tx(IMXFECState *s)
int frame_size = 0, descnt = 0;
uint8_t frame[ENET_MAX_FRAME_SIZE];
uint8_t *ptr = frame;
- uint32_t addr = s->tx_descriptor;
+ uint32_t addr = s->tx_descriptor[0];
while (descnt++ < IMX_MAX_DESC) {
IMXFECBufDesc bd;
@@ -448,17 +448,47 @@ static void imx_fec_do_tx(IMXFECState *s)
}
}
- s->tx_descriptor = addr;
+ s->tx_descriptor[0] = addr;
imx_eth_update(s);
}
-static void imx_enet_do_tx(IMXFECState *s)
+static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
{
int frame_size = 0, descnt = 0;
uint8_t frame[ENET_MAX_FRAME_SIZE];
uint8_t *ptr = frame;
- uint32_t addr = s->tx_descriptor;
+ uint32_t addr, int_txb, int_txf, tdsr;
+ size_t ring;
+
+ switch (index) {
+ case ENET_TDAR:
+ ring = 0;
+ int_txb = ENET_INT_TXB;
+ int_txf = ENET_INT_TXF;
+ tdsr = ENET_TDSR;
+ break;
+ case ENET_TDAR1:
+ ring = 1;
+ int_txb = ENET_INT_TXB1;
+ int_txf = ENET_INT_TXF1;
+ tdsr = ENET_TDSR1;
+ break;
+ case ENET_TDAR2:
+ ring = 2;
+ int_txb = ENET_INT_TXB2;
+ int_txf = ENET_INT_TXF2;
+ tdsr = ENET_TDSR2;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: bogus value for index %x\n",
+ __func__, index);
+ abort();
+ break;
+ }
+
+ addr = s->tx_descriptor[ring];
while (descnt++ < IMX_MAX_DESC) {
IMXENETBufDesc bd;
@@ -502,32 +532,32 @@ static void imx_enet_do_tx(IMXFECState *s)
ptr = frame;
frame_size = 0;
if (bd.option & ENET_BD_TX_INT) {
- s->regs[ENET_EIR] |= ENET_INT_TXF;
+ s->regs[ENET_EIR] |= int_txf;
}
}
if (bd.option & ENET_BD_TX_INT) {
- s->regs[ENET_EIR] |= ENET_INT_TXB;
+ s->regs[ENET_EIR] |= int_txb;
}
bd.flags &= ~ENET_BD_R;
/* Write back the modified descriptor. */
imx_enet_write_bd(&bd, addr);
/* Advance to the next descriptor. */
if ((bd.flags & ENET_BD_W) != 0) {
- addr = s->regs[ENET_TDSR];
+ addr = s->regs[tdsr];
} else {
addr += sizeof(bd);
}
}
- s->tx_descriptor = addr;
+ s->tx_descriptor[ring] = addr;
imx_eth_update(s);
}
-static void imx_eth_do_tx(IMXFECState *s)
+static void imx_eth_do_tx(IMXFECState *s, uint32_t index)
{
if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) {
- imx_enet_do_tx(s);
+ imx_enet_do_tx(s, index);
} else {
imx_fec_do_tx(s);
}
@@ -585,7 +615,7 @@ static void imx_eth_reset(DeviceState *d)
}
s->rx_descriptor = 0;
- s->tx_descriptor = 0;
+ memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
/* We also reset the PHY */
phy_reset(s);
@@ -791,6 +821,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
IMXFECState *s = IMX_FEC(opaque);
+ const bool single_tx_ring = s->tx_ring_num != 3;
uint32_t index = offset >> 2;
FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index),
@@ -813,10 +844,18 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
s->regs[index] = 0;
}
break;
- case ENET_TDAR:
+ case ENET_TDAR1: /* FALLTHROUGH */
+ case ENET_TDAR2: /* FALLTHROUGH */
+ if (unlikely(single_tx_ring)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: trying to access TDAR2 or TDAR1\n",
+ TYPE_IMX_FEC, __func__);
+ return;
+ }
+ case ENET_TDAR: /* FALLTHROUGH */
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
s->regs[index] = ENET_TDAR_TDAR;
- imx_eth_do_tx(s);
+ imx_eth_do_tx(s, index);
}
s->regs[index] = 0;
break;
@@ -828,8 +867,12 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) {
s->regs[ENET_RDAR] = 0;
s->rx_descriptor = s->regs[ENET_RDSR];
- s->regs[ENET_TDAR] = 0;
- s->tx_descriptor = s->regs[ENET_TDSR];
+ s->regs[ENET_TDAR] = 0;
+ s->regs[ENET_TDAR1] = 0;
+ s->regs[ENET_TDAR2] = 0;
+ s->tx_descriptor[0] = s->regs[ENET_TDSR];
+ s->tx_descriptor[1] = s->regs[ENET_TDSR1];
+ s->tx_descriptor[2] = s->regs[ENET_TDSR2];
}
break;
case ENET_MMFR:
@@ -907,7 +950,29 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
} else {
s->regs[index] = value & ~7;
}
- s->tx_descriptor = s->regs[index];
+ s->tx_descriptor[0] = s->regs[index];
+ break;
+ case ENET_TDSR1:
+ if (unlikely(single_tx_ring)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: trying to access TDSR1\n",
+ TYPE_IMX_FEC, __func__);
+ return;
+ }
+
+ s->regs[index] = value & ~7;
+ s->tx_descriptor[1] = s->regs[index];
+ break;
+ case ENET_TDSR2:
+ if (unlikely(single_tx_ring)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: trying to access TDSR2\n",
+ TYPE_IMX_FEC, __func__);
+ return;
+ }
+
+ s->regs[index] = value & ~7;
+ s->tx_descriptor[2] = s->regs[index];
break;
case ENET_MRBR:
s->regs[index] = value & 0x00003ff0;
@@ -1203,6 +1268,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
static Property imx_eth_properties[] = {
DEFINE_NIC_PROPERTIES(IMXFECState, conf),
+ DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index e482d1c13b..3a438127f9 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -52,6 +52,8 @@
#define ENET_TFWR 81
#define ENET_FRBR 83
#define ENET_FRSR 84
+#define ENET_TDSR1 89
+#define ENET_TDSR2 92
#define ENET_RDSR 96
#define ENET_TDSR 97
#define ENET_MRBR 98
@@ -66,6 +68,8 @@
#define ENET_FTRL 108
#define ENET_TACC 112
#define ENET_RACC 113
+#define ENET_TDAR1 121
+#define ENET_TDAR2 123
#define ENET_MIIGSK_CFGR 192
#define ENET_MIIGSK_ENR 194
#define ENET_ATCR 256
@@ -105,13 +109,18 @@
#define ENET_INT_WAKEUP (1 << 17)
#define ENET_INT_TS_AVAIL (1 << 16)
#define ENET_INT_TS_TIMER (1 << 15)
+#define ENET_INT_TXF2 (1 << 7)
+#define ENET_INT_TXB2 (1 << 6)
+#define ENET_INT_TXF1 (1 << 3)
+#define ENET_INT_TXB1 (1 << 2)
#define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
- ENET_INT_TS_AVAIL)
+ ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
+ ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)
/* RDAR */
#define ENET_RDAR_RDAR (1 << 24)
@@ -234,6 +243,9 @@ typedef struct {
#define ENET_BD_BDU (1 << 31)
+#define ENET_TX_RING_NUM 3
+
+
typedef struct IMXFECState {
/*< private >*/
SysBusDevice parent_obj;
@@ -246,7 +258,9 @@ typedef struct IMXFECState {
uint32_t regs[ENET_MAX];
uint32_t rx_descriptor;
- uint32_t tx_descriptor;
+
+ uint32_t tx_descriptor[ENET_TX_RING_NUM];
+ uint32_t tx_ring_num;
uint32_t phy_status;
uint32_t phy_control;
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 08/27] imx_fec: Use correct length for packet size
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (6 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 07/27] imx_fec: Add support for multiple Tx DMA rings Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 09/27] imx_fec: Fix a typo in imx_enet_receive() Andrey Smirnov
` (15 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Use 'frame_size' instead of 'len' when calling qemu_send_packet(),
failing to do so results in malformed packets send in case when that
packed is fragmented into multiple DMA transactions.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 38d8c27dcd..eefb3b2c62 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -528,7 +528,7 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
}
}
/* Last buffer in frame. */
- qemu_send_packet(qemu_get_queue(s->nic), frame, len);
+ qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
ptr = frame;
frame_size = 0;
if (bd.option & ENET_BD_TX_INT) {
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 09/27] imx_fec: Fix a typo in imx_enet_receive()
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (7 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 08/27] imx_fec: Use correct length for packet size Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 10/27] imx_fec: Reserve full 4K page for the register file Andrey Smirnov
` (14 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index eefb3b2c62..48d012cad6 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1121,7 +1121,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
size += 2;
}
- /* Huge frames are truncted. */
+ /* Huge frames are truncated. */
if (size > s->regs[ENET_FTRL]) {
size = s->regs[ENET_FTRL];
flags |= ENET_BD_TR | ENET_BD_LG;
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 10/27] imx_fec: Reserve full 4K page for the register file
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (8 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 09/27] imx_fec: Fix a typo in imx_enet_receive() Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 11/27] sdhci: Add i.MX specific subtype of SDHCI Andrey Smirnov
` (13 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Some i.MX SoCs (e.g. i.MX7) have FEC registers going as far as offset
0x614, so to avoid getting aborts when accessing those on QEMU, extend
the register file to cover 4KB of address space instead of just 1K.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/net/imx_fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 48d012cad6..e236bc933c 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -1252,7 +1252,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_eth_ops, s,
- TYPE_IMX_FEC, 0x400);
+ TYPE_IMX_FEC, 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq[0]);
sysbus_init_irq(sbd, &s->irq[1]);
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 11/27] sdhci: Add i.MX specific subtype of SDHCI
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (9 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 10/27] imx_fec: Reserve full 4K page for the register file Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 12/27] sdhci: Implement write method of ACMD12ERRSTS register Andrey Smirnov
` (12 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
IP block found on several generations of i.MX family does not use
vanilla SDHCI implementation and it comes with a number of quirks.
Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to
support unmodified Linux guest driver.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/sd/sdhci-internal.h | 15 ++++++
hw/sd/sdhci.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++++-
include/hw/sd/sdhci.h | 8 ++++
3 files changed, 148 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 161177cf39..2a1b4b06ee 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -91,6 +91,8 @@
#define SDHC_CTRL_ADMA2_32 0x10
#define SDHC_CTRL_ADMA2_64 0x18
#define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK)
+#define SDHC_CTRL_4BITBUS 0x02
+#define SDHC_CTRL_8BITBUS 0x20
/* R/W Power Control Register 0x0 */
#define SDHC_PWRCON 0x29
@@ -229,4 +231,17 @@ enum {
extern const VMStateDescription sdhci_vmstate;
+
+#define ESDHC_MIX_CTRL 0x48
+#define ESDHC_VENDOR_SPEC 0xc0
+#define ESDHC_DLL_CTRL 0x60
+
+#define ESDHC_TUNING_CTRL 0xcc
+#define ESDHC_TUNE_CTRL_STATUS 0x68
+#define ESDHC_WTMK_LVL 0x44
+
+#define ESDHC_CTRL_4BITBUS (0x1 << 1)
+#define ESDHC_CTRL_8BITBUS (0x2 << 1)
+
+
#endif
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6d6a791ee9..f561cc44e3 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -265,7 +265,8 @@ static void sdhci_send_command(SDHCIState *s)
}
}
- if ((s->norintstsen & SDHC_NISEN_TRSCMP) &&
+ if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
+ (s->norintstsen & SDHC_NISEN_TRSCMP) &&
(s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
s->norintsts |= SDHC_NIS_TRSCMP;
}
@@ -1191,6 +1192,8 @@ static void sdhci_initfn(SDHCIState *s)
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
+
+ s->io_ops = &sdhci_mmio_ops;
}
static void sdhci_uninitfn(SDHCIState *s)
@@ -1347,7 +1350,7 @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
s->buf_maxsz = sdhci_get_fifolen(s);
s->fifo_buffer = g_malloc0(s->buf_maxsz);
sysbus_init_irq(sbd, &s->irq);
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
+ memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
SDHC_REGISTERS_MAP_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
}
@@ -1386,11 +1389,131 @@ static const TypeInfo sdhci_bus_info = {
.class_init = sdhci_bus_class_init,
};
+static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
+{
+ SDHCIState *s = SYSBUS_SDHCI(opaque);
+ uint32_t ret;
+ uint16_t hostctl;
+
+ switch (offset) {
+ default:
+ return sdhci_read(opaque, offset, size);
+
+ case SDHC_HOSTCTL:
+ hostctl = SDHC_DMA_TYPE(s->hostctl) << 5;
+
+ if (s->hostctl & SDHC_CTRL_8BITBUS) {
+ hostctl |= ESDHC_CTRL_8BITBUS;
+ }
+
+ if (s->hostctl & SDHC_CTRL_4BITBUS) {
+ hostctl |= ESDHC_CTRL_4BITBUS;
+ }
+
+ ret = hostctl | (s->blkgap << 16) |
+ (s->wakcon << 24);
+
+ break;
+
+ case ESDHC_DLL_CTRL:
+ case ESDHC_TUNE_CTRL_STATUS:
+ case 0x6c:
+ case ESDHC_TUNING_CTRL:
+ case ESDHC_VENDOR_SPEC:
+ case ESDHC_MIX_CTRL:
+ case ESDHC_WTMK_LVL:
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static void
+usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
+{
+ SDHCIState *s = SYSBUS_SDHCI(opaque);
+ uint8_t hostctl = 0;
+ uint32_t value = (uint32_t)val;
+
+ switch (offset) {
+ case ESDHC_DLL_CTRL:
+ case ESDHC_TUNE_CTRL_STATUS:
+ case 0x6c:
+ case ESDHC_TUNING_CTRL:
+ case ESDHC_WTMK_LVL:
+ case ESDHC_VENDOR_SPEC:
+ break;
+
+ case SDHC_HOSTCTL:
+ if (value & ESDHC_CTRL_8BITBUS) {
+ hostctl |= SDHC_CTRL_8BITBUS;
+ }
+
+ if (value & ESDHC_CTRL_4BITBUS) {
+ hostctl |= ESDHC_CTRL_4BITBUS;
+ }
+
+ hostctl |= SDHC_DMA_TYPE(value >> 5);
+
+ value &= ~0xFE;
+ value |= hostctl;
+ value &= ~0xFF00;
+ value |= s->pwrcon;
+
+ sdhci_write(opaque, offset, value, size);
+ break;
+
+ case ESDHC_MIX_CTRL:
+ /*
+ * The layout of the register is slightly different, but we
+ * don't care about those bits
+ */
+ s->trnmod = value & 0xFFFF;
+ break;
+ case SDHC_TRNMOD:
+ sdhci_write(opaque, offset, val | s->trnmod, size);
+ break;
+ case SDHC_BLKSIZE:
+ val |= 0x7 << 12;
+ default: /* FALLTHROUGH */
+ sdhci_write(opaque, offset, val, size);
+ break;
+ }
+}
+
+
+static const MemoryRegionOps usdhc_mmio_ops = {
+ .read = usdhc_read,
+ .write = usdhc_write,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ .unaligned = false
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void imx_usdhc_init(Object *obj)
+{
+ SDHCIState *s = SYSBUS_SDHCI(obj);
+
+ s->io_ops = &usdhc_mmio_ops;
+ s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
+}
+
+static const TypeInfo imx_usdhc_info = {
+ .name = TYPE_IMX_USDHC,
+ .parent = TYPE_SYSBUS_SDHCI,
+ .instance_init = imx_usdhc_init,
+};
+
static void sdhci_register_types(void)
{
type_register_static(&sdhci_pci_info);
type_register_static(&sdhci_sysbus_info);
type_register_static(&sdhci_bus_info);
+ type_register_static(&imx_usdhc_info);
}
type_init(sdhci_register_types)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 0f0c3f1e64..dc1856a33d 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -39,6 +39,7 @@ typedef struct SDHCIState {
};
SDBus sdbus;
MemoryRegion iomem;
+ const MemoryRegionOps *io_ops;
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
QEMUTimer *transfer_timer;
@@ -83,8 +84,13 @@ typedef struct SDHCIState {
/* Force Event Auto CMD12 Error Interrupt Reg - write only */
/* Force Event Error Interrupt Register- write only */
/* RO Host Controller Version Register always reads as 0x2401 */
+
+ unsigned long quirks;
} SDHCIState;
+/* Controller does not provide transfer-complete interrupt when not busy */
+#define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14)
+
#define TYPE_PCI_SDHCI "sdhci-pci"
#define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI)
@@ -92,4 +98,6 @@ typedef struct SDHCIState {
#define SYSBUS_SDHCI(obj) \
OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI)
+#define TYPE_IMX_USDHC "imx-usdhc"
+
#endif /* SDHCI_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 12/27] sdhci: Implement write method of ACMD12ERRSTS register
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (10 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 11/27] sdhci: Add i.MX specific subtype of SDHCI Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 13/27] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks Andrey Smirnov
` (11 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/sd/sdhci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index f561cc44e3..53e5e011a7 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1139,6 +1139,9 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
((uint64_t)mask << 32))) | ((uint64_t)value << 32);
break;
+ case SDHC_ACMD12ERRSTS:
+ MASKED_WRITE(s->acmd12errsts, mask, value);
+ break;
case SDHC_FEAER:
s->acmd12errsts |= value;
s->errintsts |= (value >> 16) & s->errintstsen;
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 13/27] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (11 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 12/27] sdhci: Implement write method of ACMD12ERRSTS register Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 14/27] i.MX: Add code to emulate i.MX2 watchdog IP block Andrey Smirnov
` (10 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx7_ccm.c | 233 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx7_ccm.h | 130 +++++++++++++++++++++++++
3 files changed, 364 insertions(+)
create mode 100644 hw/misc/imx7_ccm.c
create mode 100644 include/hw/misc/imx7_ccm.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 29fb922cef..ac1be05a03 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -34,6 +34,7 @@ obj-$(CONFIG_IMX) += imx31_ccm.o
obj-$(CONFIG_IMX) += imx25_ccm.o
obj-$(CONFIG_IMX) += imx6_ccm.o
obj-$(CONFIG_IMX) += imx6_src.o
+obj-$(CONFIG_IMX) += imx7_ccm.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c
new file mode 100644
index 0000000000..2876164cfa
--- /dev/null
+++ b/hw/misc/imx7_ccm.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 CCM, PMU and ANALOG IP blocks emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+
+#include "hw/misc/imx7_ccm.h"
+
+static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
+{
+ /*
+ * This function is "consumed" by GPT emulation code, however on
+ * i.MX7 each GPT block can have their own clock root. This means
+ * that this functions needs somehow to know requester's identity
+ * and the way to pass it: be it via additional IMXClk constants
+ * or by adding another argument to this method needs to be
+ * figured out
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n",
+ TYPE_IMX7_CCM, __func__);
+ return 0;
+}
+
+static void imx7_ccm_reset(DeviceState *dev)
+{
+ IMX7CCMState *s = IMX7_CCM(dev);
+
+ s->analog[CCM_ANALOG_PLL_ARM] = 0x00002042;
+ s->analog[CCM_ANALOG_PLL_DDR] = 0x0060302c;
+ s->analog[CCM_ANALOG_PLL_DDR_SS] = 0x00000000;
+ s->analog[CCM_ANALOG_PLL_DDR_NUM] = 0x06aaac4d;
+ s->analog[CCM_ANALOG_PLL_DDR_DENOM] = 0x100003ec;
+ s->analog[CCM_ANALOG_PLL_480] = 0x00002000;
+ s->analog[CCM_ANALOG_PLL_480A] = 0x52605a56;
+ s->analog[CCM_ANALOG_PLL_480B] = 0x52525216;
+ s->analog[CCM_ANALOG_PLL_ENET] = 0x00001fc0;
+ s->analog[CCM_ANALOG_PLL_AUDIO] = 0x0001301b;
+ s->analog[CCM_ANALOG_PLL_AUDIO_SS] = 0x00000000;
+ s->analog[CCM_ANALOG_PLL_AUDIO_NUM] = 0x05f5e100;
+ s->analog[CCM_ANALOG_PLL_AUDIO_DENOM] = 0x2964619c;
+ s->analog[CCM_ANALOG_PLL_VIDEO] = 0x0008201b;
+ s->analog[CCM_ANALOG_PLL_VIDEO_SS] = 0x00000000;
+ s->analog[CCM_ANALOG_PLL_VIDEO_NUM] = 0x0000f699;
+ s->analog[CCM_ANALOG_PLL_VIDEO_DENOM] = 0x000f4240;
+ s->analog[CCM_ANALOG_PLL_MISC0] = 0x00000000;
+
+ /* all PLLs need to be locked */
+ s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_DDR] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_480] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_480A] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_480B] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_ENET] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_AUDIO] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_VIDEO] |= CCM_ANALOG_PLL_LOCK;
+ s->analog[CCM_ANALOG_PLL_MISC0] |= CCM_ANALOG_PLL_LOCK;
+
+ /*
+ * Since I couldn't find any info about this in the reference
+ * manual the value of this register is based strictly on matching
+ * what Linux kernel expects it to be.
+ */
+ s->analog[CCM_ANALOG_DIGPROG] = 0x720000;
+ /*
+ * Set revision to be 1.0 (Arbitrary choice, no particular
+ * reason).
+ */
+ s->analog[CCM_ANALOG_DIGPROG] |= 0x000010;
+}
+
+#define CCM_INDEX(offset) (((offset) & ~(hwaddr)0xF) / sizeof(uint32_t))
+#define CCM_BITOP(offset) ((offset) & (hwaddr)0xF)
+
+enum {
+ CCM_BITOP_NONE = 0x00,
+ CCM_BITOP_SET = 0x04,
+ CCM_BITOP_CLR = 0x08,
+ CCM_BITOP_TOG = 0x0C,
+};
+
+static uint64_t imx7_set_clr_tog_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const uint32_t *mmio = opaque;
+
+ return mmio[CCM_INDEX(offset)];
+}
+
+static void imx7_set_clr_tog_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ const uint8_t bitop = CCM_BITOP(offset);
+ const uint32_t index = CCM_INDEX(offset);
+ uint32_t *mmio = opaque;
+
+ switch (bitop) {
+ case CCM_BITOP_NONE:
+ mmio[index] = value;
+ break;
+ case CCM_BITOP_SET:
+ mmio[index] |= value;
+ break;
+ case CCM_BITOP_CLR:
+ mmio[index] &= ~value;
+ break;
+ case CCM_BITOP_TOG:
+ mmio[index] ^= value;
+ break;
+ };
+}
+
+static const struct MemoryRegionOps imx7_set_clr_tog_ops = {
+ .read = imx7_set_clr_tog_read,
+ .write = imx7_set_clr_tog_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static const struct MemoryRegionOps imx7_digprog_ops = {
+ .read = imx7_set_clr_tog_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx7_ccm_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMX7CCMState *s = IMX7_CCM(obj);
+
+ memory_region_init(&s->mmio.container, obj, TYPE_IMX7_CCM,
+ 0x30000);
+
+ memory_region_init_io(&s->mmio.analog,
+ obj,
+ &imx7_set_clr_tog_ops,
+ s->analog,
+ TYPE_IMX7_CCM ".analog",
+ sizeof(s->analog));
+
+ memory_region_add_subregion(&s->mmio.container,
+ 0x60, &s->mmio.analog);
+
+ memory_region_init_io(&s->mmio.digprog,
+ obj,
+ &imx7_digprog_ops,
+ &s->analog[CCM_ANALOG_DIGPROG],
+ TYPE_IMX7_CCM ".digprog",
+ sizeof(uint32_t));
+
+ memory_region_add_subregion_overlap(&s->mmio.container,
+ 0x800, &s->mmio.digprog, 10);
+
+ memory_region_init_io(&s->mmio.pmu,
+ obj,
+ &imx7_set_clr_tog_ops,
+ s->pmu,
+ TYPE_IMX7_CCM ".pmu",
+ sizeof(s->pmu));
+
+ memory_region_add_subregion(&s->mmio.container,
+ 0x200, &s->mmio.pmu);
+
+ memory_region_init_io(&s->mmio.ccm,
+ obj,
+ &imx7_set_clr_tog_ops,
+ s->ccm,
+ TYPE_IMX7_CCM ".ccm",
+ sizeof(s->ccm));
+
+ memory_region_add_subregion(&s->mmio.container,
+ 0x20000, &s->mmio.ccm);
+
+ sysbus_init_mmio(sd, &s->mmio.container);
+}
+
+static const VMStateDescription vmstate_imx7_ccm = {
+ .name = TYPE_IMX7_CCM,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(ccm, IMX7CCMState, CCM_MAX),
+ VMSTATE_UINT32_ARRAY(analog, IMX7CCMState, CCM_ANALOG_MAX),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx7_ccm_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
+
+ dc->reset = imx7_ccm_reset;
+ dc->vmsd = &vmstate_imx7_ccm;
+ dc->desc = "i.MX7 Clock Control Module";
+
+ ccm->get_clock_frequency = imx7_ccm_get_clock_frequency;
+}
+
+static const TypeInfo imx7_ccm_info = {
+ .name = TYPE_IMX7_CCM,
+ .parent = TYPE_IMX_CCM,
+ .instance_size = sizeof(IMX7CCMState),
+ .instance_init = imx7_ccm_init,
+ .class_init = imx7_ccm_class_init,
+};
+
+static void imx7_ccm_register_type(void)
+{
+ type_register_static(&imx7_ccm_info);
+}
+type_init(imx7_ccm_register_type)
diff --git a/include/hw/misc/imx7_ccm.h b/include/hw/misc/imx7_ccm.h
new file mode 100644
index 0000000000..0cd6750343
--- /dev/null
+++ b/include/hw/misc/imx7_ccm.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 CCM, PMU and ANALOG IP blocks emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX7_CCM_H
+#define IMX7_CCM_H
+
+#include "hw/misc/imx_ccm.h"
+#include "qemu/bitops.h"
+
+enum IMX7AnalogRegisters {
+ CCM_ANALOG_PLL_ARM,
+ CCM_ANALOG_PLL_ARM_SET,
+ CCM_ANALOG_PLL_ARM_CLR,
+ CCM_ANALOG_PLL_ARM_TOG,
+ CCM_ANALOG_PLL_DDR,
+ CCM_ANALOG_PLL_DDR_SET,
+ CCM_ANALOG_PLL_DDR_CLR,
+ CCM_ANALOG_PLL_DDR_TOG,
+ CCM_ANALOG_PLL_DDR_SS,
+ CCM_ANALOG_PLL_DDR_SS_SET,
+ CCM_ANALOG_PLL_DDR_SS_CLR,
+ CCM_ANALOG_PLL_DDR_SS_TOG,
+ CCM_ANALOG_PLL_DDR_NUM,
+ CCM_ANALOG_PLL_DDR_NUM_SET,
+ CCM_ANALOG_PLL_DDR_NUM_CLR,
+ CCM_ANALOG_PLL_DDR_NUM_TOG,
+ CCM_ANALOG_PLL_DDR_DENOM,
+ CCM_ANALOG_PLL_DDR_DENOM_SET,
+ CCM_ANALOG_PLL_DDR_DENOM_CLR,
+ CCM_ANALOG_PLL_DDR_DENOM_TOG,
+ CCM_ANALOG_PLL_480,
+ CCM_ANALOG_PLL_480_SET,
+ CCM_ANALOG_PLL_480_CLR,
+ CCM_ANALOG_PLL_480_TOG,
+ CCM_ANALOG_PLL_480A,
+ CCM_ANALOG_PLL_480A_SET,
+ CCM_ANALOG_PLL_480A_CLR,
+ CCM_ANALOG_PLL_480A_TOG,
+ CCM_ANALOG_PLL_480B,
+ CCM_ANALOG_PLL_480B_SET,
+ CCM_ANALOG_PLL_480B_CLR,
+ CCM_ANALOG_PLL_480B_TOG,
+ CCM_ANALOG_PLL_ENET,
+ CCM_ANALOG_PLL_ENET_SET,
+ CCM_ANALOG_PLL_ENET_CLR,
+ CCM_ANALOG_PLL_ENET_TOG,
+ CCM_ANALOG_PLL_AUDIO,
+ CCM_ANALOG_PLL_AUDIO_SET,
+ CCM_ANALOG_PLL_AUDIO_CLR,
+ CCM_ANALOG_PLL_AUDIO_TOG,
+ CCM_ANALOG_PLL_AUDIO_SS,
+ CCM_ANALOG_PLL_AUDIO_SS_SET,
+ CCM_ANALOG_PLL_AUDIO_SS_CLR,
+ CCM_ANALOG_PLL_AUDIO_SS_TOG,
+ CCM_ANALOG_PLL_AUDIO_NUM,
+ CCM_ANALOG_PLL_AUDIO_NUM_SET,
+ CCM_ANALOG_PLL_AUDIO_NUM_CLR,
+ CCM_ANALOG_PLL_AUDIO_NUM_TOG,
+ CCM_ANALOG_PLL_AUDIO_DENOM,
+ CCM_ANALOG_PLL_AUDIO_DENOM_SET,
+ CCM_ANALOG_PLL_AUDIO_DENOM_CLR,
+ CCM_ANALOG_PLL_AUDIO_DENOM_TOG,
+ CCM_ANALOG_PLL_VIDEO,
+ CCM_ANALOG_PLL_VIDEO_SET,
+ CCM_ANALOG_PLL_VIDEO_CLR,
+ CCM_ANALOG_PLL_VIDEO_TOG,
+ CCM_ANALOG_PLL_VIDEO_SS,
+ CCM_ANALOG_PLL_VIDEO_SS_SET,
+ CCM_ANALOG_PLL_VIDEO_SS_CLR,
+ CCM_ANALOG_PLL_VIDEO_SS_TOG,
+ CCM_ANALOG_PLL_VIDEO_NUM,
+ CCM_ANALOG_PLL_VIDEO_NUM_SET,
+ CCM_ANALOG_PLL_VIDEO_NUM_CLR,
+ CCM_ANALOG_PLL_VIDEO_NUM_TOG,
+ CCM_ANALOG_PLL_VIDEO_DENOM,
+ CCM_ANALOG_PLL_VIDEO_DENOM_SET,
+ CCM_ANALOG_PLL_VIDEO_DENOM_CLR,
+ CCM_ANALOG_PLL_VIDEO_DENOM_TOG,
+ CCM_ANALOG_PLL_MISC0,
+ CCM_ANALOG_PLL_MISC0_SET,
+ CCM_ANALOG_PLL_MISC0_CLR,
+ CCM_ANALOG_PLL_MISC0_TOG,
+
+ CCM_ANALOG_DIGPROG = 0x800 / sizeof(uint32_t),
+ CCM_ANALOG_MAX,
+
+ CCM_ANALOG_PLL_LOCK = BIT(31)
+};
+
+enum IMX7CCMRegisters {
+ CCM_MAX = 0xBE00 / sizeof(uint32_t) + 1,
+};
+
+enum IMX7PMURegisters {
+ PMU_MAX = 0x140 / sizeof(uint32_t),
+};
+
+#undef REG_SET_CLR_TOG
+
+#define TYPE_IMX7_CCM "imx7.ccm"
+#define IMX7_CCM(obj) OBJECT_CHECK(IMX7CCMState, (obj), TYPE_IMX7_CCM)
+
+typedef struct IMX7CCMState {
+ /* <private> */
+ IMXCCMState parent_obj;
+
+ /* <public> */
+ struct {
+ MemoryRegion container;
+ MemoryRegion ccm;
+ MemoryRegion pmu;
+ MemoryRegion analog;
+ MemoryRegion digprog;
+ } mmio;
+
+ uint32_t ccm[CCM_MAX];
+ uint32_t pmu[PMU_MAX];
+ uint32_t analog[CCM_ANALOG_MAX];
+
+} IMX7CCMState;
+
+#endif /* IMX7_CCM_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 14/27] i.MX: Add code to emulate i.MX2 watchdog IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (12 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 13/27] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 15/27] i.MX: Add code to emulate i.MX7 SNVS IP-block Andrey Smirnov
` (9 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add enough code to emulate i.MX2 watchdog IP block so it would be
possible to reboot the machine running Linux Guest.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx2_wdt.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx2_wdt.h | 34 ++++++++++++++++++
3 files changed, 123 insertions(+)
create mode 100644 hw/misc/imx2_wdt.c
create mode 100644 include/hw/misc/imx2_wdt.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ac1be05a03..c393a93456 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -35,6 +35,7 @@ obj-$(CONFIG_IMX) += imx25_ccm.o
obj-$(CONFIG_IMX) += imx6_ccm.o
obj-$(CONFIG_IMX) += imx6_src.o
obj-$(CONFIG_IMX) += imx7_ccm.o
+obj-$(CONFIG_IMX) += imx2_wdt.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/hw/misc/imx2_wdt.c b/hw/misc/imx2_wdt.c
new file mode 100644
index 0000000000..3a1c33aa51
--- /dev/null
+++ b/hw/misc/imx2_wdt.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX2 Watchdog IP block
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/watchdog.h"
+
+#include "hw/misc/imx2_wdt.h"
+
+#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
+#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
+
+static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ return 0;
+}
+
+static void imx2_wdt_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned int size)
+{
+ if (addr == IMX2_WDT_WCR &&
+ (value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
+ watchdog_perform_action();
+ }
+}
+
+static const MemoryRegionOps imx2_wdt_ops = {
+ .read = imx2_wdt_read,
+ .write = imx2_wdt_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the
+ * real device but in practice there is no reason for a guest
+ * to access this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx2_wdt_realize(DeviceState *dev, Error **errp)
+{
+ IMX2WdtState *s = IMX2_WDT(dev);
+
+ memory_region_init_io(&s->mmio, OBJECT(dev),
+ &imx2_wdt_ops, s,
+ TYPE_IMX2_WDT".mmio",
+ IMX2_WDT_REG_NUM * sizeof(uint16_t));
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+}
+
+static void imx2_wdt_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = imx2_wdt_realize;
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static const TypeInfo imx2_wdt_info = {
+ .name = TYPE_IMX2_WDT,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMX2WdtState),
+ .class_init = imx2_wdt_class_init,
+};
+
+static WatchdogTimerModel model = {
+ .wdt_name = "imx2-watchdog",
+ .wdt_description = "i.MX2 Watchdog",
+};
+
+static void imx2_wdt_register_type(void)
+{
+ watchdog_add_model(&model);
+ type_register_static(&imx2_wdt_info);
+}
+type_init(imx2_wdt_register_type)
diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/misc/imx2_wdt.h
new file mode 100644
index 0000000000..e67ac6939d
--- /dev/null
+++ b/include/hw/misc/imx2_wdt.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX2 Watchdog IP block
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX2_WDT_H
+#define IMX2_WDT_H
+
+#include "qemu/bitops.h"
+#include "hw/sysbus.h"
+
+#define TYPE_IMX2_WDT "imx2.wdt"
+#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
+
+enum IMX2WdtRegisters {
+ IMX2_WDT_WCR = 0x0000,
+ IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1,
+};
+
+
+typedef struct IMX2WdtState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+} IMX2WdtState;
+
+#endif /* IMX7_SNVS_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 15/27] i.MX: Add code to emulate i.MX7 SNVS IP-block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (13 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 14/27] i.MX: Add code to emulate i.MX2 watchdog IP block Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 16/27] i.MX: Add code to emulate GPCv2 IP block Andrey Smirnov
` (8 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add code to emulate SNVS IP-block. Currently only the bits needed to
be able to emulate machine shutdown are implemented.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx7_snvs.c | 83 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx7_snvs.h | 35 +++++++++++++++++++
3 files changed, 119 insertions(+)
create mode 100644 hw/misc/imx7_snvs.c
create mode 100644 include/hw/misc/imx7_snvs.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c393a93456..16cee88e0f 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -36,6 +36,7 @@ obj-$(CONFIG_IMX) += imx6_ccm.o
obj-$(CONFIG_IMX) += imx6_src.o
obj-$(CONFIG_IMX) += imx7_ccm.o
obj-$(CONFIG_IMX) += imx2_wdt.o
+obj-$(CONFIG_IMX) += imx7_snvs.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c
new file mode 100644
index 0000000000..670b9f4639
--- /dev/null
+++ b/hw/misc/imx7_snvs.c
@@ -0,0 +1,83 @@
+/*
+ * IMX7 Secure Non-Volatile Storage
+ *
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * Bare minimum emulation code needed to support being able to shut
+ * down linux guest gracefully.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/imx7_snvs.h"
+#include "qemu/log.h"
+#include "sysemu/sysemu.h"
+
+static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size)
+{
+ return 0;
+}
+
+static void imx7_snvs_write(void *opaque, hwaddr offset,
+ uint64_t v, unsigned size)
+{
+ const uint32_t value = v;
+ const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN;
+
+ if (offset == SNVS_LPCR && ((value & mask) == mask)) {
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ }
+}
+
+static const struct MemoryRegionOps imx7_snvs_ops = {
+ .read = imx7_snvs_read,
+ .write = imx7_snvs_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx7_snvs_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMX7SNVSState *s = IMX7_SNVS(obj);
+
+ memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s,
+ TYPE_IMX7_SNVS, 0x1000);
+
+ sysbus_init_mmio(sd, &s->mmio);
+}
+
+static void imx7_snvs_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "i.MX7 Secure Non-Volatile Storage Module";
+}
+
+static const TypeInfo imx7_snvs_info = {
+ .name = TYPE_IMX7_SNVS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMX7SNVSState),
+ .instance_init = imx7_snvs_init,
+ .class_init = imx7_snvs_class_init,
+};
+
+static void imx7_snvs_register_type(void)
+{
+ type_register_static(&imx7_snvs_info);
+}
+type_init(imx7_snvs_register_type)
diff --git a/include/hw/misc/imx7_snvs.h b/include/hw/misc/imx7_snvs.h
new file mode 100644
index 0000000000..255f8f26f9
--- /dev/null
+++ b/include/hw/misc/imx7_snvs.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 SNVS block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX7_SNVS_H
+#define IMX7_SNVS_H
+
+#include "qemu/bitops.h"
+#include "hw/sysbus.h"
+
+
+enum IMX7SNVSRegisters {
+ SNVS_LPCR = 0x38,
+ SNVS_LPCR_TOP = BIT(6),
+ SNVS_LPCR_DP_EN = BIT(5)
+};
+
+#define TYPE_IMX7_SNVS "imx7.snvs"
+#define IMX7_SNVS(obj) OBJECT_CHECK(IMX7SNVSState, (obj), TYPE_IMX7_SNVS)
+
+typedef struct IMX7SNVSState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+} IMX7SNVSState;
+
+#endif /* IMX7_SNVS_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 16/27] i.MX: Add code to emulate GPCv2 IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (14 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 15/27] i.MX: Add code to emulate i.MX7 SNVS IP-block Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 17/27] i.MX: Add code to emulate i.MX7 IOMUXC " Andrey Smirnov
` (7 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/intc/Makefile.objs | 2 +-
hw/intc/imx_gpcv2.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
include/hw/intc/imx_gpcv2.h | 22 ++++++++
3 files changed, 148 insertions(+), 1 deletion(-)
create mode 100644 hw/intc/imx_gpcv2.c
create mode 100644 include/hw/intc/imx_gpcv2.h
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 78426a7daf..db234901aa 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -4,7 +4,7 @@ common-obj-$(CONFIG_PL190) += pl190.o
common-obj-$(CONFIG_PUV3) += puv3_intc.o
common-obj-$(CONFIG_XILINX) += xilinx_intc.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
-common-obj-$(CONFIG_IMX) += imx_avic.o
+common-obj-$(CONFIG_IMX) += imx_avic.o imx_gpcv2.o
common-obj-$(CONFIG_LM32) += lm32_pic.o
common-obj-$(CONFIG_REALVIEW) += realview_gic.o
common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c
new file mode 100644
index 0000000000..496ed31b78
--- /dev/null
+++ b/hw/intc/imx_gpcv2.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 GPCv2 block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/intc/imx_gpcv2.h"
+#include "qemu/log.h"
+
+#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
+#define GPC_PU_PGC_SW_PDN_REQ 0x104
+
+#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
+#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
+#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
+#define PCIE_PHY_SW_Pxx_REQ BIT(1)
+#define MIPI_PHY_SW_Pxx_REQ BIT(0)
+
+
+static void imx_gpcv2_reset(DeviceState *dev)
+{
+ IMXGPCv2State *s = IMX_GPCV2(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static uint64_t imx_gpcv2_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ IMXGPCv2State *s = opaque;
+
+ return s->regs[offset / sizeof(uint32_t)];
+}
+
+static void imx_gpcv2_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMXGPCv2State *s = opaque;
+ const size_t idx = offset / sizeof(uint32_t);
+
+ s->regs[idx] = value;
+
+ /*
+ * Real HW will clear those bits once as a way to indicate that
+ * power up request is complete
+ */
+ if (offset == GPC_PU_PGC_SW_PUP_REQ ||
+ offset == GPC_PU_PGC_SW_PDN_REQ) {
+ s->regs[idx] &= ~(USB_HSIC_PHY_SW_Pxx_REQ |
+ USB_OTG2_PHY_SW_Pxx_REQ |
+ USB_OTG1_PHY_SW_Pxx_REQ |
+ PCIE_PHY_SW_Pxx_REQ |
+ MIPI_PHY_SW_Pxx_REQ);
+ }
+}
+
+static const struct MemoryRegionOps imx_gpcv2_ops = {
+ .read = imx_gpcv2_read,
+ .write = imx_gpcv2_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx_gpcv2_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMXGPCv2State *s = IMX_GPCV2(obj);
+
+ memory_region_init_io(&s->iomem,
+ obj,
+ &imx_gpcv2_ops,
+ s,
+ TYPE_IMX_GPCV2 ".iomem",
+ sizeof(s->regs));
+ sysbus_init_mmio(sd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_imx_gpcv2 = {
+ .name = TYPE_IMX_GPCV2,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IMXGPCv2State, GPC_NUM),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx_gpcv2_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx_gpcv2_reset;
+ dc->vmsd = &vmstate_imx_gpcv2;
+ dc->desc = "i.MX GPCv2 Module";
+}
+
+static const TypeInfo imx_gpcv2_info = {
+ .name = TYPE_IMX_GPCV2,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXGPCv2State),
+ .instance_init = imx_gpcv2_init,
+ .class_init = imx_gpcv2_class_init,
+};
+
+static void imx_gpcv2_register_type(void)
+{
+ type_register_static(&imx_gpcv2_info);
+}
+type_init(imx_gpcv2_register_type)
diff --git a/include/hw/intc/imx_gpcv2.h b/include/hw/intc/imx_gpcv2.h
new file mode 100644
index 0000000000..ed978b24bb
--- /dev/null
+++ b/include/hw/intc/imx_gpcv2.h
@@ -0,0 +1,22 @@
+#ifndef IMX_GPCV2_H
+#define IMX_GPCV2_H
+
+#include "hw/sysbus.h"
+
+enum IMXGPCv2Registers {
+ GPC_NUM = 0xE00 / sizeof(uint32_t),
+};
+
+typedef struct IMXGPCv2State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[GPC_NUM];
+} IMXGPCv2State;
+
+#define TYPE_IMX_GPCV2 "imx-gpcv2"
+#define IMX_GPCV2(obj) OBJECT_CHECK(IMXGPCv2State, (obj), TYPE_IMX_GPCV2)
+
+#endif /* IMX_GPCV2_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 17/27] i.MX: Add code to emulate i.MX7 IOMUXC IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (15 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 16/27] i.MX: Add code to emulate GPCv2 IP block Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 19/27] i.MX: Add code to emulate SDMA " Andrey Smirnov
` (6 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx7_iomuxc.c | 99 +++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx7_iomuxc.h | 22 ++++++++++
3 files changed, 122 insertions(+)
create mode 100644 hw/misc/imx7_iomuxc.c
create mode 100644 include/hw/misc/imx7_iomuxc.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 16cee88e0f..492c535330 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -37,6 +37,7 @@ obj-$(CONFIG_IMX) += imx6_src.o
obj-$(CONFIG_IMX) += imx7_ccm.o
obj-$(CONFIG_IMX) += imx2_wdt.o
obj-$(CONFIG_IMX) += imx7_snvs.o
+obj-$(CONFIG_IMX) += imx7_iomuxc.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/hw/misc/imx7_iomuxc.c b/hw/misc/imx7_iomuxc.c
new file mode 100644
index 0000000000..aa26a7485f
--- /dev/null
+++ b/hw/misc/imx7_iomuxc.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 IOMUXC block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/imx7_iomuxc.h"
+#include "qemu/log.h"
+
+static void imx7_iomuxc_reset(DeviceState *dev)
+{
+ IMX7IOMUXCState *s = IMX7_IOMUXC(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static uint64_t imx7_iomuxc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ IMX7IOMUXCState *s = opaque;
+ return s->regs[offset / sizeof(uint32_t)];
+}
+
+static void imx7_iomuxc_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMX7IOMUXCState *s = opaque;
+ s->regs[offset / sizeof(uint32_t)] = value;
+}
+
+static const struct MemoryRegionOps imx7_iomuxc_ops = {
+ .read = imx7_iomuxc_read,
+ .write = imx7_iomuxc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx7_iomuxc_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMX7IOMUXCState *s = IMX7_IOMUXC(obj);
+
+ memory_region_init_io(&s->iomem,
+ obj,
+ &imx7_iomuxc_ops,
+ s,
+ TYPE_IMX7_IOMUXC ".iomem",
+ sizeof(s->regs));
+ sysbus_init_mmio(sd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_imx7_iomuxc = {
+ .name = TYPE_IMX7_IOMUXC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IMX7IOMUXCState, IOMUXC_NUM),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx7_iomuxc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx7_iomuxc_reset;
+ dc->vmsd = &vmstate_imx7_iomuxc;
+ dc->desc = "i.MX IOMUXC Module";
+}
+
+static const TypeInfo imx7_iomuxc_info = {
+ .name = TYPE_IMX7_IOMUXC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMX7IOMUXCState),
+ .instance_init = imx7_iomuxc_init,
+ .class_init = imx7_iomuxc_class_init,
+};
+
+static void imx7_iomuxc_register_type(void)
+{
+ type_register_static(&imx7_iomuxc_info);
+}
+type_init(imx7_iomuxc_register_type)
diff --git a/include/hw/misc/imx7_iomuxc.h b/include/hw/misc/imx7_iomuxc.h
new file mode 100644
index 0000000000..7041a1ff42
--- /dev/null
+++ b/include/hw/misc/imx7_iomuxc.h
@@ -0,0 +1,22 @@
+#ifndef IMX7_IOMUXC_H
+#define IMX7_IOMUXC_H
+
+#include "hw/sysbus.h"
+
+enum IMX7IOMUXCRegisters {
+ IOMUXC_NUM = 0x740 / sizeof(uint32_t),
+};
+
+typedef struct IMX7IOMUXCState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[IOMUXC_NUM];
+} IMX7IOMUXCState;
+
+#define TYPE_IMX7_IOMUXC "imx7-iomuxc"
+#define IMX7_IOMUXC(obj) OBJECT_CHECK(IMX7IOMUXCState, (obj), TYPE_IMX7_IOMUXC)
+
+#endif /* IMX7_IOMUXC_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 19/27] i.MX: Add code to emulate SDMA IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (16 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 17/27] i.MX: Add code to emulate i.MX7 IOMUXC " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 20/27] i.MX: Add code to emulate FlexCAN " Andrey Smirnov
` (5 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/dma/Makefile.objs | 1 +
hw/dma/imx_sdma.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++
include/hw/dma/imx_sdma.h | 22 +++++++++++
3 files changed, 122 insertions(+)
create mode 100644 hw/dma/imx_sdma.c
create mode 100644 include/hw/dma/imx_sdma.h
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 087c8e6855..3cee0b1047 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -14,3 +14,4 @@ obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dpdma.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
obj-$(CONFIG_RASPI) += bcm2835_dma.o
+obj-$(CONFIG_IMX) += imx_sdma.o
diff --git a/hw/dma/imx_sdma.c b/hw/dma/imx_sdma.c
new file mode 100644
index 0000000000..0776e41b9a
--- /dev/null
+++ b/hw/dma/imx_sdma.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 IOMUXC block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/dma/imx_sdma.h"
+#include "qemu/log.h"
+
+static void imx_sdma_reset(DeviceState *dev)
+{
+ IMXSDMAState *s = IMX_SDMA(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static uint64_t imx_sdma_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ IMXSDMAState *s = opaque;
+ return s->regs[offset / sizeof(uint32_t)];
+}
+
+static void imx_sdma_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMXSDMAState *s = opaque;
+ s->regs[offset / sizeof(uint32_t)] = value;
+}
+
+static const struct MemoryRegionOps imx_sdma_ops = {
+ .read = imx_sdma_read,
+ .write = imx_sdma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx_sdma_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMXSDMAState *s = IMX_SDMA(obj);
+
+ memory_region_init_io(&s->iomem,
+ obj,
+ &imx_sdma_ops,
+ s,
+ TYPE_IMX_SDMA ".iomem",
+ sizeof(s->regs));
+ sysbus_init_mmio(sd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_imx_sdma = {
+ .name = TYPE_IMX_SDMA,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IMXSDMAState, SDMA_NUM),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx_sdma_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx_sdma_reset;
+ dc->vmsd = &vmstate_imx_sdma;
+ dc->desc = "i.MX IOMUXC Module";
+}
+
+static const TypeInfo imx_sdma_info = {
+ .name = TYPE_IMX_SDMA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXSDMAState),
+ .instance_init = imx_sdma_init,
+ .class_init = imx_sdma_class_init,
+};
+
+static void imx_sdma_register_type(void)
+{
+ type_register_static(&imx_sdma_info);
+}
+type_init(imx_sdma_register_type)
diff --git a/include/hw/dma/imx_sdma.h b/include/hw/dma/imx_sdma.h
new file mode 100644
index 0000000000..13c5be7a00
--- /dev/null
+++ b/include/hw/dma/imx_sdma.h
@@ -0,0 +1,22 @@
+#ifndef IMX_SDMA_H
+#define IMX_SDMA_H
+
+#include "hw/sysbus.h"
+
+enum IMXSDMARegisters {
+ SDMA_NUM = 0x300 / sizeof(uint32_t) + 1,
+};
+
+typedef struct IMXSDMAState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[SDMA_NUM];
+} IMXSDMAState;
+
+#define TYPE_IMX_SDMA "imx-sdma"
+#define IMX_SDMA(obj) OBJECT_CHECK(IMXSDMAState, (obj), TYPE_IMX_SDMA)
+
+#endif /* IMX_SDMA_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 20/27] i.MX: Add code to emulate FlexCAN IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (17 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 19/27] i.MX: Add code to emulate SDMA " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 21/27] i.MX: Add implementation of i.MX7 GPR " Andrey Smirnov
` (4 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx_flexcan.c | 99 +++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx_flexcan.h | 22 ++++++++++
3 files changed, 122 insertions(+)
create mode 100644 hw/misc/imx_flexcan.c
create mode 100644 include/hw/misc/imx_flexcan.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 492c535330..943b22af40 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -38,6 +38,7 @@ obj-$(CONFIG_IMX) += imx7_ccm.o
obj-$(CONFIG_IMX) += imx2_wdt.o
obj-$(CONFIG_IMX) += imx7_snvs.o
obj-$(CONFIG_IMX) += imx7_iomuxc.o
+obj-$(CONFIG_IMX) += imx_flexcan.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/hw/misc/imx_flexcan.c b/hw/misc/imx_flexcan.c
new file mode 100644
index 0000000000..dd4d3d6dc1
--- /dev/null
+++ b/hw/misc/imx_flexcan.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX FlexCAN block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/imx_flexcan.h"
+#include "qemu/log.h"
+
+static void imx_flexcan_reset(DeviceState *dev)
+{
+ IMXFlexCANState *s = IMX_FLEXCAN(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static uint64_t imx_flexcan_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ IMXFlexCANState *s = opaque;
+ return s->regs[offset / sizeof(uint32_t)];
+}
+
+static void imx_flexcan_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMXFlexCANState *s = opaque;
+ s->regs[offset / sizeof(uint32_t)] = value;
+}
+
+static const struct MemoryRegionOps imx_flexcan_ops = {
+ .read = imx_flexcan_read,
+ .write = imx_flexcan_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx_flexcan_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMXFlexCANState *s = IMX_FLEXCAN(obj);
+
+ memory_region_init_io(&s->iomem,
+ obj,
+ &imx_flexcan_ops,
+ s,
+ TYPE_IMX_FLEXCAN ".iomem",
+ sizeof(s->regs));
+ sysbus_init_mmio(sd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_imx_flexcan = {
+ .name = TYPE_IMX_FLEXCAN,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IMXFlexCANState, FLEXCAN_NUM),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx_flexcan_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx_flexcan_reset;
+ dc->vmsd = &vmstate_imx_flexcan;
+ dc->desc = "i.MX FlexCAN Module";
+}
+
+static const TypeInfo imx_flexcan_info = {
+ .name = TYPE_IMX_FLEXCAN,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXFlexCANState),
+ .instance_init = imx_flexcan_init,
+ .class_init = imx_flexcan_class_init,
+};
+
+static void imx_flexcan_register_type(void)
+{
+ type_register_static(&imx_flexcan_info);
+}
+type_init(imx_flexcan_register_type)
diff --git a/include/hw/misc/imx_flexcan.h b/include/hw/misc/imx_flexcan.h
new file mode 100644
index 0000000000..da9980cf86
--- /dev/null
+++ b/include/hw/misc/imx_flexcan.h
@@ -0,0 +1,22 @@
+#ifndef IMX_FLEXCAN_H
+#define IMX_FLEXCAN_H
+
+#include "hw/sysbus.h"
+
+enum IMXFlexCANRegisters {
+ FLEXCAN_NUM = 0x9E0 / sizeof(uint32_t) + 1,
+};
+
+typedef struct IMXFlexCANState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[FLEXCAN_NUM];
+} IMXFlexCANState;
+
+#define TYPE_IMX_FLEXCAN "imx-flexcan"
+#define IMX_FLEXCAN(obj) OBJECT_CHECK(IMXFlexCANState, (obj), TYPE_IMX_FLEXCAN)
+
+#endif /* IMX_FLEXCAN_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 21/27] i.MX: Add implementation of i.MX7 GPR IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (18 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 20/27] i.MX: Add code to emulate FlexCAN " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 22/27] pci: Add support for Designware " Andrey Smirnov
` (3 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx7_gpr.c | 119 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx7_gpr.h | 28 +++++++++++
3 files changed, 148 insertions(+)
create mode 100644 hw/misc/imx7_gpr.c
create mode 100644 include/hw/misc/imx7_gpr.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 943b22af40..c9944161bd 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -39,6 +39,7 @@ obj-$(CONFIG_IMX) += imx2_wdt.o
obj-$(CONFIG_IMX) += imx7_snvs.o
obj-$(CONFIG_IMX) += imx7_iomuxc.o
obj-$(CONFIG_IMX) += imx_flexcan.o
+obj-$(CONFIG_IMX) += imx7_gpr.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c
new file mode 100644
index 0000000000..9e8ccea9e8
--- /dev/null
+++ b/hw/misc/imx7_gpr.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 GPR IP block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * Bare minimum emulation code needed to support being able to shut
+ * down linux guest gracefully.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/imx7_gpr.h"
+#include "qemu/log.h"
+#include "sysemu/sysemu.h"
+
+enum IMX7GPRRegisters {
+ IOMUXC_GPR0 = 0x00,
+ IOMUXC_GPR1 = 0x04,
+ IOMUXC_GPR2 = 0x08,
+ IOMUXC_GPR3 = 0x0c,
+ IOMUXC_GPR4 = 0x10,
+ IOMUXC_GPR5 = 0x14,
+ IOMUXC_GPR6 = 0x18,
+ IOMUXC_GPR7 = 0x1c,
+ IOMUXC_GPR8 = 0x20,
+ IOMUXC_GPR9 = 0x24,
+ IOMUXC_GPR10 = 0x28,
+ IOMUXC_GPR11 = 0x2c,
+ IOMUXC_GPR12 = 0x30,
+ IOMUXC_GPR13 = 0x34,
+ IOMUXC_GPR14 = 0x38,
+ IOMUXC_GPR15 = 0x3c,
+ IOMUXC_GPR16 = 0x40,
+ IOMUXC_GPR17 = 0x44,
+ IOMUXC_GPR18 = 0x48,
+ IOMUXC_GPR19 = 0x4c,
+ IOMUXC_GPR20 = 0x50,
+ IOMUXC_GPR21 = 0x54,
+ IOMUXC_GPR22 = 0x58,
+};
+
+#define IMX7D_GPR1_IRQ_MASK BIT(12)
+#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK BIT(13)
+#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK BIT(14)
+#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
+#define IMX7D_GPR1_ENET1_CLK_DIR_MASK BIT(17)
+#define IMX7D_GPR1_ENET2_CLK_DIR_MASK BIT(18)
+#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
+
+#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI BIT(4)
+#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)
+#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)
+
+
+static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size)
+{
+ if (offset == IOMUXC_GPR22) {
+ return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED;
+ }
+
+ return 0;
+}
+
+static void imx7_gpr_write(void *opaque, hwaddr offset,
+ uint64_t v, unsigned size)
+{
+}
+
+static const struct MemoryRegionOps imx7_gpr_ops = {
+ .read = imx7_gpr_read,
+ .write = imx7_gpr_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the
+ * real device but in practice there is no reason for a guest
+ * to access this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx7_gpr_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMX7GPRState *s = IMX7_GPR(obj);
+
+ memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,
+ TYPE_IMX7_GPR, 64 * 1024);
+ sysbus_init_mmio(sd, &s->mmio);
+}
+
+static void imx7_gpr_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "i.MX7 General Purpose Registers Module";
+}
+
+static const TypeInfo imx7_gpr_info = {
+ .name = TYPE_IMX7_GPR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMX7GPRState),
+ .instance_init = imx7_gpr_init,
+ .class_init = imx7_gpr_class_init,
+};
+
+static void imx7_gpr_register_type(void)
+{
+ type_register_static(&imx7_gpr_info);
+}
+type_init(imx7_gpr_register_type)
diff --git a/include/hw/misc/imx7_gpr.h b/include/hw/misc/imx7_gpr.h
new file mode 100644
index 0000000000..e19373d274
--- /dev/null
+++ b/include/hw/misc/imx7_gpr.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 GPR IP block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX7_GPR_H
+#define IMX7_GPR_H
+
+#include "qemu/bitops.h"
+#include "hw/sysbus.h"
+
+#define TYPE_IMX7_GPR "imx7.gpr"
+#define IMX7_GPR(obj) OBJECT_CHECK(IMX7GPRState, (obj), TYPE_IMX7_GPR)
+
+typedef struct IMX7GPRState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+} IMX7GPRState;
+
+#endif /* IMX7_GPR_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 22/27] pci: Add support for Designware IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (19 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 21/27] i.MX: Add implementation of i.MX7 GPR " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 23/27] i.MX: Add code to emulate i.MX7 USBMISC " Andrey Smirnov
` (2 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add code needed to get a functional PCI subsytem when using in
conjunction with upstream Linux guest (4.13+). Tested to work against
"e1000e" (network adapter, using MSI interrupts) as well as
"usb-ehci" (USB controller, using legacy PCI interrupts).
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
default-configs/arm-softmmu.mak | 2 +
hw/pci-host/Makefile.objs | 2 +
hw/pci-host/designware.c | 614 +++++++++++++++++++++++++++++++++++++++
include/hw/pci-host/designware.h | 92 ++++++
include/hw/pci/pci_ids.h | 2 +
5 files changed, 712 insertions(+)
create mode 100644 hw/pci-host/designware.c
create mode 100644 include/hw/pci-host/designware.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index bbdd3c1d8b..225ebbd90a 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -129,3 +129,5 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+
+CONFIG_PCI_DESIGNWARE=y
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index 9c7909cf44..0e2c0a123b 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -17,3 +17,5 @@ common-obj-$(CONFIG_PCI_PIIX) += piix.o
common-obj-$(CONFIG_PCI_Q35) += q35.o
common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
+
+common-obj-$(CONFIG_PCI_DESIGNWARE) += designware.o
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
new file mode 100644
index 0000000000..7ae4126d96
--- /dev/null
+++ b/hw/pci-host/designware.c
@@ -0,0 +1,614 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * Designware PCIe IP block emulation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci/pcie_port.h"
+#include "hw/pci-host/designware.h"
+
+#define PCIE_PORT_LINK_CONTROL 0x710
+
+#define PCIE_PHY_DEBUG_R1 0x72C
+#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
+
+#define PCIE_MSI_ADDR_LO 0x820
+#define PCIE_MSI_ADDR_HI 0x824
+#define PCIE_MSI_INTR0_ENABLE 0x828
+#define PCIE_MSI_INTR0_MASK 0x82C
+#define PCIE_MSI_INTR0_STATUS 0x830
+
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
+#define PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
+static DesignwarePCIEHost *
+designware_pcie_root_to_host(DesignwarePCIERoot *root)
+{
+ BusState *bus = qdev_get_parent_bus(DEVICE(root));
+ return DESIGNWARE_PCIE_HOST(bus->parent);
+}
+
+static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned len)
+{
+ DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
+ DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+
+ root->msi.intr[0].status |= (1 << val) & root->msi.intr[0].enable;
+
+ if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
+ qemu_set_irq(host->pci.irqs[0], 1);
+ }
+}
+
+const MemoryRegionOps designware_pci_host_msi_ops = {
+ .write = designware_pcie_root_msi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)
+
+{
+ DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+ MemoryRegion *address_space = &host->pci.memory;
+ MemoryRegion *mem = &root->msi.iomem;
+ const uint64_t base = root->msi.base;
+ const bool enable = root->msi.intr[0].enable;
+
+ if (memory_region_is_mapped(mem)) {
+ memory_region_del_subregion(address_space, mem);
+ object_unparent(OBJECT(mem));
+ }
+
+ if (enable) {
+ memory_region_init_io(mem, OBJECT(root),
+ &designware_pci_host_msi_ops,
+ root, "pcie-msi", 0x1000);
+
+ memory_region_add_subregion(address_space, base, mem);
+ }
+}
+
+static DesignwarePCIEViewport *
+designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)
+{
+ const unsigned int idx = root->atu_viewport & 0xF;
+ const unsigned int dir = !!(root->atu_viewport & PCIE_ATU_REGION_INBOUND);
+ return &root->viewports[dir][idx];
+}
+
+static uint32_t
+designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
+{
+ DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
+ DesignwarePCIEViewport *viewport =
+ designware_pcie_root_get_current_viewport(root);
+
+ uint32_t val;
+
+ switch (address) {
+ case PCIE_PORT_LINK_CONTROL:
+ case PCIE_LINK_WIDTH_SPEED_CONTROL:
+ val = 0xDEADBEEF;
+ /* No-op */
+ break;
+
+ case PCIE_MSI_ADDR_LO:
+ val = root->msi.base;
+ break;
+
+ case PCIE_MSI_ADDR_HI:
+ val = root->msi.base >> 32;
+ break;
+
+ case PCIE_MSI_INTR0_ENABLE:
+ val = root->msi.intr[0].enable;
+ break;
+
+ case PCIE_MSI_INTR0_MASK:
+ val = root->msi.intr[0].mask;
+ break;
+
+ case PCIE_MSI_INTR0_STATUS:
+ val = root->msi.intr[0].status;
+ break;
+
+ case PCIE_PHY_DEBUG_R1:
+ val = PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
+ break;
+
+ case PCIE_ATU_VIEWPORT:
+ val = root->atu_viewport;
+ break;
+
+ case PCIE_ATU_LOWER_BASE:
+ val = viewport->base;
+ break;
+
+ case PCIE_ATU_UPPER_BASE:
+ val = viewport->base >> 32;
+ break;
+
+ case PCIE_ATU_LOWER_TARGET:
+ val = viewport->target;
+ break;
+
+ case PCIE_ATU_UPPER_TARGET:
+ val = viewport->target >> 32;
+ break;
+
+ case PCIE_ATU_LIMIT:
+ val = viewport->limit;
+ break;
+
+ case PCIE_ATU_CR1:
+ case PCIE_ATU_CR2: /* FALLTHROUGH */
+ val = viewport->cr[(address - PCIE_ATU_CR1) / sizeof(uint32_t)];
+ break;
+
+ default:
+ val = pci_default_read_config(d, address, len);
+ break;
+ }
+
+ return val;
+}
+
+static uint64_t designware_pcie_root_data_read(void *opaque,
+ hwaddr addr, unsigned len)
+{
+ DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
+ DesignwarePCIEViewport *viewport =
+ designware_pcie_root_get_current_viewport(root);
+
+ const uint8_t busnum = PCIE_ATU_BUS(viewport->target);
+ const uint8_t devfn = PCIE_ATU_DEVFN(viewport->target);
+ PCIBus *pcibus = PCI_DEVICE(root)->bus;
+ PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn);
+
+ if (pcidev) {
+ addr &= PCI_CONFIG_SPACE_SIZE - 1;
+
+ return pci_host_config_read_common(pcidev, addr,
+ PCI_CONFIG_SPACE_SIZE, len);
+ }
+
+ return UINT64_MAX;
+}
+
+static void designware_pcie_root_data_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned len)
+{
+ DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
+ DesignwarePCIEViewport *viewport =
+ designware_pcie_root_get_current_viewport(root);
+ const uint8_t busnum = PCIE_ATU_BUS(viewport->target);
+ const uint8_t devfn = PCIE_ATU_DEVFN(viewport->target);
+ PCIBus *pcibus = PCI_DEVICE(root)->bus;
+ PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn);
+
+ if (pcidev) {
+ addr &= PCI_CONFIG_SPACE_SIZE - 1;
+ pci_host_config_write_common(pcidev, addr,
+ PCI_CONFIG_SPACE_SIZE,
+ val, len);
+ }
+}
+
+const MemoryRegionOps designware_pci_host_conf_ops = {
+ .read = designware_pcie_root_data_read,
+ .write = designware_pcie_root_data_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void designware_pcie_update_viewport(DesignwarePCIERoot *root,
+ DesignwarePCIEViewport *viewport)
+{
+ DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+
+ MemoryRegion *mem = &viewport->memory;
+ const uint64_t target = viewport->target;
+ const uint64_t base = viewport->base;
+ const uint64_t size = (uint64_t)viewport->limit - base + 1;
+ const bool inbound = viewport->inbound;
+
+ MemoryRegion *source, *destination;
+ const char *direction;
+ char *name;
+
+ if (inbound) {
+ source = &host->pci.address_space_root;
+ destination = get_system_memory();
+ direction = "Inbound";
+ } else {
+ source = get_system_memory();
+ destination = &host->pci.memory;
+ direction = "Outbound";
+ }
+
+ if (memory_region_is_mapped(mem)) {
+ /* Before we modify anything, unmap and destroy the region */
+ memory_region_del_subregion(source, mem);
+ object_unparent(OBJECT(mem));
+ }
+
+ name = g_strdup_printf("PCI %s Viewport %p", direction, viewport);
+
+ switch (viewport->cr[0]) {
+ case PCIE_ATU_TYPE_MEM:
+ memory_region_init_alias(mem, OBJECT(root), name,
+ destination, target, size);
+ break;
+ case PCIE_ATU_TYPE_CFG0:
+ case PCIE_ATU_TYPE_CFG1: /* FALLTHROUGH */
+ if (inbound) {
+ goto exit;
+ }
+
+ memory_region_init_io(mem, OBJECT(root),
+ &designware_pci_host_conf_ops,
+ root, name, size);
+ break;
+ }
+
+ if (inbound) {
+ memory_region_add_subregion_overlap(source, base,
+ mem, -1);
+ } else {
+ memory_region_add_subregion(source, base, mem);
+ }
+
+ exit:
+ g_free(name);
+}
+
+static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
+ uint32_t val, int len)
+{
+ DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
+ DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+ DesignwarePCIEViewport *viewport =
+ designware_pcie_root_get_current_viewport(root);
+
+ switch (address) {
+ case PCIE_PORT_LINK_CONTROL:
+ case PCIE_LINK_WIDTH_SPEED_CONTROL:
+ case PCIE_PHY_DEBUG_R1:
+ /* No-op */
+ break;
+
+ case PCIE_MSI_ADDR_LO:
+ root->msi.base &= 0xFFFFFFFF00000000ULL;
+ root->msi.base |= val;
+ break;
+
+ case PCIE_MSI_ADDR_HI:
+ root->msi.base &= 0x00000000FFFFFFFFULL;
+ root->msi.base |= (uint64_t)val << 32;
+ break;
+
+ case PCIE_MSI_INTR0_ENABLE: {
+ const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
+
+ root->msi.intr[0].enable = val;
+
+ if (update_msi_mapping) {
+ designware_pcie_root_update_msi_mapping(root);
+ }
+ break;
+ }
+
+ case PCIE_MSI_INTR0_MASK:
+ root->msi.intr[0].mask = val;
+ break;
+
+ case PCIE_MSI_INTR0_STATUS:
+ root->msi.intr[0].status ^= val;
+ if (!root->msi.intr[0].status) {
+ qemu_set_irq(host->pci.irqs[0], 0);
+ }
+ break;
+
+ case PCIE_ATU_VIEWPORT:
+ root->atu_viewport = val;
+ break;
+
+ case PCIE_ATU_LOWER_BASE:
+ viewport->base &= 0xFFFFFFFF00000000ULL;
+ viewport->base |= val;
+ break;
+
+ case PCIE_ATU_UPPER_BASE:
+ viewport->base &= 0x00000000FFFFFFFFULL;
+ viewport->base |= (uint64_t)val << 32;
+ break;
+
+ case PCIE_ATU_LOWER_TARGET:
+ viewport->target &= 0xFFFFFFFF00000000ULL;
+ viewport->target |= val;
+ break;
+
+ case PCIE_ATU_UPPER_TARGET:
+ viewport->target &= 0x00000000FFFFFFFFULL;
+ viewport->target |= val;
+ break;
+
+ case PCIE_ATU_LIMIT:
+ viewport->limit = val;
+ break;
+
+ case PCIE_ATU_CR1:
+ viewport->cr[0] = val;
+ break;
+ case PCIE_ATU_CR2:
+ viewport->cr[1] = val;
+
+ if (viewport->cr[1] & PCIE_ATU_ENABLE) {
+ designware_pcie_update_viewport(root, viewport);
+ }
+ break;
+
+ default:
+ pci_bridge_write_config(d, address, val, len);
+ break;
+ }
+}
+
+static int designware_pcie_root_init(PCIDevice *dev)
+{
+ DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
+ PCIBridge *br = PCI_BRIDGE(dev);
+ DesignwarePCIEViewport *viewport;
+ size_t i;
+
+ br->bus_name = "dw-pcie";
+
+ pci_set_word(dev->config + PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ pci_config_set_interrupt_pin(dev->config, 1);
+ pci_bridge_initfn(dev, TYPE_PCI_BUS);
+
+ pcie_port_init_reg(dev);
+
+ pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT,
+ 0, &error_fatal);
+
+ msi_nonbroken = true;
+ msi_init(dev, 0x50, 32, true, true, &error_fatal);
+
+ for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) {
+ viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];
+ viewport->inbound = true;
+ }
+
+ /*
+ * If no inbound iATU windows are configured, HW defaults to
+ * letting inbound TLPs to pass in. We emulate that by exlicitly
+ * configuring first inbound window to cover all of target's
+ * address space.
+ *
+ * NOTE: This will not work correctly for the case when first
+ * configured inbound window is window 0
+ */
+ viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];
+ viewport->base = 0x0000000000000000ULL;
+ viewport->target = 0x0000000000000000ULL;
+ viewport->limit = UINT32_MAX;
+ viewport->cr[0] = PCIE_ATU_TYPE_MEM;
+
+ designware_pcie_update_viewport(root, viewport);
+
+ return 0;
+}
+
+static void designware_pcie_set_irq(void *opaque, int irq_num, int level)
+{
+ DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque);
+
+ qemu_set_irq(host->pci.irqs[irq_num], level);
+}
+
+static const char *designware_pcie_host_root_bus_path(PCIHostState *host_bridge,
+ PCIBus *rootbus)
+{
+ return "0000:00";
+}
+
+
+static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+
+ k->vendor_id = PCI_VENDOR_ID_SYNOPSYS;
+ k->device_id = 0xABCD;
+ k->revision = 0;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ k->is_express = true;
+ k->is_bridge = true;
+ k->init = designware_pcie_root_init;
+ k->exit = pci_bridge_exitfn;
+ dc->reset = pci_bridge_reset;
+ k->config_read = designware_pcie_root_config_read;
+ k->config_write = designware_pcie_root_config_write;
+
+ /*
+ * PCI-facing part of the host bridge, not usable without the
+ * host-facing part, which can't be device_add'ed, yet.
+ */
+ dc->user_creatable = false;
+}
+
+static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
+ PCIDevice *device = pci_find_device(pci->bus, 0, 0);
+
+ return pci_host_config_read_common(device,
+ addr,
+ pci_config_size(device),
+ size);
+}
+
+static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int size)
+{
+ PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
+ PCIDevice *device = pci_find_device(pci->bus, 0, 0);
+
+ return pci_host_config_write_common(device,
+ addr,
+ pci_config_size(device),
+ val, size);
+}
+
+static const MemoryRegionOps designware_pci_mmio_ops = {
+ .read = designware_pcie_host_mmio_read,
+ .write = designware_pcie_host_mmio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque,
+ int devfn)
+{
+ DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque);
+
+ return &s->pci.address_space;
+}
+
+static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
+{
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+ DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {
+ sysbus_init_irq(sbd, &s->pci.irqs[i]);
+ }
+
+ memory_region_init_io(&s->mmio,
+ OBJECT(s),
+ &designware_pci_mmio_ops,
+ s,
+ "pcie.reg", 4 * 1024);
+ sysbus_init_mmio(sbd, &s->mmio);
+
+ memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
+ memory_region_init(&s->pci.memory, OBJECT(s),
+ "pcie-bus-memory",
+ UINT64_MAX);
+
+ pci->bus = pci_register_bus(dev, "pcie",
+ designware_pcie_set_irq,
+ pci_swizzle_map_irq_fn,
+ s,
+ &s->pci.memory,
+ &s->pci.io,
+ 0, 4,
+ TYPE_PCIE_BUS);
+
+ memory_region_init(&s->pci.address_space_root,
+ OBJECT(s),
+ "pcie-bus-address-space-root",
+ UINT64_MAX);
+ memory_region_add_subregion(&s->pci.address_space_root,
+ 0x0, &s->pci.memory);
+ address_space_init(&s->pci.address_space,
+ &s->pci.address_space_root,
+ "pcie-bus-address-space");
+ pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s);
+
+ qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
+ qdev_init_nofail(DEVICE(&s->root));
+}
+
+static void designware_pcie_host_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
+
+ hc->root_bus_path = designware_pcie_host_root_bus_path;
+ dc->realize = designware_pcie_host_realize;
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->fw_name = "pci";
+}
+
+static void designware_pcie_host_init(Object *obj)
+{
+ DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj);
+ DesignwarePCIERoot *root = &s->root;
+
+ object_initialize(root, sizeof(*root), TYPE_DESIGNWARE_PCIE_ROOT);
+ object_property_add_child(obj, "root", OBJECT(root), NULL);
+ qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
+ qdev_prop_set_bit(DEVICE(root), "multifunction", false);
+}
+
+static const TypeInfo designware_pcie_root_info = {
+ .name = TYPE_DESIGNWARE_PCIE_ROOT,
+ .parent = TYPE_PCI_BRIDGE,
+ .instance_size = sizeof(DesignwarePCIERoot),
+ .class_init = designware_pcie_root_class_init,
+};
+
+static const TypeInfo designware_pcie_host_info = {
+ .name = TYPE_DESIGNWARE_PCIE_HOST,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .instance_size = sizeof(DesignwarePCIEHost),
+ .instance_init = designware_pcie_host_init,
+ .class_init = designware_pcie_host_class_init,
+};
+
+static void designware_pcie_register(void)
+{
+ type_register_static(&designware_pcie_root_info);
+ type_register_static(&designware_pcie_host_info);
+}
+type_init(designware_pcie_register)
+
+/* 00:00.0 Class 0604: 16c3:abcd */
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
new file mode 100644
index 0000000000..c1eabfa16b
--- /dev/null
+++ b/include/hw/pci-host/designware.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * Designware PCIe IP block emulation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DESIGNWARE_H
+#define DESIGNWARE_H
+
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pcie_host.h"
+
+#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
+#define DESIGNWARE_PCIE_HOST(obj) \
+ OBJECT_CHECK(DesignwarePCIEHost, (obj), TYPE_DESIGNWARE_PCIE_HOST)
+
+#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
+#define DESIGNWARE_PCIE_ROOT(obj) \
+ OBJECT_CHECK(DesignwarePCIERoot, (obj), TYPE_DESIGNWARE_PCIE_ROOT)
+
+typedef struct DesignwarePCIEViewport {
+ MemoryRegion memory;
+
+ uint64_t base;
+ uint64_t target;
+ uint32_t limit;
+ uint32_t cr[2];
+
+ bool inbound;
+} DesignwarePCIEViewport;
+
+typedef struct DesignwarePCIERoot {
+ PCIBridge parent_obj;
+
+ uint32_t atu_viewport;
+
+#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND 0
+#define DESIGNWARE_PCIE_VIEWPORT_INBOUND 1
+#define DESIGNWARE_PCIE_NUM_VIEWPORTS 4
+
+ DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
+
+ struct {
+ uint64_t base;
+ MemoryRegion iomem;
+
+ struct {
+ uint32_t enable;
+ uint32_t mask;
+ uint32_t status;
+ } intr[1];
+ } msi;
+} DesignwarePCIERoot;
+
+typedef struct DesignwarePCIEHost {
+ PCIHostState parent_obj;
+
+ bool link_up;
+
+ DesignwarePCIERoot root;
+
+ struct {
+ AddressSpace address_space;
+ MemoryRegion address_space_root;
+
+ MemoryRegion memory;
+ MemoryRegion io;
+
+ qemu_irq irqs[4];
+ } pci;
+
+ MemoryRegion mmio;
+} DesignwarePCIEHost;
+
+#endif /* DESIGNWARE_H */
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index 3752ddc93a..e2816d054f 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -264,4 +264,6 @@
#define PCI_VENDOR_ID_TEWS 0x1498
#define PCI_DEVICE_ID_TEWS_TPCI200 0x30C8
+#define PCI_VENDOR_ID_SYNOPSYS 0x16C3
+
#endif
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 23/27] i.MX: Add code to emulate i.MX7 USBMISC IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (20 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 22/27] pci: Add support for Designware " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 24/27] i.MX: Add code to emulate i.MX7 ADC " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 26/27] i.MX: Add i.MX7 SOC implementation Andrey Smirnov
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/usb/Makefile.objs | 1 +
hw/usb/imx-usbmisc.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
include/hw/usb/imx-usbmisc.h | 22 ++++++++++
3 files changed, 122 insertions(+)
create mode 100644 hw/usb/imx-usbmisc.c
create mode 100644 include/hw/usb/imx-usbmisc.h
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index 97f1c4561a..813359fadc 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
obj-$(CONFIG_TUSB6010) += tusb6010.o
+obj-$(CONFIG_IMX) += imx-usbmisc.o
# emulated usb devices
common-obj-$(CONFIG_USB) += dev-hub.o
diff --git a/hw/usb/imx-usbmisc.c b/hw/usb/imx-usbmisc.c
new file mode 100644
index 0000000000..d5e236a4be
--- /dev/null
+++ b/hw/usb/imx-usbmisc.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 IOMUXC block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/usb/imx-usbmisc.h"
+#include "qemu/log.h"
+
+static void imx_usbmisc_reset(DeviceState *dev)
+{
+ IMXUSBMiscState *s = IMX_USBMISC(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static uint64_t imx_usbmisc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ IMXUSBMiscState *s = opaque;
+ return s->regs[offset / sizeof(uint32_t)];
+}
+
+static void imx_usbmisc_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMXUSBMiscState *s = opaque;
+ s->regs[offset / sizeof(uint32_t)] = value;
+}
+
+static const struct MemoryRegionOps imx_usbmisc_ops = {
+ .read = imx_usbmisc_read,
+ .write = imx_usbmisc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx_usbmisc_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMXUSBMiscState *s = IMX_USBMISC(obj);
+
+ memory_region_init_io(&s->iomem,
+ obj,
+ &imx_usbmisc_ops,
+ s,
+ TYPE_IMX_USBMISC ".iomem",
+ sizeof(s->regs));
+ sysbus_init_mmio(sd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_imx_usbmisc = {
+ .name = TYPE_IMX_USBMISC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IMXUSBMiscState, USBMISC_NUM),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx_usbmisc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx_usbmisc_reset;
+ dc->vmsd = &vmstate_imx_usbmisc;
+ dc->desc = "i.MX IOMUXC Module";
+}
+
+static const TypeInfo imx_usbmisc_info = {
+ .name = TYPE_IMX_USBMISC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXUSBMiscState),
+ .instance_init = imx_usbmisc_init,
+ .class_init = imx_usbmisc_class_init,
+};
+
+static void imx_usbmisc_register_type(void)
+{
+ type_register_static(&imx_usbmisc_info);
+}
+type_init(imx_usbmisc_register_type)
diff --git a/include/hw/usb/imx-usbmisc.h b/include/hw/usb/imx-usbmisc.h
new file mode 100644
index 0000000000..64b06f3d3c
--- /dev/null
+++ b/include/hw/usb/imx-usbmisc.h
@@ -0,0 +1,22 @@
+#ifndef IMX_USBMISC_H
+#define IMX_USBMISC_H
+
+#include "hw/sysbus.h"
+
+enum IMXUSBMiscRegisters {
+ USBMISC_NUM = 0x24 / sizeof(uint32_t) + 1,
+};
+
+typedef struct IMXUSBMiscState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[USBMISC_NUM];
+} IMXUSBMiscState;
+
+#define TYPE_IMX_USBMISC "imx-usbmisc"
+#define IMX_USBMISC(obj) OBJECT_CHECK(IMXUSBMiscState, (obj), TYPE_IMX_USBMISC)
+
+#endif /* IMX_USBMISC_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 24/27] i.MX: Add code to emulate i.MX7 ADC IP block
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (21 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 23/27] i.MX: Add code to emulate i.MX7 USBMISC " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 26/27] i.MX: Add i.MX7 SOC implementation Andrey Smirnov
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/imx7_adc.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/imx7_adc.h | 22 +++++++++++
3 files changed, 122 insertions(+)
create mode 100644 hw/misc/imx7_adc.c
create mode 100644 include/hw/misc/imx7_adc.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c9944161bd..b578bd0cba 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -39,6 +39,7 @@ obj-$(CONFIG_IMX) += imx2_wdt.o
obj-$(CONFIG_IMX) += imx7_snvs.o
obj-$(CONFIG_IMX) += imx7_iomuxc.o
obj-$(CONFIG_IMX) += imx_flexcan.o
+obj-$(CONFIG_IMX) += imx7_adc.o
obj-$(CONFIG_IMX) += imx7_gpr.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
diff --git a/hw/misc/imx7_adc.c b/hw/misc/imx7_adc.c
new file mode 100644
index 0000000000..7945e99075
--- /dev/null
+++ b/hw/misc/imx7_adc.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 ADC block emulation code
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/imx7_adc.h"
+#include "qemu/log.h"
+
+static void imx7_adc_reset(DeviceState *dev)
+{
+ IMX7ADCState *s = IMX7_ADC(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static uint64_t imx7_adc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ IMX7ADCState *s = opaque;
+ return s->regs[offset / sizeof(uint32_t)];
+}
+
+static void imx7_adc_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMX7ADCState *s = opaque;
+ s->regs[offset / sizeof(uint32_t)] = value;
+}
+
+static const struct MemoryRegionOps imx7_adc_ops = {
+ .read = imx7_adc_read,
+ .write = imx7_adc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx7_adc_init(Object *obj)
+{
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ IMX7ADCState *s = IMX7_ADC(obj);
+
+ memory_region_init_io(&s->iomem,
+ obj,
+ &imx7_adc_ops,
+ s,
+ TYPE_IMX7_ADC ".iomem",
+ sizeof(s->regs));
+ sysbus_init_mmio(sd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_imx7_adc = {
+ .name = TYPE_IMX7_ADC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IMX7ADCState, ADC_NUM),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx7_adc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx7_adc_reset;
+ dc->vmsd = &vmstate_imx7_adc;
+ dc->desc = "i.MX ADC Module";
+}
+
+static const TypeInfo imx7_adc_info = {
+ .name = TYPE_IMX7_ADC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMX7ADCState),
+ .instance_init = imx7_adc_init,
+ .class_init = imx7_adc_class_init,
+};
+
+static void imx7_adc_register_type(void)
+{
+ type_register_static(&imx7_adc_info);
+}
+type_init(imx7_adc_register_type)
diff --git a/include/hw/misc/imx7_adc.h b/include/hw/misc/imx7_adc.h
new file mode 100644
index 0000000000..4a61c52caf
--- /dev/null
+++ b/include/hw/misc/imx7_adc.h
@@ -0,0 +1,22 @@
+#ifndef IMX7_ADC_H
+#define IMX7_ADC_H
+
+#include "hw/sysbus.h"
+
+enum IMX7ADCRegisters {
+ ADC_NUM = 0x130 / sizeof(uint32_t) + 1,
+};
+
+typedef struct IMX7ADCState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[ADC_NUM];
+} IMX7ADCState;
+
+#define TYPE_IMX7_ADC "imx7-adc"
+#define IMX7_ADC(obj) OBJECT_CHECK(IMX7ADCState, (obj), TYPE_IMX7_ADC)
+
+#endif /* IMX7_ADC_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 26/27] i.MX: Add i.MX7 SOC implementation.
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
` (22 preceding siblings ...)
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 24/27] i.MX: Add code to emulate i.MX7 ADC " Andrey Smirnov
@ 2017-10-23 20:10 ` Andrey Smirnov
23 siblings, 0 replies; 25+ messages in thread
From: Andrey Smirnov @ 2017-10-23 20:10 UTC (permalink / raw)
To: qemu-arm
Cc: Andrey Smirnov, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé,
qemu-devel, yurovsky
The following interfaces are partially or fully emulated:
* up to 2 Cortex A9 cores (SMP works with PSCI)
* A7 MPCORE (identical to A15 MPCORE)
* 4 GPTs modules
* 7 GPIO controllers
* 2 IOMUXC controllers
* 1 CCM module
* 1 SVNS module
* 1 SRC module
* 1 GPCv2 controller
* 4 eCSPI controllers
* 4 I2C controllers
* 7 i.MX UART controllers
* 2 FlexCAN controllers
* 2 Ethernet controllers (FEC)
* 3 SD controllers (USDHC)
* 4 WDT modules
* 1 SDMA module
* 1 GPR module
* 2 USBMISC modules
* 2 ADC modules
* 1 PCIe controller
Tested to boot and work with upstream Linux (4.13+) guest.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 2 +
hw/arm/fsl-imx7.c | 596 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/fsl-imx7.h | 217 +++++++++++++++
4 files changed, 816 insertions(+)
create mode 100644 hw/arm/fsl-imx7.c
create mode 100644 include/hw/arm/fsl-imx7.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 225ebbd90a..a2f318d6dd 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -118,6 +118,7 @@ CONFIG_ALLWINNER_A10=y
CONFIG_FSL_IMX6=y
CONFIG_FSL_IMX31=y
CONFIG_FSL_IMX25=y
+CONFIG_FSL_IMX7=y
CONFIG_IMX_I2C=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index a2e56ecaae..33f6051ae3 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,3 +19,5 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
obj-$(CONFIG_MPS2) += mps2.o
+obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o
+
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
new file mode 100644
index 0000000000..f1a6a79179
--- /dev/null
+++ b/hw/arm/fsl-imx7.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 SoC definitions
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * Based on hw/arm/fsl-imx6.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/fsl-imx7.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+
+#define NAME_SIZE 20
+
+static void fsl_imx7_init(Object *obj)
+{
+ BusState *sysbus = sysbus_get_default();
+ FslIMX7State *s = FSL_IMX7(obj);
+ char name[NAME_SIZE];
+ int i;
+
+ if (smp_cpus > FSL_IMX7_NUM_CPUS) {
+ error_report("%s: Only %d CPUs are supported (%d requested)",
+ TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
+ exit(1);
+ }
+
+ for (i = 0; i < smp_cpus; i++) {
+ object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
+ "cortex-a7-" TYPE_ARM_CPU);
+ snprintf(name, NAME_SIZE, "cpu%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->cpu[i]),
+ &error_fatal);
+ }
+
+ /*
+ * A7MPCORE
+ */
+ object_initialize(&s->a7mpcore, sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
+ qdev_set_parent_bus(DEVICE(&s->a7mpcore), sysbus);
+ object_property_add_child(obj, "a7mpcore",
+ OBJECT(&s->a7mpcore), &error_fatal);
+
+ /*
+ * GPIOs 1 to 7
+ */
+ for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+ object_initialize(&s->gpio[i], sizeof(s->gpio[i]),
+ TYPE_IMX_GPIO);
+ qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus);
+ snprintf(name, NAME_SIZE, "gpio%d", i);
+ object_property_add_child(obj, name,
+ OBJECT(&s->gpio[i]), &error_fatal);
+ }
+
+ /*
+ * IOMUXC and IOMUXC_LPSR
+ */
+ for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
+ object_initialize(&s->iomuxc[i], sizeof(s->iomuxc[i]),
+ TYPE_IMX7_IOMUXC);
+ qdev_set_parent_bus(DEVICE(&s->iomuxc[i]), sysbus);
+ snprintf(name, NAME_SIZE, "iomuxc%d", i);
+ object_property_add_child(obj, name,
+ OBJECT(&s->iomuxc[i]), &error_fatal);
+ }
+
+ /*
+ * GPT1, 2, 3, 4
+ */
+ for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+ object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX7_GPT);
+ qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus);
+ snprintf(name, NAME_SIZE, "gpt%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->gpt[i]),
+ &error_fatal);
+ }
+
+ /*
+ * CCM
+ */
+ object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM);
+ qdev_set_parent_bus(DEVICE(&s->ccm), sysbus);
+ object_property_add_child(obj, "ccm", OBJECT(&s->ccm), &error_fatal);
+
+ /*
+ * GPCv2
+ */
+ object_initialize(&s->gpcv2, sizeof(s->gpcv2), TYPE_IMX_GPCV2);
+ qdev_set_parent_bus(DEVICE(&s->gpcv2), sysbus);
+ object_property_add_child(obj, "gpcv2", OBJECT(&s->gpcv2), &error_fatal);
+
+ for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+ object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI);
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+ snprintf(name, NAME_SIZE, "spi%d", i + 1);
+ object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL);
+ }
+
+
+ for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+ object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
+ qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
+ snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+ object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL);
+ }
+
+ /*
+ * UART
+ */
+ for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+ object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
+ qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus);
+ snprintf(name, NAME_SIZE, "uart%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->uart[i]),
+ &error_fatal);
+ }
+
+ /*
+ * FlexCAN1 and 2
+ */
+
+ for (i = 0; i < FSL_IMX7_NUM_FLEXCANS; i++) {
+ object_initialize(&s->flexcan[i],
+ sizeof(s->flexcan[i]), TYPE_IMX_FLEXCAN);
+ qdev_set_parent_bus(DEVICE(&s->flexcan[i]), sysbus);
+ snprintf(name, NAME_SIZE, "flexcan%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->flexcan[i]),
+ &error_fatal);
+ }
+
+ /*
+ * Ethernet
+ */
+ for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
+ object_initialize(&s->eth[i], sizeof(s->eth[i]), TYPE_IMX_ENET);
+ qdev_set_parent_bus(DEVICE(&s->eth[i]), sysbus);
+ snprintf(name, NAME_SIZE, "eth%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->eth[i]),
+ &error_fatal);
+ }
+
+ /*
+ * SDHCI
+ */
+ for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+ object_initialize(&s->usdhc[i], sizeof(s->usdhc[i]),
+ TYPE_IMX_USDHC);
+ qdev_set_parent_bus(DEVICE(&s->usdhc[i]), sysbus);
+ snprintf(name, NAME_SIZE, "usdhc%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->usdhc[i]),
+ &error_fatal);
+ }
+
+ /*
+ * SNVS
+ */
+ object_initialize(&s->snvs, sizeof(s->snvs), TYPE_IMX7_SNVS);
+ qdev_set_parent_bus(DEVICE(&s->snvs), sysbus);
+ object_property_add_child(obj, "snvs", OBJECT(&s->snvs), &error_fatal);
+
+ /*
+ * SRC
+ */
+ object_initialize(&s->src, sizeof(s->src), TYPE_IMX7_SRC);
+ qdev_set_parent_bus(DEVICE(&s->src), sysbus);
+ object_property_add_child(obj, "src", OBJECT(&s->src), &error_fatal);
+
+ /*
+ * Watchdog
+ */
+ for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+ object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_IMX2_WDT);
+ qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus);
+ snprintf(name, NAME_SIZE, "wdt%d", i);
+ object_property_add_child(obj, name, OBJECT(&s->wdt[i]),
+ &error_fatal);
+ }
+
+ /*
+ * SDMA
+ */
+ object_initialize(&s->sdma, sizeof(s->sdma), TYPE_IMX_SDMA);
+ qdev_set_parent_bus(DEVICE(&s->sdma), sysbus);
+ object_property_add_child(obj, "sdma", OBJECT(&s->sdma), &error_fatal);
+
+ /*
+ * GPR
+ */
+ object_initialize(&s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR);
+ qdev_set_parent_bus(DEVICE(&s->gpr), sysbus);
+ object_property_add_child(obj, "gpr", OBJECT(&s->gpr), &error_fatal);
+
+ object_initialize(&s->pcie, sizeof(s->pcie), TYPE_DESIGNWARE_PCIE_HOST);
+ qdev_set_parent_bus(DEVICE(&s->pcie), sysbus);
+ object_property_add_child(obj, "pcie", OBJECT(&s->pcie), &error_fatal);
+
+ for (i = 0; i < FSL_IMX7_NUM_USBMISCS; i++) {
+ object_initialize(&s->usbmisc[i],
+ sizeof(s->usbmisc[i]), TYPE_IMX_USBMISC);
+ qdev_set_parent_bus(DEVICE(&s->usbmisc[i]), sysbus);
+ snprintf(name, NAME_SIZE, "usbmisc%d", i);
+ object_property_add_child(obj, name,
+ OBJECT(&s->usbmisc[i]), &error_fatal);
+ }
+
+ for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
+ object_initialize(&s->adc[i], sizeof(s->adc[i]), TYPE_IMX7_ADC);
+ qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus);
+ snprintf(name, NAME_SIZE, "adc%d", i);
+ object_property_add_child(obj, name,
+ OBJECT(&s->adc[i]), &error_fatal);
+ }
+}
+
+static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+{
+ FslIMX7State *s = FSL_IMX7(dev);
+ Object *o;
+ int i;
+ qemu_irq irq;
+
+ for (i = 0; i < smp_cpus; i++) {
+ o = OBJECT(&s->cpu[i]);
+
+ object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
+ "psci-conduit", &error_abort);
+
+ /* On uniprocessor, the CBAR is set to 0 */
+ if (smp_cpus > 1) {
+ object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR,
+ "reset-cbar", &error_abort);
+ }
+
+ if (i) {
+ /* Secondary CPUs start in PSCI powered-down state */
+ object_property_set_bool(o, true,
+ "start-powered-off", &error_abort);
+ }
+
+ object_property_set_bool(o, true, "realized", &error_abort);
+ }
+
+ /*
+ * A7MPCORE
+ */
+ object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
+ &error_abort);
+ object_property_set_int(OBJECT(&s->a7mpcore),
+ FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
+ "num-irq", &error_abort);
+
+ object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
+
+ for (i = 0; i < smp_cpus; i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
+ DeviceState *d = DEVICE(qemu_get_cpu(i));
+
+ irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
+ sysbus_connect_irq(sbd, i, irq);
+ irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
+ sysbus_connect_irq(sbd, i + smp_cpus, irq);
+ }
+
+
+ /*
+ * GPT1, 2, 3, 4
+ */
+ for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+ static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
+ FSL_IMX7_GPT1_ADDR,
+ FSL_IMX7_GPT2_ADDR,
+ FSL_IMX7_GPT3_ADDR,
+ FSL_IMX7_GPT4_ADDR,
+ };
+
+ s->gpt[i].ccm = IMX_CCM(&s->ccm);
+ object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
+ }
+
+ for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+ static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
+ FSL_IMX7_GPIO1_ADDR,
+ FSL_IMX7_GPIO2_ADDR,
+ FSL_IMX7_GPIO3_ADDR,
+ FSL_IMX7_GPIO4_ADDR,
+ FSL_IMX7_GPIO5_ADDR,
+ FSL_IMX7_GPIO6_ADDR,
+ FSL_IMX7_GPIO7_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
+ }
+
+ /*
+ * IOMUXC and IOMUXC_LPSR
+ */
+ for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
+ static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
+ FSL_IMX7_IOMUXC_ADDR,
+ FSL_IMX7_IOMUXC_LPSR_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->iomuxc[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->iomuxc[i]), 0,
+ FSL_IMX7_IOMUXCn_ADDR[i]);
+ }
+
+ /*
+ * CCM
+ */
+ object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
+
+ /*
+ * GPCv2
+ */
+ object_property_set_bool(OBJECT(&s->gpcv2), true,
+ "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
+
+ /* Initialize all ECSPI */
+ for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+ static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
+ FSL_IMX7_ECSPI1_ADDR,
+ FSL_IMX7_ECSPI2_ADDR,
+ FSL_IMX7_ECSPI3_ADDR,
+ FSL_IMX7_ECSPI4_ADDR,
+ };
+
+ static const hwaddr FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
+ FSL_IMX7_ECSPI1_IRQ,
+ FSL_IMX7_ECSPI2_IRQ,
+ FSL_IMX7_ECSPI3_IRQ,
+ FSL_IMX7_ECSPI4_IRQ,
+ };
+
+ /* Initialize the SPI */
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ FSL_IMX7_SPIn_ADDR[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX7_SPIn_IRQ[i]));
+ }
+
+ for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+ static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
+ FSL_IMX7_I2C1_ADDR,
+ FSL_IMX7_I2C2_ADDR,
+ FSL_IMX7_I2C3_ADDR,
+ FSL_IMX7_I2C4_ADDR,
+ };
+
+ static const hwaddr FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
+ FSL_IMX7_I2C1_IRQ,
+ FSL_IMX7_I2C2_IRQ,
+ FSL_IMX7_I2C3_IRQ,
+ FSL_IMX7_I2C4_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX7_I2Cn_IRQ[i]));
+ }
+
+ /*
+ * UART
+ */
+ for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+ static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
+ FSL_IMX7_UART1_ADDR,
+ FSL_IMX7_UART2_ADDR,
+ FSL_IMX7_UART3_ADDR,
+ FSL_IMX7_UART4_ADDR,
+ FSL_IMX7_UART5_ADDR,
+ FSL_IMX7_UART6_ADDR,
+ FSL_IMX7_UART7_ADDR,
+ };
+
+ static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
+ FSL_IMX7_UART1_IRQ,
+ FSL_IMX7_UART2_IRQ,
+ FSL_IMX7_UART3_IRQ,
+ FSL_IMX7_UART4_IRQ,
+ FSL_IMX7_UART5_IRQ,
+ FSL_IMX7_UART6_IRQ,
+ FSL_IMX7_UART7_IRQ,
+ };
+
+
+ if (i < MAX_SERIAL_PORTS) {
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
+ }
+
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
+ }
+
+ for (i = 0; i < FSL_IMX7_NUM_FLEXCANS; i++) {
+ static const hwaddr FSL_IMX7_FLEXCANn_ADDR[FSL_IMX7_NUM_FLEXCANS] = {
+ FSL_IMX7_FLEXCAN1_ADDR,
+ FSL_IMX7_FLEXCAN2_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->flexcan[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->flexcan[i]), 0,
+ FSL_IMX7_FLEXCANn_ADDR[i]);
+ }
+
+ /*
+ * Ethernet
+ */
+ for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
+ static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
+ FSL_IMX7_ENET1_ADDR,
+ FSL_IMX7_ENET2_ADDR,
+ };
+
+ object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
+ "tx-ring-num", &error_abort);
+ qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
+ object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
+ }
+
+ /*
+ * USDHC
+ */
+ for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+ static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
+ FSL_IMX7_USDHC1_ADDR,
+ FSL_IMX7_USDHC2_ADDR,
+ FSL_IMX7_USDHC3_ADDR,
+ };
+
+ static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
+ FSL_IMX7_USDHC1_IRQ,
+ FSL_IMX7_USDHC2_IRQ,
+ FSL_IMX7_USDHC3_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
+ FSL_IMX7_USDHCn_ADDR[i]);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
+ }
+
+ /*
+ * SNVS
+ */
+ object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
+
+ /*
+ * SRC
+ */
+ object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
+
+ /*
+ * Watchdog
+ */
+ for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+ static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
+ FSL_IMX7_WDOG1_ADDR,
+ FSL_IMX7_WDOG2_ADDR,
+ FSL_IMX7_WDOG3_ADDR,
+ FSL_IMX7_WDOG4_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
+ }
+
+ /*
+ * SDMA
+ */
+ object_property_set_bool(OBJECT(&s->sdma), true, "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdma), 0, FSL_IMX7_SDMA_ADDR);
+
+ object_property_set_bool(OBJECT(&s->gpr), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
+
+ object_property_set_bool(OBJECT(&s->pcie), true,
+ "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+
+
+ for (i = 0; i < FSL_IMX7_NUM_USBMISCS; i++) {
+ static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBMISCS] = {
+ FSL_IMX7_USBMISC1_ADDR,
+ FSL_IMX7_USBMISC2_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->usbmisc[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbmisc[i]), 0,
+ FSL_IMX7_USBMISCn_ADDR[i]);
+ }
+
+ for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
+ static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
+ FSL_IMX7_ADC1_ADDR,
+ FSL_IMX7_ADC2_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->adc[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc[i]), 0,
+ FSL_IMX7_ADCn_ADDR[i]);
+ }
+}
+
+static void fsl_imx7_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = fsl_imx7_realize;
+
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
+ dc->user_creatable = false;
+ dc->desc = "i.MX7 SOC";
+}
+
+static const TypeInfo fsl_imx7_type_info = {
+ .name = TYPE_FSL_IMX7,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(FslIMX7State),
+ .instance_init = fsl_imx7_init,
+ .class_init = fsl_imx7_class_init,
+};
+
+static void fsl_imx7_register_types(void)
+{
+ type_register_static(&fsl_imx7_type_info);
+}
+type_init(fsl_imx7_register_types)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
new file mode 100644
index 0000000000..24c9cc2e46
--- /dev/null
+++ b/include/hw/arm/fsl-imx7.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ *
+ * i.MX7 SoC definitions
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef FSL_IMX7_H
+#define FSL_IMX7_H
+
+#include "hw/arm/arm.h"
+#include "hw/cpu/a15mpcore.h"
+#include "hw/intc/imx_gpcv2.h"
+#include "hw/misc/imx7_ccm.h"
+#include "hw/misc/imx7_snvs.h"
+#include "hw/misc/imx7_iomuxc.h"
+#include "hw/misc/imx7_adc.h"
+#include "hw/misc/imx_flexcan.h"
+#include "hw/misc/imx7_gpr.h"
+#include "hw/misc/imx7_src.h"
+#include "hw/misc/imx6_src.h"
+#include "hw/misc/imx2_wdt.h"
+#include "hw/gpio/imx_gpio.h"
+#include "hw/char/imx_serial.h"
+#include "hw/timer/imx_gpt.h"
+#include "hw/timer/imx_epit.h"
+#include "hw/i2c/imx_i2c.h"
+#include "hw/gpio/imx_gpio.h"
+#include "hw/dma/imx_sdma.h"
+#include "hw/sd/sdhci.h"
+#include "hw/usb/imx-usbmisc.h"
+#include "hw/ssi/imx_spi.h"
+#include "hw/net/imx_fec.h"
+#include "hw/pci-host/designware.h"
+#include "exec/memory.h"
+#include "cpu.h"
+
+#define TYPE_FSL_IMX7 "fsl,imx7"
+#define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7)
+
+enum FslIMX7Configuration {
+ FSL_IMX7_NUM_CPUS = 2,
+ FSL_IMX7_NUM_UARTS = 7,
+ FSL_IMX7_NUM_ETHS = 2,
+ FSL_IMX7_ETH_NUM_TX_RINGS = 3,
+ FSL_IMX7_NUM_USDHCS = 3,
+ FSL_IMX7_NUM_WDTS = 4,
+ FSL_IMX7_NUM_GPTS = 4,
+ FSL_IMX7_NUM_IOMUXCS = 2,
+ FSL_IMX7_NUM_GPIOS = 7,
+ FSL_IMX7_NUM_I2CS = 4,
+ FSL_IMX7_NUM_ECSPIS = 4,
+ FSL_IMX7_NUM_FLEXCANS = 2,
+ FSL_IMX7_NUM_USBMISCS = 2,
+ FSL_IMX7_NUM_ADCS = 2,
+};
+
+typedef struct FslIMX7State {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ ARMCPU cpu[FSL_IMX7_NUM_CPUS];
+ A15MPPrivState a7mpcore;
+ IMXGPTState gpt[FSL_IMX7_NUM_GPTS];
+ IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS];
+ IMX7IOMUXCState iomuxc[FSL_IMX7_NUM_IOMUXCS];
+ IMX7CCMState ccm;
+ IMX7SNVSState snvs;
+ IMX7SRCState src;
+ IMXGPCv2State gpcv2;
+ IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
+ IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
+ IMXSerialState uart[FSL_IMX7_NUM_UARTS];
+ IMXFlexCANState flexcan[FSL_IMX7_NUM_FLEXCANS];
+ IMXFECState eth[FSL_IMX7_NUM_ETHS];
+ SDHCIState usdhc[FSL_IMX7_NUM_USDHCS];
+ IMX2WdtState wdt[FSL_IMX7_NUM_WDTS];
+ IMXSDMAState sdma;
+ IMX7GPRState gpr;
+ IMXUSBMiscState usbmisc[FSL_IMX7_NUM_USBMISCS];
+ IMX7ADCState adc[FSL_IMX7_NUM_ADCS];
+
+ DesignwarePCIEHost pcie;
+} FslIMX7State;
+
+enum FslIMX7MemoryMap {
+ FSL_IMX7_MMDC_ADDR = 0x80000000,
+ FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
+
+ FSL_IMX7_GPIO1_ADDR = 0x30200000,
+ FSL_IMX7_GPIO2_ADDR = 0x30210000,
+ FSL_IMX7_GPIO3_ADDR = 0x30220000,
+ FSL_IMX7_GPIO4_ADDR = 0x30230000,
+ FSL_IMX7_GPIO5_ADDR = 0x30240000,
+ FSL_IMX7_GPIO6_ADDR = 0x30250000,
+ FSL_IMX7_GPIO7_ADDR = 0x30260000,
+
+ FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+
+ FSL_IMX7_WDOG1_ADDR = 0x30280000,
+ FSL_IMX7_WDOG2_ADDR = 0x30290000,
+ FSL_IMX7_WDOG3_ADDR = 0x302A0000,
+ FSL_IMX7_WDOG4_ADDR = 0x302B0000,
+
+ FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
+
+ FSL_IMX7_GPT1_ADDR = 0x302D0000,
+ FSL_IMX7_GPT2_ADDR = 0x302E0000,
+ FSL_IMX7_GPT3_ADDR = 0x302F0000,
+ FSL_IMX7_GPT4_ADDR = 0x30300000,
+
+ FSL_IMX7_IOMUXC_ADDR = 0x30330000,
+ FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
+
+ FSL_IMX7_CCM_ADDR = 0x30360000,
+ FSL_IMX7_SNVS_ADDR = 0x30370000,
+
+ FSL_IMX7_SRC_ADDR = 0x30390000,
+
+ FSL_IMX7_ADC1_ADDR = 0x30610000,
+ FSL_IMX7_ADC2_ADDR = 0x30620000,
+
+ FSL_IMX7_GPC_ADDR = 0x303A0000,
+
+ FSL_IMX7_I2C1_ADDR = 0x30A20000,
+ FSL_IMX7_I2C2_ADDR = 0x30A30000,
+ FSL_IMX7_I2C3_ADDR = 0x30A40000,
+ FSL_IMX7_I2C4_ADDR = 0x30A50000,
+
+ FSL_IMX7_ECSPI1_ADDR = 0x30820000,
+ FSL_IMX7_ECSPI2_ADDR = 0x30830000,
+ FSL_IMX7_ECSPI3_ADDR = 0x30840000,
+ FSL_IMX7_ECSPI4_ADDR = 0x30630000,
+
+ FSL_IMX7_UART1_ADDR = 0x30860000,
+ /*
+ * Some versions of the reference manual claim that UART2 is @
+ * 0x30870000, but experiments with HW + DT files in upstream
+ * Linux kernel show that not to be true and that block is
+ * acutally located @ 0x30890000
+ */
+ FSL_IMX7_UART2_ADDR = 0x30890000,
+ FSL_IMX7_UART3_ADDR = 0x30880000,
+ FSL_IMX7_UART4_ADDR = 0x30A60000,
+ FSL_IMX7_UART5_ADDR = 0x30A70000,
+ FSL_IMX7_UART6_ADDR = 0x30A80000,
+ FSL_IMX7_UART7_ADDR = 0x30A90000,
+
+ FSL_IMX7_FLEXCAN1_ADDR = 0x30A00000,
+ FSL_IMX7_FLEXCAN2_ADDR = 0x30A10000,
+
+ FSL_IMX7_ENET1_ADDR = 0x30BE0000,
+ FSL_IMX7_ENET2_ADDR = 0x30BF0000,
+
+ FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
+ FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
+
+ FSL_IMX7_USDHC1_ADDR = 0x30B40000,
+ FSL_IMX7_USDHC2_ADDR = 0x30B50000,
+ FSL_IMX7_USDHC3_ADDR = 0x30B60000,
+
+ FSL_IMX7_SDMA_ADDR = 0x30BD0000,
+
+ FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
+
+ FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
+ FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
+
+ FSL_IMX7_GPR_ADDR = 0x30340000,
+};
+
+enum FslIMX7IRQs {
+ FSL_IMX7_USDHC1_IRQ = 22,
+ FSL_IMX7_USDHC2_IRQ = 23,
+ FSL_IMX7_USDHC3_IRQ = 24,
+
+ FSL_IMX7_UART1_IRQ = 26,
+ FSL_IMX7_UART2_IRQ = 27,
+ FSL_IMX7_UART3_IRQ = 28,
+ FSL_IMX7_UART4_IRQ = 29,
+ FSL_IMX7_UART5_IRQ = 30,
+ FSL_IMX7_UART6_IRQ = 16,
+
+ FSL_IMX7_ECSPI1_IRQ = 31,
+ FSL_IMX7_ECSPI2_IRQ = 32,
+ FSL_IMX7_ECSPI3_IRQ = 33,
+ FSL_IMX7_ECSPI4_IRQ = 34,
+
+ FSL_IMX7_I2C1_IRQ = 35,
+ FSL_IMX7_I2C2_IRQ = 36,
+ FSL_IMX7_I2C3_IRQ = 37,
+ FSL_IMX7_I2C4_IRQ = 38,
+
+ FSL_IMX7_PCI_INTA_IRQ = 122,
+ FSL_IMX7_PCI_INTB_IRQ = 123,
+ FSL_IMX7_PCI_INTC_IRQ = 124,
+ FSL_IMX7_PCI_INTD_IRQ = 125,
+
+ FSL_IMX7_UART7_IRQ = 126,
+
+#define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118))
+
+ FSL_IMX7_MAX_IRQ = 128,
+};
+
+#endif /* FSL_IMX7_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
end of thread, other threads:[~2017-10-23 20:11 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-23 20:10 [Qemu-devel] [PATCH v2 00/27] Initial i.MX7 support Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 01/27] imx_fec: Do not link to netdev Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 02/27] imx_fec: Refactor imx_eth_enable_rx() Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 03/27] imx_fec: Change queue flushing heuristics Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 04/27] imx_fec: Use ENET_FTRL to determine truncation length Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 05/27] imx_fec: Use MIN instead of explicit ternary operator Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 06/27] imx_fec: Emulate SHIFT16 in ENETx_RACC Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 07/27] imx_fec: Add support for multiple Tx DMA rings Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 08/27] imx_fec: Use correct length for packet size Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 09/27] imx_fec: Fix a typo in imx_enet_receive() Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 10/27] imx_fec: Reserve full 4K page for the register file Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 11/27] sdhci: Add i.MX specific subtype of SDHCI Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 12/27] sdhci: Implement write method of ACMD12ERRSTS register Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 13/27] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 14/27] i.MX: Add code to emulate i.MX2 watchdog IP block Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 15/27] i.MX: Add code to emulate i.MX7 SNVS IP-block Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 16/27] i.MX: Add code to emulate GPCv2 IP block Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 17/27] i.MX: Add code to emulate i.MX7 IOMUXC " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 19/27] i.MX: Add code to emulate SDMA " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 20/27] i.MX: Add code to emulate FlexCAN " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 21/27] i.MX: Add implementation of i.MX7 GPR " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 22/27] pci: Add support for Designware " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 23/27] i.MX: Add code to emulate i.MX7 USBMISC " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 24/27] i.MX: Add code to emulate i.MX7 ADC " Andrey Smirnov
2017-10-23 20:10 ` [Qemu-devel] [PATCH v2 26/27] i.MX: Add i.MX7 SOC implementation Andrey Smirnov
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.