* [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info
@ 2017-10-24 10:10 Sagar Arun Kamble
2017-10-24 10:16 ` Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Sagar Arun Kamble @ 2017-10-24 10:10 UTC (permalink / raw)
To: intel-gfx
PM interrupt register offsets are constant per platforms and saving those
in device info is more appropriate than getting those through functions.
This patch removes functions gen6_pm_iir/imr/ier and saves those offsets
in device info.
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++++
drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++----------------------
drivers/gpu/drm/i915/intel_device_info.c | 11 +++++++++++
3 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54b5d4c..2f77d26 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -888,6 +888,11 @@ struct intel_device_info {
u16 degamma_lut_size;
u16 gamma_lut_size;
} color;
+
+ /* PM interrupt register offsets */
+ i915_reg_t pm_iir_offset;
+ i915_reg_t pm_imr_offset;
+ i915_reg_t pm_ier_offset;
};
struct intel_display_error_state;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1296a5..68c6f44 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -306,21 +306,6 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
ilk_update_gt_irq(dev_priv, mask, 0);
}
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
-{
- return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
-}
-
-static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
-{
- return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
-}
-
-static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
-{
- return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
-}
-
/**
* snb_update_pm_irq - update GEN6_PMIMR
* @dev_priv: driver private
@@ -343,8 +328,8 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
if (new_val != dev_priv->pm_imr) {
dev_priv->pm_imr = new_val;
- I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
- POSTING_READ(gen6_pm_imr(dev_priv));
+ I915_WRITE(dev_priv->info.pm_imr_offset, dev_priv->pm_imr);
+ POSTING_READ(dev_priv->info.pm_imr_offset);
}
}
@@ -371,7 +356,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
{
- i915_reg_t reg = gen6_pm_iir(dev_priv);
+ i915_reg_t reg = dev_priv->info.pm_iir_offset;
lockdep_assert_held(&dev_priv->irq_lock);
@@ -385,7 +370,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
lockdep_assert_held(&dev_priv->irq_lock);
dev_priv->pm_ier |= enable_mask;
- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+ I915_WRITE(dev_priv->info.pm_ier_offset, dev_priv->pm_ier);
gen6_unmask_pm_irq(dev_priv, enable_mask);
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
}
@@ -396,7 +381,7 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
dev_priv->pm_ier &= ~disable_mask;
__gen6_mask_pm_irq(dev_priv, disable_mask);
- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
+ I915_WRITE(dev_priv->info.pm_ier_offset, dev_priv->pm_ier);
/* though a barrier is missing here, but don't really need a one */
}
@@ -417,7 +402,8 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
spin_lock_irq(&dev_priv->irq_lock);
WARN_ON_ONCE(rps->pm_iir);
- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
+ WARN_ON_ONCE(I915_READ(dev_priv->info.pm_iir_offset) &
+ dev_priv->pm_rps_events);
rps->interrupts_enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
@@ -461,7 +447,7 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {
- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+ WARN_ON_ONCE(I915_READ(dev_priv->info.pm_iir_offset) &
dev_priv->pm_guc_events);
dev_priv->guc.interrupts_enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 875d428..d1a4911 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -462,4 +462,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->sseu.has_subslice_pg ? "y" : "n");
DRM_DEBUG_DRIVER("has EU power gating: %s\n",
info->sseu.has_eu_pg ? "y" : "n");
+
+ /* Initialize PM interrupt register offsets */
+ if (INTEL_GEN(dev_priv) >= 8) {
+ info->pm_iir_offset = GEN8_GT_IIR(2);
+ info->pm_imr_offset = GEN8_GT_IMR(2);
+ info->pm_ier_offset = GEN8_GT_IER(2);
+ } else {
+ info->pm_iir_offset = GEN6_PMIIR;
+ info->pm_imr_offset = GEN6_PMIMR;
+ info->pm_ier_offset = GEN6_PMIER;
+ }
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info
2017-10-24 10:10 [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info Sagar Arun Kamble
@ 2017-10-24 10:16 ` Chris Wilson
2017-10-24 11:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/1] " Patchwork
2017-10-24 17:42 ` [PATCH 1/1] " Jani Nikula
2 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2017-10-24 10:16 UTC (permalink / raw)
To: Sagar Arun Kamble, intel-gfx
Quoting Sagar Arun Kamble (2017-10-24 11:10:50)
> PM interrupt register offsets are constant per platforms and saving those
> in device info is more appropriate than getting those through functions.
> This patch removes functions gen6_pm_iir/imr/ier and saves those offsets
> in device info.
>
> Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
What direction are we taking on INTEL_INFO() vs i915->info?
INTEL_INFO still offers the bait-n-switch promise of single-gen
compilation...
-Chris
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/1] drm/i915: Save PM interrupt register offsets in device info
2017-10-24 10:10 [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info Sagar Arun Kamble
2017-10-24 10:16 ` Chris Wilson
@ 2017-10-24 11:30 ` Patchwork
2017-10-24 17:42 ` [PATCH 1/1] " Jani Nikula
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-10-24 11:30 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/1] drm/i915: Save PM interrupt register offsets in device info
URL : https://patchwork.freedesktop.org/series/32524/
State : failure
== Summary ==
Series 32524v1 series starting with [1/1] drm/i915: Save PM interrupt register offsets in device info
https://patchwork.freedesktop.org/api/1.0/series/32524/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
pass -> INCOMPLETE (fi-skl-6700hq)
Test drv_module_reload:
Subgroup basic-reload-inject:
pass -> INCOMPLETE (fi-bwr-2160)
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:455s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:516s
fi-bwr-2160 total:288 pass:182 dwarn:0 dfail:0 fail:0 skip:105
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:495s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:495s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:489s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:477s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:551s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:420s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:249s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:575s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:488s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:435s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:497s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:460s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:494s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:572s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:478s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:580s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:552s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:443s
fi-skl-6700hq total:232 pass:207 dwarn:0 dfail:0 fail:0 skip:24
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:516s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:501s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:459s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:556s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:415s
5c82a37eff83ab4e60e760fbaf03db5ba0563497 drm-tip: 2017y-10m-23d-18h-06m-28s UTC integration manifest
41730da16e6e drm/i915: Save PM interrupt register offsets in device info
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6154/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info
2017-10-24 10:10 [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info Sagar Arun Kamble
2017-10-24 10:16 ` Chris Wilson
2017-10-24 11:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/1] " Patchwork
@ 2017-10-24 17:42 ` Jani Nikula
2017-10-24 17:55 ` Ville Syrjälä
2 siblings, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2017-10-24 17:42 UTC (permalink / raw)
To: Sagar Arun Kamble, intel-gfx
On Tue, 24 Oct 2017, Sagar Arun Kamble <sagar.a.kamble@intel.com> wrote:
> PM interrupt register offsets are constant per platforms and saving those
> in device info is more appropriate than getting those through functions.
> This patch removes functions gen6_pm_iir/imr/ier and saves those offsets
> in device info.
Do we *really* want to start on this path? We have the *_offsets in
device info for some groups of registers, but this is a whole another
ballgame. You could make the same argument for half the registers in
i915_reg.h!
If you don't want to use a function to get the correct
register... almost all of the rest of the driver uses if-else in code
for this...
The issue is not this single patch per se. The issue is the precedence
it sets, and the apparent lack of thought on where we'll end up with
this.
BR,
Jani.
>
> Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++++
> drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++----------------------
> drivers/gpu/drm/i915/intel_device_info.c | 11 +++++++++++
> 3 files changed, 24 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 54b5d4c..2f77d26 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -888,6 +888,11 @@ struct intel_device_info {
> u16 degamma_lut_size;
> u16 gamma_lut_size;
> } color;
> +
> + /* PM interrupt register offsets */
> + i915_reg_t pm_iir_offset;
> + i915_reg_t pm_imr_offset;
> + i915_reg_t pm_ier_offset;
> };
>
> struct intel_display_error_state;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b1296a5..68c6f44 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -306,21 +306,6 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
> ilk_update_gt_irq(dev_priv, mask, 0);
> }
>
> -static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
> -{
> - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> -}
> -
> -static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
> -{
> - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
> -}
> -
> -static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
> -{
> - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
> -}
> -
> /**
> * snb_update_pm_irq - update GEN6_PMIMR
> * @dev_priv: driver private
> @@ -343,8 +328,8 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
>
> if (new_val != dev_priv->pm_imr) {
> dev_priv->pm_imr = new_val;
> - I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
> - POSTING_READ(gen6_pm_imr(dev_priv));
> + I915_WRITE(dev_priv->info.pm_imr_offset, dev_priv->pm_imr);
> + POSTING_READ(dev_priv->info.pm_imr_offset);
> }
> }
>
> @@ -371,7 +356,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
>
> static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
> {
> - i915_reg_t reg = gen6_pm_iir(dev_priv);
> + i915_reg_t reg = dev_priv->info.pm_iir_offset;
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -385,7 +370,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
> lockdep_assert_held(&dev_priv->irq_lock);
>
> dev_priv->pm_ier |= enable_mask;
> - I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
> + I915_WRITE(dev_priv->info.pm_ier_offset, dev_priv->pm_ier);
> gen6_unmask_pm_irq(dev_priv, enable_mask);
> /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
> }
> @@ -396,7 +381,7 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
>
> dev_priv->pm_ier &= ~disable_mask;
> __gen6_mask_pm_irq(dev_priv, disable_mask);
> - I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
> + I915_WRITE(dev_priv->info.pm_ier_offset, dev_priv->pm_ier);
> /* though a barrier is missing here, but don't really need a one */
> }
>
> @@ -417,7 +402,8 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
>
> spin_lock_irq(&dev_priv->irq_lock);
> WARN_ON_ONCE(rps->pm_iir);
> - WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> + WARN_ON_ONCE(I915_READ(dev_priv->info.pm_iir_offset) &
> + dev_priv->pm_rps_events);
> rps->interrupts_enabled = true;
> gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
>
> @@ -461,7 +447,7 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> {
> spin_lock_irq(&dev_priv->irq_lock);
> if (!dev_priv->guc.interrupts_enabled) {
> - WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
> + WARN_ON_ONCE(I915_READ(dev_priv->info.pm_iir_offset) &
> dev_priv->pm_guc_events);
> dev_priv->guc.interrupts_enabled = true;
> gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 875d428..d1a4911 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -462,4 +462,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> info->sseu.has_subslice_pg ? "y" : "n");
> DRM_DEBUG_DRIVER("has EU power gating: %s\n",
> info->sseu.has_eu_pg ? "y" : "n");
> +
> + /* Initialize PM interrupt register offsets */
> + if (INTEL_GEN(dev_priv) >= 8) {
> + info->pm_iir_offset = GEN8_GT_IIR(2);
> + info->pm_imr_offset = GEN8_GT_IMR(2);
> + info->pm_ier_offset = GEN8_GT_IER(2);
> + } else {
> + info->pm_iir_offset = GEN6_PMIIR;
> + info->pm_imr_offset = GEN6_PMIMR;
> + info->pm_ier_offset = GEN6_PMIER;
> + }
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info
2017-10-24 17:42 ` [PATCH 1/1] " Jani Nikula
@ 2017-10-24 17:55 ` Ville Syrjälä
0 siblings, 0 replies; 5+ messages in thread
From: Ville Syrjälä @ 2017-10-24 17:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 24, 2017 at 08:42:41PM +0300, Jani Nikula wrote:
> On Tue, 24 Oct 2017, Sagar Arun Kamble <sagar.a.kamble@intel.com> wrote:
> > PM interrupt register offsets are constant per platforms and saving those
> > in device info is more appropriate than getting those through functions.
> > This patch removes functions gen6_pm_iir/imr/ier and saves those offsets
> > in device info.
>
> Do we *really* want to start on this path? We have the *_offsets in
> device info for some groups of registers, but this is a whole another
> ballgame. You could make the same argument for half the registers in
> i915_reg.h!
>
> If you don't want to use a function to get the correct
> register... almost all of the rest of the driver uses if-else in code
> for this...
>
> The issue is not this single patch per se. The issue is the precedence
> it sets, and the apparent lack of thought on where we'll end up with
> this.
I definitely think we shouldn't do this for individual registers. I even
removed some _offsets[] arrays in the past because they were effectively
covering just one or two registers, and thus didn't seem justified.
In this case we could actually make do with a single offset that would
cover the four interrupt registers. So it's maybe on the edge of what
seems sensible to me.
>
>
> BR,
> Jani.
>
> >
> > Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 5 +++++
> > drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++----------------------
> > drivers/gpu/drm/i915/intel_device_info.c | 11 +++++++++++
> > 3 files changed, 24 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 54b5d4c..2f77d26 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -888,6 +888,11 @@ struct intel_device_info {
> > u16 degamma_lut_size;
> > u16 gamma_lut_size;
> > } color;
> > +
> > + /* PM interrupt register offsets */
> > + i915_reg_t pm_iir_offset;
> > + i915_reg_t pm_imr_offset;
> > + i915_reg_t pm_ier_offset;
> > };
> >
> > struct intel_display_error_state;
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index b1296a5..68c6f44 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -306,21 +306,6 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
> > ilk_update_gt_irq(dev_priv, mask, 0);
> > }
> >
> > -static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
> > -{
> > - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> > -}
> > -
> > -static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
> > -{
> > - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
> > -}
> > -
> > -static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
> > -{
> > - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
> > -}
> > -
> > /**
> > * snb_update_pm_irq - update GEN6_PMIMR
> > * @dev_priv: driver private
> > @@ -343,8 +328,8 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
> >
> > if (new_val != dev_priv->pm_imr) {
> > dev_priv->pm_imr = new_val;
> > - I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
> > - POSTING_READ(gen6_pm_imr(dev_priv));
> > + I915_WRITE(dev_priv->info.pm_imr_offset, dev_priv->pm_imr);
> > + POSTING_READ(dev_priv->info.pm_imr_offset);
> > }
> > }
> >
> > @@ -371,7 +356,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
> >
> > static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
> > {
> > - i915_reg_t reg = gen6_pm_iir(dev_priv);
> > + i915_reg_t reg = dev_priv->info.pm_iir_offset;
> >
> > lockdep_assert_held(&dev_priv->irq_lock);
> >
> > @@ -385,7 +370,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
> > lockdep_assert_held(&dev_priv->irq_lock);
> >
> > dev_priv->pm_ier |= enable_mask;
> > - I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
> > + I915_WRITE(dev_priv->info.pm_ier_offset, dev_priv->pm_ier);
> > gen6_unmask_pm_irq(dev_priv, enable_mask);
> > /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
> > }
> > @@ -396,7 +381,7 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
> >
> > dev_priv->pm_ier &= ~disable_mask;
> > __gen6_mask_pm_irq(dev_priv, disable_mask);
> > - I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
> > + I915_WRITE(dev_priv->info.pm_ier_offset, dev_priv->pm_ier);
> > /* though a barrier is missing here, but don't really need a one */
> > }
> >
> > @@ -417,7 +402,8 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
> >
> > spin_lock_irq(&dev_priv->irq_lock);
> > WARN_ON_ONCE(rps->pm_iir);
> > - WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> > + WARN_ON_ONCE(I915_READ(dev_priv->info.pm_iir_offset) &
> > + dev_priv->pm_rps_events);
> > rps->interrupts_enabled = true;
> > gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
> >
> > @@ -461,7 +447,7 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> > {
> > spin_lock_irq(&dev_priv->irq_lock);
> > if (!dev_priv->guc.interrupts_enabled) {
> > - WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
> > + WARN_ON_ONCE(I915_READ(dev_priv->info.pm_iir_offset) &
> > dev_priv->pm_guc_events);
> > dev_priv->guc.interrupts_enabled = true;
> > gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 875d428..d1a4911 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -462,4 +462,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> > info->sseu.has_subslice_pg ? "y" : "n");
> > DRM_DEBUG_DRIVER("has EU power gating: %s\n",
> > info->sseu.has_eu_pg ? "y" : "n");
> > +
> > + /* Initialize PM interrupt register offsets */
> > + if (INTEL_GEN(dev_priv) >= 8) {
> > + info->pm_iir_offset = GEN8_GT_IIR(2);
> > + info->pm_imr_offset = GEN8_GT_IMR(2);
> > + info->pm_ier_offset = GEN8_GT_IER(2);
> > + } else {
> > + info->pm_iir_offset = GEN6_PMIIR;
> > + info->pm_imr_offset = GEN6_PMIMR;
> > + info->pm_ier_offset = GEN6_PMIER;
> > + }
> > }
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-10-24 17:56 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-24 10:10 [PATCH 1/1] drm/i915: Save PM interrupt register offsets in device info Sagar Arun Kamble
2017-10-24 10:16 ` Chris Wilson
2017-10-24 11:30 ` ✗ Fi.CI.BAT: failure for series starting with [1/1] " Patchwork
2017-10-24 17:42 ` [PATCH 1/1] " Jani Nikula
2017-10-24 17:55 ` Ville Syrjälä
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