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* [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST
@ 2017-10-27 13:43 Ville Syrjala
  2017-10-27 13:53 ` Ville Syrjälä
                   ` (7 more replies)
  0 siblings, 8 replies; 9+ messages in thread
From: Ville Syrjala @ 2017-10-27 13:43 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
the correct lane latency optimal setting applied. And we obviously need
to compute the correct value, and read it out to keep the state checker
happy.

While at it drop the useless 'encoder' parameter to
bxt_ddi_phy_calc_lane_lat_optim_mask()

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  3 +--
 drivers/gpu/drm/i915/intel_ddi.c      |  3 +--
 drivers/gpu/drm/i915/intel_dp_mst.c   | 23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dpio_phy.c |  3 +--
 4 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 366ba74b0ad2..de32576b2540 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4177,8 +4177,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 			    enum dpio_phy phy);
 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 			      enum dpio_phy phy);
-uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
-					     uint8_t lane_count);
+uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 				     uint8_t lane_lat_optim_mask);
 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 28c25cb9eb2c..d4b336cffe68 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2673,8 +2673,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
 
 	if (IS_GEN9_LP(dev_priv) && ret)
 		pipe_config->lane_lat_optim_mask =
-			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
-							     pipe_config->lane_count);
+			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 3d62c63c0763..c34ffa959e90 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -88,6 +88,10 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
 	pipe_config->dp_m_n.tu = slots;
 
+	if (IS_GEN9_LP(dev_priv))
+		pipe_config->lane_lat_optim_mask =
+			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
+
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
 	return true;
@@ -182,6 +186,20 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 }
 
+static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
+					const struct intel_crtc_state *pipe_config,
+					const struct drm_connector_state *conn_state)
+{
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
+	struct intel_digital_port *intel_dig_port = intel_mst->primary;
+	struct intel_dp *intel_dp = &intel_dig_port->dp;
+
+	if (intel_dp->active_mst_links == 0 &&
+	    intel_dig_port->base.pre_pll_enable)
+		intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
+						    pipe_config, NULL);
+}
+
 static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *pipe_config,
 				    const struct drm_connector_state *conn_state)
@@ -311,6 +329,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 
 	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
 
+	if (IS_GEN9_LP(dev_priv))
+		pipe_config->lane_lat_optim_mask =
+			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
+
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 }
 
@@ -582,6 +604,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
 	intel_encoder->compute_config = intel_dp_mst_compute_config;
 	intel_encoder->disable = intel_mst_disable_dp;
 	intel_encoder->post_disable = intel_mst_post_disable_dp;
+	intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
 	intel_encoder->pre_enable = intel_mst_pre_enable_dp;
 	intel_encoder->enable = intel_mst_enable_dp;
 	intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index de38d014ed39..63b76eac018f 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -567,8 +567,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 }
 
 uint8_t
-bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
-				     uint8_t lane_count)
+bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
 {
 	switch (lane_count) {
 	case 1:
-- 
2.13.6

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
@ 2017-10-27 13:53 ` Ville Syrjälä
  2017-10-27 14:00 ` Maarten Lankhorst
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2017-10-27 13:53 UTC (permalink / raw)
  To: intel-gfx

On Fri, Oct 27, 2017 at 04:43:48PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
> the correct lane latency optimal setting applied. And we obviously need
> to compute the correct value, and read it out to keep the state checker
> happy.
> 
> While at it drop the useless 'encoder' parameter to
> bxt_ddi_phy_calc_lane_lat_optim_mask()
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  3 +--
>  drivers/gpu/drm/i915/intel_ddi.c      |  3 +--
>  drivers/gpu/drm/i915/intel_dp_mst.c   | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dpio_phy.c |  3 +--
>  4 files changed, 26 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 366ba74b0ad2..de32576b2540 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4177,8 +4177,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  			    enum dpio_phy phy);
>  bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			      enum dpio_phy phy);
> -uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
> -					     uint8_t lane_count);
> +uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
>  void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  				     uint8_t lane_lat_optim_mask);
>  uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 28c25cb9eb2c..d4b336cffe68 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2673,8 +2673,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
>  
>  	if (IS_GEN9_LP(dev_priv) && ret)
>  		pipe_config->lane_lat_optim_mask =
> -			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
> -							     pipe_config->lane_count);
> +			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>  
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 3d62c63c0763..c34ffa959e90 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -88,6 +88,10 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  
>  	pipe_config->dp_m_n.tu = slots;
>  
> +	if (IS_GEN9_LP(dev_priv))
> +		pipe_config->lane_lat_optim_mask =
> +			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
> +
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
>  	return true;
> @@ -182,6 +186,20 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  }
>  
> +static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
> +					const struct intel_crtc_state *pipe_config,
> +					const struct drm_connector_state *conn_state)
> +{
> +	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> +	struct intel_digital_port *intel_dig_port = intel_mst->primary;
> +	struct intel_dp *intel_dp = &intel_dig_port->dp;
> +
> +	if (intel_dp->active_mst_links == 0 &&

BTW this is yet another place that's probably totally broken when
it comes to parallel modesets.

I'm thinking we should do something higher up to prevent parallel
modesets in general, until someone properly reviews all the modeset
code. That's assuming we allow parallel modesets, which I think we
do with nonblocking.

> +	    intel_dig_port->base.pre_pll_enable)
> +		intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
> +						    pipe_config, NULL);
> +}
> +
>  static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *pipe_config,
>  				    const struct drm_connector_state *conn_state)
> @@ -311,6 +329,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
>  
>  	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
>  
> +	if (IS_GEN9_LP(dev_priv))
> +		pipe_config->lane_lat_optim_mask =
> +			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
> +
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  }
>  
> @@ -582,6 +604,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
>  	intel_encoder->compute_config = intel_dp_mst_compute_config;
>  	intel_encoder->disable = intel_mst_disable_dp;
>  	intel_encoder->post_disable = intel_mst_post_disable_dp;
> +	intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
>  	intel_encoder->pre_enable = intel_mst_pre_enable_dp;
>  	intel_encoder->enable = intel_mst_enable_dp;
>  	intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index de38d014ed39..63b76eac018f 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -567,8 +567,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  }
>  
>  uint8_t
> -bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
> -				     uint8_t lane_count)
> +bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
>  {
>  	switch (lane_count) {
>  	case 1:
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
  2017-10-27 13:53 ` Ville Syrjälä
@ 2017-10-27 14:00 ` Maarten Lankhorst
  2017-10-27 14:19 ` ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Maarten Lankhorst @ 2017-10-27 14:00 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

Op 27-10-17 om 15:43 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
> the correct lane latency optimal setting applied. And we obviously need
> to compute the correct value, and read it out to keep the state checker
> happy.
>
> While at it drop the useless 'encoder' parameter to
> bxt_ddi_phy_calc_lane_lat_optim_mask()
>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  3 +--
>  drivers/gpu/drm/i915/intel_ddi.c      |  3 +--
>  drivers/gpu/drm/i915/intel_dp_mst.c   | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dpio_phy.c |  3 +--
>  4 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 366ba74b0ad2..de32576b2540 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -4177,8 +4177,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  			    enum dpio_phy phy);
>  bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			      enum dpio_phy phy);
> -uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
> -					     uint8_t lane_count);
> +uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
>  void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  				     uint8_t lane_lat_optim_mask);
>  uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 28c25cb9eb2c..d4b336cffe68 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2673,8 +2673,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
>  
>  	if (IS_GEN9_LP(dev_priv) && ret)
>  		pipe_config->lane_lat_optim_mask =
> -			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
> -							     pipe_config->lane_count);
> +			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>  
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 3d62c63c0763..c34ffa959e90 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -88,6 +88,10 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  
>  	pipe_config->dp_m_n.tu = slots;
>  
> +	if (IS_GEN9_LP(dev_priv))
> +		pipe_config->lane_lat_optim_mask =
> +			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
> +
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
>  	return true;
> @@ -182,6 +186,20 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  }
>  
> +static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
> +					const struct intel_crtc_state *pipe_config,
> +					const struct drm_connector_state *conn_state)
> +{
> +	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> +	struct intel_digital_port *intel_dig_port = intel_mst->primary;
> +	struct intel_dp *intel_dp = &intel_dig_port->dp;
> +
> +	if (intel_dp->active_mst_links == 0 &&
> +	    intel_dig_port->base.pre_pll_enable)
> +		intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
> +						    pipe_config, NULL);
> +}
We really need to get better at locking in the future, but looks ok.
>  static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *pipe_config,
>  				    const struct drm_connector_state *conn_state)
> @@ -311,6 +329,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
>  
>  	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
>  
> +	if (IS_GEN9_LP(dev_priv))
> +		pipe_config->lane_lat_optim_mask =
> +			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
> +
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  }
>  
> @@ -582,6 +604,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
>  	intel_encoder->compute_config = intel_dp_mst_compute_config;
>  	intel_encoder->disable = intel_mst_disable_dp;
>  	intel_encoder->post_disable = intel_mst_post_disable_dp;
> +	intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
>  	intel_encoder->pre_enable = intel_mst_pre_enable_dp;
>  	intel_encoder->enable = intel_mst_enable_dp;
>  	intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index de38d014ed39..63b76eac018f 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -567,8 +567,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  }
>  
>  uint8_t
> -bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
> -				     uint8_t lane_count)
> +bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
>  {
>  	switch (lane_count) {
>  	case 1:

I don't have a BXT with DP-MST to test with, so this might need an ack by someone who does :)

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
  2017-10-27 13:53 ` Ville Syrjälä
  2017-10-27 14:00 ` Maarten Lankhorst
@ 2017-10-27 14:19 ` Patchwork
  2017-10-27 15:14 ` Patchwork
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-27 14:19 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL   : https://patchwork.freedesktop.org/series/32756/
State : failure

== Summary ==

Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/32756/revisions/1/mbox/

Test kms_busy:
        Subgroup basic-flip-a:
                pass       -> INCOMPLETE (fi-glk-dsi)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-gdg-551) fdo#102618
Test kms_frontbuffer_tracking:
        Subgroup basic:
                pass       -> DMESG-WARN (fi-bdw-5557u) fdo#102473

fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618
fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473

fi-bdw-5557u     total:289  pass:267  dwarn:1   dfail:0   fail:0   skip:21  time:445s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:453s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:373s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:521s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:266s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:504s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:503s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:492s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:471s
fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:604s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:418s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:251s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:575s
fi-glk-dsi       total:206  pass:183  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:427s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:428s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:419s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:494s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:459s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:483s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:568s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:477s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:583s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:540s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:447s
fi-skl-6600u     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:590s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:647s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:515s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:497s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:452s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:567s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:415s

795d258e67f403ff77d1f14b37551e98163f5b4e drm-tip: 2017y-10m-27d-11h-42m-39s UTC integration manifest
83e8bf78702a drm/i915: Fix BXT lane latenccy optimal setting with MST

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6234/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
                   ` (2 preceding siblings ...)
  2017-10-27 14:19 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-10-27 15:14 ` Patchwork
  2017-10-27 15:43 ` Patchwork
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-27 15:14 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL   : https://patchwork.freedesktop.org/series/32756/
State : failure

== Summary ==

Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/32756/revisions/1/mbox/

Test gem_exec_reloc:
        Subgroup basic-cpu-active:
                pass       -> FAIL       (fi-gdg-551) fdo#102582 +4
        Subgroup basic-write-cpu-active:
                pass       -> FAIL       (fi-gdg-551)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-gdg-551) fdo#102618
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-cnl-y)

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:444s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:454s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:372s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:528s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:267s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:500s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:501s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:489s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:479s
fi-cnl-y         total:231  pass:206  dwarn:0   dfail:0   fail:0   skip:24 
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-gdg-551       total:289  pass:172  dwarn:1   dfail:0   fail:7   skip:109 time:248s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:578s
fi-glk-dsi       total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  time:490s
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:428s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:427s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:420s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:501s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:460s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:490s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:562s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:477s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:583s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:554s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:448s
fi-skl-6600u     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:587s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:647s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:513s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:496s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:457s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:559s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:419s

795d258e67f403ff77d1f14b37551e98163f5b4e drm-tip: 2017y-10m-27d-11h-42m-39s UTC integration manifest
2e70ad81069a drm/i915: Fix BXT lane latenccy optimal setting with MST

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6237/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
                   ` (3 preceding siblings ...)
  2017-10-27 15:14 ` Patchwork
@ 2017-10-27 15:43 ` Patchwork
  2017-10-27 17:20 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-27 15:43 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL   : https://patchwork.freedesktop.org/series/32756/
State : failure

== Summary ==

Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/32756/revisions/1/mbox/

Test chamelium:
        Subgroup dp-crc-fast:
                pass       -> DMESG-FAIL (fi-kbl-7500u) fdo#102514
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-gdg-551) fdo#102618
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a-frame-sequence:
                pass       -> INCOMPLETE (fi-elk-e7500)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:442s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:446s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:373s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:521s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:264s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:502s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:492s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:491s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:479s
fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:603s
fi-elk-e7500     total:240  pass:189  dwarn:0   dfail:0   fail:0   skip:50 
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:250s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:582s
fi-glk-dsi       total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  time:484s
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:428s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:428s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:426s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:482s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:458s
fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:1   fail:0   skip:24  time:490s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:573s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:476s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:584s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:545s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:455s
fi-skl-6600u     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:595s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:642s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:518s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:503s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:462s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:563s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:415s

795d258e67f403ff77d1f14b37551e98163f5b4e drm-tip: 2017y-10m-27d-11h-42m-39s UTC integration manifest
023e9d5ec320 drm/i915: Fix BXT lane latenccy optimal setting with MST

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6238/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
                   ` (4 preceding siblings ...)
  2017-10-27 15:43 ` Patchwork
@ 2017-10-27 17:20 ` Patchwork
  2017-10-27 18:44 ` ✓ Fi.CI.IGT: " Patchwork
  2017-10-27 19:52 ` ✗ Fi.CI.BAT: failure " Patchwork
  7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-27 17:20 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL   : https://patchwork.freedesktop.org/series/32756/
State : success

== Summary ==

Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/32756/revisions/1/mbox/

Test chamelium:
        Subgroup dp-crc-fast:
                pass       -> FAIL       (fi-kbl-7500u) fdo#102514

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:445s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:444s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:375s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:530s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:265s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:505s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:493s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:492s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:479s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:249s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:580s
fi-glk-dsi       total:289  pass:258  dwarn:0   dfail:0   fail:1   skip:30  time:488s
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:425s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:432s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:422s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:490s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:458s
fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  time:486s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:570s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:476s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:584s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:546s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:447s
fi-skl-6600u     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:590s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:649s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:519s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:496s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:455s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:568s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:417s

4efa630855362c267af94785e50948bb60615bfe drm-tip: 2017y-10m-27d-15h-25m-04s UTC integration manifest
8e8a7250a4ce drm/i915: Fix BXT lane latenccy optimal setting with MST

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6241/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
                   ` (5 preceding siblings ...)
  2017-10-27 17:20 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-10-27 18:44 ` Patchwork
  2017-10-27 19:52 ` ✗ Fi.CI.BAT: failure " Patchwork
  7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-27 18:44 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL   : https://patchwork.freedesktop.org/series/32756/
State : success

== Summary ==

Test kms_flip:
        Subgroup plain-flip-fb-recreate-interruptible:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test perf:
        Subgroup blocking:
                fail       -> PASS       (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hsw        total:2539 pass:1432 dwarn:1   dfail:0   fail:9   skip:1097 time:9191s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6241/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Fix BXT lane latenccy optimal setting with MST
  2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
                   ` (6 preceding siblings ...)
  2017-10-27 18:44 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-10-27 19:52 ` Patchwork
  7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-10-27 19:52 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL   : https://patchwork.freedesktop.org/series/32756/
State : failure

== Summary ==

Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/32756/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-c-frame-sequence:
                pass       -> INCOMPLETE (fi-glk-dsi)

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:441s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:449s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:371s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:519s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:264s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:500s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:497s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:495s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:473s
fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:595s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:248s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:574s
fi-glk-dsi       total:244  pass:216  dwarn:0   dfail:0   fail:1   skip:26 
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:429s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:429s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:424s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:494s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:458s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:487s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:570s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:472s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:584s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:543s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:450s
fi-skl-6600u     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:586s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:645s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:519s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:499s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:460s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:562s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:415s

4efa630855362c267af94785e50948bb60615bfe drm-tip: 2017y-10m-27d-15h-25m-04s UTC integration manifest
0d9b5460560c drm/i915: Fix BXT lane latenccy optimal setting with MST

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6246/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-10-27 19:52 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-27 13:43 [PATCH] drm/i915: Fix BXT lane latenccy optimal setting with MST Ville Syrjala
2017-10-27 13:53 ` Ville Syrjälä
2017-10-27 14:00 ` Maarten Lankhorst
2017-10-27 14:19 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-10-27 15:14 ` Patchwork
2017-10-27 15:43 ` Patchwork
2017-10-27 17:20 ` ✓ Fi.CI.BAT: success " Patchwork
2017-10-27 18:44 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-27 19:52 ` ✗ Fi.CI.BAT: failure " Patchwork

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