All of lore.kernel.org
 help / color / mirror / Atom feed
From: Niklas Cassel <niklas.cassel@axis.com>
To: Niklas Cassel <niklass@axis.com>,
	Jesper Nilsson <jespern@axis.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@axis.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 16/17] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
Date: Mon, 30 Oct 2017 13:42:19 +0100	[thread overview]
Message-ID: <20171030124221.20690-17-niklas.cassel@axis.com> (raw)
In-Reply-To: <20171030124221.20690-1-niklas.cassel@axis.com>

The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
---
V2:
* Split out the DT binding change to a self contained patch.
* Added Rob's ack (from V1). No change to this file since V1.

 Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 33eef7ae5a23..979dc7b6cfe8 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -6,6 +6,8 @@ and thus inherits all the common properties defined in designware-pcie.txt.
 Required properties:
 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
 	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
+	      "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
+	      "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
 - reg: base addresses and lengths of the PCIe controller (DBI),
 	the PHY controller, and configuration address space.
 - reg-names: Must include the following entries:
-- 
2.14.2

  parent reply	other threads:[~2017-10-30 12:43 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-30 12:42 [PATCH v2 00/17] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-10-30 12:42 ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 01/17] PCI: dwc: Use DMA-API for allocating MSI data Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 02/17] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 03/17] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 04/17] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-10-31  6:01   ` Kishon Vijay Abraham I
2017-10-31 20:57     ` Niklas Cassel
2017-11-16 17:16     ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 05/17] PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() Niklas Cassel
2017-10-31  5:09   ` Kishon Vijay Abraham I
2017-10-31  5:09     ` Kishon Vijay Abraham I
2017-10-30 12:42 ` [PATCH v2 06/17] PCI: designware-ep: Add generic function for raising MSI irq Niklas Cassel
2017-10-31  6:22   ` Kishon Vijay Abraham I
2017-10-31 21:06     ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 07/17] PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode Niklas Cassel
2017-10-31  6:23   ` Kishon Vijay Abraham I
2017-10-30 12:42 ` [PATCH v2 08/17] PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe Niklas Cassel
2017-10-31  8:14   ` Kishon Vijay Abraham I
2017-10-31  8:14     ` Kishon Vijay Abraham I
2017-10-30 12:42 ` [PATCH v2 09/17] PCI: dwc: dra7xx: Add ifdefs for host/ep specific code Niklas Cassel
2017-10-31  8:29   ` Kishon Vijay Abraham I
2017-10-31  8:29     ` Kishon Vijay Abraham I
2017-10-31 21:27     ` Niklas Cassel
2017-10-31 21:27       ` Niklas Cassel
2017-10-31 21:38       ` Niklas Cassel
2017-10-31 21:38         ` Niklas Cassel
2017-10-31 22:51         ` Niklas Cassel
2017-10-31 22:51           ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 10/17] PCI: dwc: artpec6: Remove unused defines Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 11/17] PCI: dwc: artpec6: Use BIT and GENMASK macros Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 12/17] PCI: dwc: artpec6: Split artpec6_pcie_establish_link to smaller functions Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 13/17] bindings: PCI: artpec: Add support for endpoint mode Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 14/17] PCI: dwc: artpec6: " Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 15/17] PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-10-30 12:42 ` Niklas Cassel [this message]
2017-10-30 12:42 ` [PATCH v2 17/17] PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC Niklas Cassel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20171030124221.20690-17-niklas.cassel@axis.com \
    --to=niklas.cassel@axis.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=jespern@axis.com \
    --cc=linux-arm-kernel@axis.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=niklass@axis.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.