* [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable.
@ 2017-11-03 18:30 Rafael Antognolli
2017-11-03 19:16 ` ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2) Patchwork
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Rafael Antognolli @ 2017-11-03 18:30 UTC (permalink / raw)
To: intel-gfx
The workaround for this is described as:
"if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
Further documentation in the internal bug referenced by the bspec
suggest that any of the above suggestions should suffice to fix the
issue. We are going with disabling RCC clock gating.
Unfortunately, what we are doing doesn't match the name of the
workaround, but at least it matches its description.
This change improves CNL stability by avoiding some of the hangs seen in
the platform.
v2: Only disable RCC clock gating.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c775e96b4e4..bd36ec9bc93f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3837,6 +3837,7 @@ enum {
*/
#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
+#define RCCUNIT_CLKGATE_DIS (1 << 7)
/*
* Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f31f2d6384c3..3af0dcb91e9c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+ /* ReadHitWriteOnlyDisable: cnl */
+ WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)
2017-11-03 18:30 [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
@ 2017-11-03 19:16 ` Patchwork
2017-11-03 20:31 ` ✗ Fi.CI.IGT: warning " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-11-03 19:16 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)
URL : https://patchwork.freedesktop.org/series/32991/
State : success
== Summary ==
Series 32991v2 drm/i915: Implement ReadHitWriteOnlyDisable.
https://patchwork.freedesktop.org/api/1.0/series/32991/revisions/2/mbox/
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS (fi-cfl-s)
Subgroup create-fd-close:
dmesg-warn -> PASS (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS (fi-bsw-n3050)
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:455s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:382s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:535s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:277s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:504s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:504s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:491s
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:559s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:608s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:266s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:583s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:432s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:430s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:489s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:462s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:492s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:574s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:484s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:563s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:456s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:595s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:652s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:522s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:498s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:463s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:567s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:420s
8b0ae6b50a229dc661a02f4034252ee854cc9b83 drm-tip: 2017y-11m-03d-17h-15m-57s UTC integration manifest
d367636c14d1 drm/i915: Implement ReadHitWriteOnlyDisable.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6950/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)
2017-11-03 18:30 [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
2017-11-03 19:16 ` ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2) Patchwork
@ 2017-11-03 20:31 ` Patchwork
2017-11-08 20:07 ` [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rodrigo Vivi
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-11-03 20:31 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement ReadHitWriteOnlyDisable. (rev2)
URL : https://patchwork.freedesktop.org/series/32991/
State : warning
== Summary ==
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
fail -> DMESG-FAIL (shard-hsw) fdo#103375
Test kms_plane_lowres:
Subgroup pipe-B-tiling-none:
pass -> SKIP (shard-hsw)
Test kms_flip:
Subgroup wf_vblank-vs-dpms-interruptible:
pass -> INCOMPLETE (shard-hsw) fdo#102614
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
shard-hsw total:2528 pass:1426 dwarn:0 dfail:1 fail:7 skip:1093 time:9021s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6950/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-03 18:30 [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
2017-11-03 19:16 ` ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2) Patchwork
2017-11-03 20:31 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2017-11-08 20:07 ` Rodrigo Vivi
2017-11-08 20:47 ` Rodrigo Vivi
2017-11-10 21:21 ` Chris Wilson
4 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-11-08 20:07 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
On Fri, Nov 03, 2017 at 06:30:27PM +0000, Rafael Antognolli wrote:
> The workaround for this is described as:
>
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
>
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
>
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
>
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
>
> v2: Only disable RCC clock gating.
>
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
> */
> #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
>
> /*
> * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> + /* ReadHitWriteOnlyDisable: cnl */
> + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> +
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-03 18:30 [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
` (2 preceding siblings ...)
2017-11-08 20:07 ` [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rodrigo Vivi
@ 2017-11-08 20:47 ` Rodrigo Vivi
2017-11-10 21:21 ` Chris Wilson
4 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-11-08 20:47 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
On Fri, Nov 03, 2017 at 06:30:27PM +0000, Rafael Antognolli wrote:
> The workaround for this is described as:
>
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
>
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
>
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
>
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
>
> v2: Only disable RCC clock gating.
>
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Merged to dinq. Thanks for the patch.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
> */
> #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
>
> /*
> * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> + /* ReadHitWriteOnlyDisable: cnl */
> + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> +
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-03 18:30 [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
` (3 preceding siblings ...)
2017-11-08 20:47 ` Rodrigo Vivi
@ 2017-11-10 21:21 ` Chris Wilson
2017-11-10 22:01 ` Rafael Antognolli
4 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2017-11-10 21:21 UTC (permalink / raw)
To: Rafael Antognolli, intel-gfx
Quoting Rafael Antognolli (2017-11-03 18:30:27)
> The workaround for this is described as:
>
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
>
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
>
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
>
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
>
> v2: Only disable RCC clock gating.
>
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
> */
> #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
>
> /*
> * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> + /* ReadHitWriteOnlyDisable: cnl */
> + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
This is not sticking. Why are we applying SLICE_UNIT_LEVEL_CLKGATE as a
context register here, and as an ordinary unmasked register over in
cnl_init_clock_gating() ?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-10 21:21 ` Chris Wilson
@ 2017-11-10 22:01 ` Rafael Antognolli
0 siblings, 0 replies; 7+ messages in thread
From: Rafael Antognolli @ 2017-11-10 22:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 10, 2017 at 09:21:51PM +0000, Chris Wilson wrote:
> Quoting Rafael Antognolli (2017-11-03 18:30:27)
> > The workaround for this is described as:
> >
> > "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> > RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
> >
> > Further documentation in the internal bug referenced by the bspec
> > suggest that any of the above suggestions should suffice to fix the
> > issue. We are going with disabling RCC clock gating.
> >
> > Unfortunately, what we are doing doesn't match the name of the
> > workaround, but at least it matches its description.
> >
> > This change improves CNL stability by avoiding some of the hangs seen in
> > the platform.
> >
> > v2: Only disable RCC clock gating.
> >
> > Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8c775e96b4e4..bd36ec9bc93f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3837,6 +3837,7 @@ enum {
> > */
> > #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > #define SARBUNIT_CLKGATE_DIS (1 << 5)
> > +#define RCCUNIT_CLKGATE_DIS (1 << 7)
> >
> > /*
> > * Display engine regs
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index f31f2d6384c3..3af0dcb91e9c 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> > WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> > GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
> >
> > + /* ReadHitWriteOnlyDisable: cnl */
> > + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
>
> This is not sticking. Why are we applying SLICE_UNIT_LEVEL_CLKGATE as a
> context register here, and as an ordinary unmasked register over in
> cnl_init_clock_gating() ?
Ugh, I didn't know there was a better place for this. Feel free to move it to
cnl_init_clock_gating(), or I can send a patch soon. Sorry for the mess.
Rafael
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-11-10 22:01 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-03 18:30 [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
2017-11-03 19:16 ` ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable. (rev2) Patchwork
2017-11-03 20:31 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-11-08 20:07 ` [PATCH v2] drm/i915: Implement ReadHitWriteOnlyDisable Rodrigo Vivi
2017-11-08 20:47 ` Rodrigo Vivi
2017-11-10 21:21 ` Chris Wilson
2017-11-10 22:01 ` Rafael Antognolli
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