[PATCH 0/2] riscv: pass endianness and machine size to sparse

[PATCH 0/2] riscv: pass endianness and machine size to sparse

[Luc Van Oostenryck]

The goal of these two patches is to ass endianness and machine
size info to sparse so that sparse can emit correct diagnostics
even when the endianness and machine size doesn't correspond to
sparse's defaults.

Luc Van Oostenryck (2):
  riscv: pass endianness info to sparse
  riscv: pass machine size to sparse

 arch/riscv/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

-- 

To: Palmer Dabbelt <palmer@sifive.com>
CC: Albert Ou <albert@sifive.com>
CC: patches@groups.riscv.org
CC: linux-kernel@vger.kernel.org

[PATCH 1/2] riscv: pass endianness info to sparse

[Luc Van Oostenryck]

RISC-V is little-endian only but sparse assumes the same
endianness as the building machine.
This is problematic for code which expect __BYTE_ORDER__ being
correctly predefined by the compiler which sparse can then
pre-process differently from what gcc would, depending on the
building machine endianness.

To avoid any possible problem, fix this by letting sparse know
about the architecture endianness.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
---
 arch/riscv/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6719dd30e..206484dde 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -16,6 +16,8 @@ KBUILD_CFLAGS_MODULE += -fPIC
 
 KBUILD_DEFCONFIG = defconfig
 
+CHECKFLAGS += -mlittle-endian
+
 export BITS
 ifeq ($(CONFIG_ARCH_RV64I),y)
 	BITS := 64
-- 
2.14.0

[PATCH 2/2] riscv: pass machine size to sparse

[Luc Van Oostenryck]

By default, sparse assumes a 64bit machine when compiled on x86-64
and 32bit when compiled on anything else.

This can of course create all sort of problems when this doesn't
correspond to the target's machine size, like issuing false
warnings like: 'constant ... is so big it is unsigned long long'
or 'shift too big (32) for type unsigned long' when the architecture
is 64bit while sparse was compiled on a 32bit machine, or worse,
to not emit legitimate warnings in the reverse situation.

Fix this by passing the appropriate -m32/-m64 flag to sparse.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
---
 arch/riscv/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 206484dde..a0ea7a71d 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -27,6 +27,7 @@ ifeq ($(CONFIG_ARCH_RV64I),y)
 	KBUILD_AFLAGS += -mabi=lp64
 	KBUILD_MARCH = rv64im
 	LDFLAGS += -melf64lriscv
+	CHECKFLAGS += -m64
 else
 	BITS := 32
 	UTS_MACHINE := riscv32
@@ -35,6 +36,7 @@ else
 	KBUILD_AFLAGS += -mabi=ilp32
 	KBUILD_MARCH = rv32im
 	LDFLAGS += -melf32lriscv
+	CHECKFLAGS += -m32
 endif
 
 KBUILD_CFLAGS += -Wall
-- 
2.14.0

Re: [patches] [PATCH 0/2] riscv: pass endianness and machine size to sparse

[Palmer Dabbelt]

On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenryck@gmail.com wrote:
> The goal of these two patches is to ass endianness and machine
> size info to sparse so that sparse can emit correct diagnostics
> even when the endianness and machine size doesn't correspond to
> sparse's defaults.
>
> Luc Van Oostenryck (2):
>   riscv: pass endianness info to sparse
>   riscv: pass machine size to sparse
>
>  arch/riscv/Makefile | 4 ++++
>  1 file changed, 4 insertions(+)

Thanks!  I'll take these into the RISC-V tree.

Re: [patches] [PATCH 0/2] riscv: pass endianness and machine size to sparse

[Luc Van Oostenryck]

On Thu, Nov 9, 2017 at 10:36 PM, Palmer Dabbelt <palmer@sifive.com> wrote:
> On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenryck@gmail.com wrote:
>> The goal of these two patches is to ass endianness and machine
>> size info to sparse so that sparse can emit correct diagnostics
>> even when the endianness and machine size doesn't correspond to
>> sparse's defaults.
>>
>> Luc Van Oostenryck (2):
>>   riscv: pass endianness info to sparse
>>   riscv: pass machine size to sparse
>>
>>  arch/riscv/Makefile | 4 ++++
>>  1 file changed, 4 insertions(+)
>
> Thanks!  I'll take these into the RISC-V tree.

Well, better to hold one because someone has asked
to treat the problem in a generic way (the same problem exist
on other archs) and I certainly think it's indeed better.

I'll sent a newer patch in a day or two.

Sorry for this,
-- Luc Van Oostenryck

Re: [patches] [PATCH 0/2] riscv: pass endianness and machine size to sparse

[Palmer Dabbelt]

On Thu, 09 Nov 2017 13:46:50 PST (-0800), luc.vanoostenryck@gmail.com wrote:
> On Thu, Nov 9, 2017 at 10:36 PM, Palmer Dabbelt <palmer@sifive.com> wrote:
>> On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenryck@gmail.com wrote:
>>> The goal of these two patches is to ass endianness and machine
>>> size info to sparse so that sparse can emit correct diagnostics
>>> even when the endianness and machine size doesn't correspond to
>>> sparse's defaults.
>>>
>>> Luc Van Oostenryck (2):
>>>   riscv: pass endianness info to sparse
>>>   riscv: pass machine size to sparse
>>>
>>>  arch/riscv/Makefile | 4 ++++
>>>  1 file changed, 4 insertions(+)
>>
>> Thanks!  I'll take these into the RISC-V tree.
>
> Well, better to hold one because someone has asked
> to treat the problem in a generic way (the same problem exist
> on other archs) and I certainly think it's indeed better.
>
> I'll sent a newer patch in a day or two.

OK, no problem.  I'm re-organizing our big list of outstanding patches (in
addition the reviewed ones I'll be sending up), so I'll just leave this on a
staging branch.

Thanks!