* [RFC 0/7] UVD support for SI in amdgpu
@ 2017-11-08 22:38 Piotr Redlewski
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hi,
Following series implements UVD support for SI in amdgpu driver. Code is based
on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
it requires tahiti uvd firmware with added header - I've created simple script
to produce exactly this, so if anyone is interested it can be found here:
https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
Code is based on amd-staging-drm-next branch in Alex's tree. After applying
these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
and mpv.
Some comments/issues for the patches:
1. To make uvd work, I had to bring back fb location programming. Using location
programmed by vbios, vram location is not available for uvd mc (at least on my
machine) due to too wide address. Starting address is 40-bit long for fb, but
uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
in radeon driver)
2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
offsets before starting other engines. Because of that I set it in .sw_init
function. In my opinion this should be fixed as it generally doesn't follow
amdgpu driver architecture (hardware setup during software setup stage) and
probably will break suspending and resume (I didn't test it). As I mentioned,
I couldn't figure out why this is happening, so I count on help with finding fix
for this.
3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
this file is generated, so fix should be made wherever it is generated from. For
now I removed offending lines just to silence the compiler warnings.
4. I'm not sure whether I choose the right version for the uvd. Existing code in
si.c suggested that it should be 3.1, however I went with the 4.0, because for
this version there are available new style headers.
Regards,
Piotr
Piotr Redlewski (7):
drm/amdgpu: remove duplicated definitions of some of the SI registers
drm/amdgpu/uvd4: fix some register's mask and shift definitions
drm/amdgpu/gmc6: don't use vram location programmed by the vbios
drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
drm/amdgpu: enable UVD for SI
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
.../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
13 files changed, 1273 insertions(+), 68 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
--
2.15.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [RFC 1/7] drm/amdgpu: remove duplicated definitions of some of the SI registers
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 22:38 ` [RFC 2/7] drm/amdgpu/uvd4: fix some register's mask and shift definitions Piotr Redlewski
` (6 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Some of the registers are defined both in the sid.h and in the new style
headers. Removed definitions from the sid.h
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/si.c | 1 +
drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +++
drivers/gpu/drm/amd/amdgpu/sid.h | 16 ----------------
3 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 8284d5dbfc30..2ac1c2be8ca4 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -42,6 +42,7 @@
#include "dce_virtual.h"
#include "gca/gfx_6_0_d.h"
#include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
#include "gmc/gmc_6_0_d.h"
#include "dce/dce_6_0_d.h"
#include "uvd/uvd_4_0_d.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index d2c6b80309c8..ca53ff7e3c56 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -26,6 +26,9 @@
#include "sid.h"
#include "si_ih.h"
+#include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
+
static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
static void si_ih_enable_interrupts(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index c57eff159374..59f8fc944ecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -2320,10 +2320,6 @@
# define NI_INPUT_GAMMA_XVYCC_222 3
# define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
-#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
-#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
-#define SRBM_STATUS__IH_BUSY_MASK 0x20000
-#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
#define BLACKOUT_MODE_MASK 0x00000007
#define VGA_RENDER_CONTROL 0xC0
@@ -2411,16 +2407,6 @@
#define MC_SEQ_MISC0__MT__HBM 0x60000000
#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
-#define SRBM_STATUS__MCB_BUSY_MASK 0x200
-#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
-#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
-#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
-#define SRBM_STATUS__MCC_BUSY_MASK 0x800
-#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
-#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
-#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
-#define SRBM_STATUS__VMC_BUSY_MASK 0x100
-#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
@@ -2447,8 +2433,6 @@
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
-#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
-#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
#define PCIE_PORT_INDEX 0xe
#define PCIE_PORT_DATA 0xf
#define EVERGREEN_PIF_PHY0_INDEX 0x8
--
2.15.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 2/7] drm/amdgpu/uvd4: fix some register's mask and shift definitions
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-08 22:38 ` [RFC 1/7] drm/amdgpu: remove duplicated definitions of some of the SI registers Piotr Redlewski
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 22:38 ` [RFC 3/7] drm/amdgpu/gmc6: don't use vram location programmed by the vbios Piotr Redlewski
` (5 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
UVD_LMI_CTRL__RFU_MASK and UVD_LMI_CTRL__RFU__SHIFT are defined twice,
each time with different values
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
index 8ee3149df5b7..2ef1273e65ab 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
@@ -340,8 +340,6 @@
#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009
#define UVD_LMI_CTRL__RFU_MASK 0xf8000000L
-#define UVD_LMI_CTRL__RFU_MASK 0xfc000000L
-#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a
#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b
#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
--
2.15.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 3/7] drm/amdgpu/gmc6: don't use vram location programmed by the vbios
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-08 22:38 ` [RFC 1/7] drm/amdgpu: remove duplicated definitions of some of the SI registers Piotr Redlewski
2017-11-08 22:38 ` [RFC 2/7] drm/amdgpu/uvd4: fix some register's mask and shift definitions Piotr Redlewski
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 22:38 ` [RFC 4/7] drm/amdgpu/uvd4: add early init stage functions for uvd 4.0 Piotr Redlewski
` (4 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On SI chips, fb location programmed by the vbios (40-bit address) is out of
reach of the UVD memory controller, which supports only 32-bits.
This partially reverts following commits:
commit e4f6b39e8bcd ("drm/amdgpu: remove *_mc_access from display funcs")
commit 71086a3e8470 ("drm/amdgpu/gmc6: drop fb location programming")
commit ba3a5b83dd9b ("drm/amdgpu/gmc6: use the vram location programmed by the vbios")
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 ++
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++++++++++++++++++++++++++++++-
drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 ++
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 ++++++++---
4 files changed, 155 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 4069a3b2f55f..0bd916bd4c08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -262,6 +262,12 @@ struct amdgpu_audio {
int num_pins;
};
+struct amdgpu_mode_mc_save {
+ u32 vga_render_control;
+ u32 vga_hdp_control;
+ bool crtc_enabled[AMDGPU_MAX_CRTCS];
+};
+
struct amdgpu_display_funcs {
/* display watermarks */
void (*bandwidth_update)(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bd2c4f727df6..b9549806abc1 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -393,8 +393,118 @@ static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
return mmDC_GPIO_HPD_A;
}
-static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
- bool render)
+static u32 evergreen_get_vblank_counter(struct amdgpu_device *adev, int crtc)
+{
+ if (crtc >= adev->mode_info.num_crtc)
+ return 0;
+ else
+ return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
+}
+
+void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save)
+{
+ u32 crtc_enabled, tmp, frame_count;
+ int i, j;
+
+ save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
+ save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
+
+ /* disable VGA render */
+ WREG32(mmVGA_RENDER_CONTROL, 0);
+
+ /* blank the display controllers */
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
+ if (crtc_enabled) {
+ save->crtc_enabled[i] = true;
+ tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
+
+ if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
+ dce_v6_0_vblank_wait(adev, i);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
+ WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ /* wait for the next frame */
+ frame_count = evergreen_get_vblank_counter(adev, i);
+ for (j = 0; j < adev->usec_timeout; j++) {
+ if (evergreen_get_vblank_counter(adev, i) != frame_count)
+ break;
+ udelay(1);
+ }
+
+ /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
+ tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
+ WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ save->crtc_enabled[i] = false;
+ /* ***** */
+ } else {
+ save->crtc_enabled[i] = false;
+ }
+ }
+}
+
+void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save)
+{
+ u32 tmp;
+ int i, j;
+
+ /* update crtc base addresses */
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
+ upper_32_bits(adev->mc.vram_start));
+ WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
+ upper_32_bits(adev->mc.vram_start));
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
+ (u32)adev->mc.vram_start);
+ WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
+ (u32)adev->mc.vram_start);
+ }
+
+ WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
+ WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
+
+ /* unlock regs and wait for update */
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ if (save->crtc_enabled[i]) {
+ tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
+ if ((tmp & 0x7) != 0) {
+ tmp &= ~0x7;
+ WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
+ if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
+ tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
+ WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
+ if (tmp & 1) {
+ tmp &= ~1;
+ WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+ }
+ for (j = 0; j < adev->usec_timeout; j++) {
+ tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
+ if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
+ break;
+ udelay(1);
+ }
+ }
+ }
+
+ /* Unlock vga access */
+ WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
+ mdelay(1);
+ WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
+
+}
+
+void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, bool render)
{
if (!render)
WREG32(mmVGA_RENDER_CONTROL,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
index 7b546b596de1..35134523f53d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
@@ -28,5 +28,10 @@ extern const struct amdgpu_ip_block_version dce_v6_0_ip_block;
extern const struct amdgpu_ip_block_version dce_v6_4_ip_block;
void dce_v6_0_disable_dce(struct amdgpu_device *adev);
+void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save);
+void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save);
+void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, bool render);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index d2a43db22cff..3f891f22af93 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -24,6 +24,7 @@
#include <drm/drmP.h>
#include "amdgpu.h"
#include "gmc_v6_0.h"
+#include "dce_v6_0.h"
#include "amdgpu_ucode.h"
#include "bif/bif_3_0_d.h"
@@ -66,10 +67,14 @@ static const u32 crtc_offsets[6] =
SI_CRTC5_REGISTER_OFFSET
};
-static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
+static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save)
{
u32 blackout;
+ if (adev->mode_info.num_crtc)
+ dce_v6_0_stop_mc_access(adev, save);
+
gmc_v6_0_wait_for_idle((void *)adev);
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
@@ -86,7 +91,8 @@ static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
}
-static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
+static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save)
{
u32 tmp;
@@ -98,6 +104,9 @@ static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
WREG32(mmBIF_FB_EN, tmp);
+
+ if (adev->mode_info.num_crtc)
+ dce_v6_0_resume_mc_access(adev, save);
}
static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
@@ -219,20 +228,19 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
struct amdgpu_mc *mc)
{
- u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
- base <<= 24;
-
if (mc->mc_vram_size > 0xFFC0000000ULL) {
dev_warn(adev->dev, "limiting VRAM\n");
mc->real_vram_size = 0xFFC0000000ULL;
mc->mc_vram_size = 0xFFC0000000ULL;
}
- amdgpu_vram_location(adev, &adev->mc, base);
+ amdgpu_vram_location(adev, &adev->mc, 0);
amdgpu_gart_location(adev, mc);
}
static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
{
+ struct amdgpu_mode_mc_save save;
+ u32 tmp;
int i, j;
/* Initialize HDP */
@@ -245,6 +253,11 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
}
WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
+ if (adev->mode_info.num_crtc)
+ dce_v6_0_set_vga_render_state(adev, false);
+
+ gmc_v6_0_mc_stop(adev, &save);
+
if (gmc_v6_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
@@ -269,6 +282,15 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
adev->mc.vram_end >> 12);
WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
adev->vram_scratch.gpu_addr >> 12);
+
+ tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
+ tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
+ WREG32(mmMC_VM_FB_LOCATION, tmp);
+ /* XXX double check these! */
+ WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
+ WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
+ WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
+
WREG32(mmMC_VM_AGP_BASE, 0);
WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
@@ -276,6 +298,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
if (gmc_v6_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
+ gmc_v6_0_mc_resume(adev, &save);
}
static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
@@ -997,6 +1020,7 @@ static int gmc_v6_0_wait_for_idle(void *handle)
static int gmc_v6_0_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_mode_mc_save save;
u32 srbm_soft_reset = 0;
u32 tmp = RREG32(mmSRBM_STATUS);
@@ -1012,7 +1036,7 @@ static int gmc_v6_0_soft_reset(void *handle)
}
if (srbm_soft_reset) {
- gmc_v6_0_mc_stop(adev);
+ gmc_v6_0_mc_stop(adev, &save);
if (gmc_v6_0_wait_for_idle(adev)) {
dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
}
@@ -1032,7 +1056,7 @@ static int gmc_v6_0_soft_reset(void *handle)
udelay(50);
- gmc_v6_0_mc_resume(adev);
+ gmc_v6_0_mc_resume(adev, &save);
udelay(50);
}
--
2.15.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 4/7] drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (2 preceding siblings ...)
2017-11-08 22:38 ` [RFC 3/7] drm/amdgpu/gmc6: don't use vram location programmed by the vbios Piotr Redlewski
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 22:38 ` [RFC 5/7] drm/amdgpu/uvd4: add sw init and fini stages' " Piotr Redlewski
` (3 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Add uvd ring and interrupt functions
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/sid.h | 14 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 282 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 ++++
3 files changed, 319 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index 59f8fc944ecb..42556e2fafd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -1646,16 +1646,20 @@
/*
* PM4
*/
-#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
- (((reg) >> 2) & 0xFFFF) | \
+#define PACKET_TYPE0 0
+#define PACKET_TYPE1 1
+#define PACKET_TYPE2 2
+#define PACKET_TYPE3 3
+
+#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
+ ((reg) & 0xFFFF) | \
((n) & 0x3FFF) << 16)
#define CP_PACKET2 0x80000000
#define PACKET2_PAD_SHIFT 0
#define PACKET2_PAD_MASK (0x3fffffff << 0)
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-#define RADEON_PACKET_TYPE3 3
-#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
+#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
(((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
@@ -2407,8 +2411,6 @@
#define MC_SEQ_MISC0__MT__HBM 0x60000000
#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
-
-
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
#define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
new file mode 100644
index 000000000000..127269a0a90c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Christian König <christian.koenig@amd.com>
+ */
+
+#include <linux/firmware.h>
+#include <drm/drmP.h>
+#include "amdgpu.h"
+#include "amdgpu_uvd.h"
+#include "sid.h"
+
+#include "uvd/uvd_4_0_d.h"
+#include "uvd/uvd_4_0_sh_mask.h"
+
+#include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
+
+#include "bif/bif_3_0_d.h"
+
+static void uvd_v4_0_set_ring_funcs(struct amdgpu_device *adev);
+static void uvd_v4_0_set_irq_funcs(struct amdgpu_device *adev);
+
+/**
+ * uvd_v4_0_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t uvd_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ return RREG32(mmUVD_RBC_RB_RPTR);
+}
+
+/**
+ * uvd_v4_0_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware write pointer
+ */
+static uint64_t uvd_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ return RREG32(mmUVD_RBC_RB_WPTR);
+}
+
+/**
+ * uvd_v4_0_ring_set_wptr - set write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the write pointer to the hardware
+ */
+static void uvd_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
+}
+
+static int uvd_v4_0_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ uvd_v4_0_set_ring_funcs(adev);
+ uvd_v4_0_set_irq_funcs(adev);
+
+ return 0;
+}
+
+/**
+ * uvd_v4_0_ring_emit_fence - emit an fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write a fence and a trap command to the ring.
+ */
+static void uvd_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+ u64 seq, unsigned int flags)
+{
+ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+ amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
+ amdgpu_ring_write(ring, seq);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+ amdgpu_ring_write(ring, lower_32_bits(addr));
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+ amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+ amdgpu_ring_write(ring, 0);
+
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+ amdgpu_ring_write(ring, 2);
+}
+
+/**
+ * uvd_v4_0_ring_emit_hdp_flush - emit an hdp flush
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Emits an hdp flush.
+ */
+static void uvd_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
+ amdgpu_ring_write(ring, 0);
+}
+
+/**
+ * uvd_v4_0_ring_emit_hdp_invalidate - emit an hdp invalidate
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Emits an hdp invalidate.
+ */
+static void uvd_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
+ amdgpu_ring_write(ring, 1);
+}
+
+/**
+ * uvd_v4_0_ring_test_ring - register write test
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Test if we can successfully write to the context register
+ */
+static int uvd_v4_0_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t tmp = 0;
+ unsigned int i;
+ int r;
+
+ WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+ ring->idx, r);
+ return r;
+ }
+ amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
+ amdgpu_ring_write(ring, 0xDEADBEEF);
+ amdgpu_ring_commit(ring);
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(mmUVD_CONTEXT_ID);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+
+ if (i < adev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+ } else {
+ DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
+ ring->idx, tmp);
+ r = -EINVAL;
+ }
+ return r;
+}
+
+/**
+ * uvd_v4_0_ring_emit_ib - execute indirect buffer
+ *
+ * @ring: amdgpu_ring pointer
+ * @ib: indirect buffer to execute
+ *
+ * Write ring commands to execute the indirect buffer
+ */
+static void uvd_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_ib *ib,
+ unsigned int vm_id, bool ctx_switch)
+{
+ amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
+ amdgpu_ring_write(ring, ib->gpu_addr);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
+ amdgpu_ring_write(ring, ib->length_dw);
+}
+
+static int uvd_v4_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned int type,
+ enum amdgpu_interrupt_state state)
+{
+ // TODO
+ return 0;
+}
+
+static int uvd_v4_0_process_interrupt(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ DRM_DEBUG("IH: UVD TRAP\n");
+ amdgpu_fence_process(&adev->uvd.ring);
+ return 0;
+}
+
+static const struct amd_ip_funcs uvd_v4_0_ip_funcs = {
+ .name = "uvd_v4_0",
+ .early_init = uvd_v4_0_early_init,
+ .late_init = NULL,
+};
+
+static const struct amdgpu_ring_funcs uvd_v4_0_ring_funcs = {
+ .type = AMDGPU_RING_TYPE_UVD,
+ .align_mask = 0xf,
+ .nop = PACKET0(mmUVD_NO_OP, 0),
+ .support_64bit_ptrs = false,
+ .get_rptr = uvd_v4_0_ring_get_rptr,
+ .get_wptr = uvd_v4_0_ring_get_wptr,
+ .set_wptr = uvd_v4_0_ring_set_wptr,
+ .parse_cs = amdgpu_uvd_ring_parse_cs,
+ .emit_frame_size =
+ 2 + /* uvd_v4_0_ring_emit_hdp_flush */
+ 2 + /* uvd_v4_0_ring_emit_hdp_invalidate */
+ 14, /* uvd_v4_0_ring_emit_fence x1 no user fence */
+ .emit_ib_size = 4, /* uvd_v4_0_ring_emit_ib */
+ .emit_ib = uvd_v4_0_ring_emit_ib,
+ .emit_fence = uvd_v4_0_ring_emit_fence,
+ .emit_hdp_flush = uvd_v4_0_ring_emit_hdp_flush,
+ .emit_hdp_invalidate = uvd_v4_0_ring_emit_hdp_invalidate,
+ .test_ring = uvd_v4_0_ring_test_ring,
+ .test_ib = amdgpu_uvd_ring_test_ib,
+ .insert_nop = amdgpu_ring_insert_nop,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_uvd_ring_begin_use,
+ .end_use = amdgpu_uvd_ring_end_use,
+};
+
+static void uvd_v4_0_set_ring_funcs(struct amdgpu_device *adev)
+{
+ adev->uvd.ring.funcs = &uvd_v4_0_ring_funcs;
+}
+
+static const struct amdgpu_irq_src_funcs uvd_v4_0_irq_funcs = {
+ .set = uvd_v4_0_set_interrupt_state,
+ .process = uvd_v4_0_process_interrupt,
+};
+
+static void uvd_v4_0_set_irq_funcs(struct amdgpu_device *adev)
+{
+ adev->uvd.irq.num_types = 1;
+ adev->uvd.irq.funcs = &uvd_v4_0_irq_funcs;
+}
+
+const struct amdgpu_ip_block_version uvd_v4_0_ip_block = {
+ .type = AMD_IP_BLOCK_TYPE_UVD,
+ .major = 4,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &uvd_v4_0_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
new file mode 100644
index 000000000000..e74147c86643
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __UVD_V4_0_H__
+#define __UVD_V4_0_H__
+
+extern const struct amdgpu_ip_block_version uvd_v4_0_ip_block;
+
+#endif
--
2.15.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 5/7] drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (3 preceding siblings ...)
2017-11-08 22:38 ` [RFC 4/7] drm/amdgpu/uvd4: add early init stage functions for uvd 4.0 Piotr Redlewski
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 22:38 ` [RFC 6/7] drm/amdgpu/uvd4: add hardware specific " Piotr Redlewski
` (2 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Load firmware and initialize uvd ring
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 ++++++++++++
drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 40 +++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index be607b2be4e9..59ae2f2012ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -52,6 +52,9 @@
#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
/* Firmware Names */
+#ifdef CONFIG_DRM_AMDGPU_SI
+#define FIRMWARE_TAHITI "radeon/tahiti_uvd.bin"
+#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
#define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
@@ -94,6 +97,9 @@ struct amdgpu_uvd_cs_ctx {
unsigned *buf_sizes;
};
+#ifdef CONFIG_DRM_AMDGPU_SI
+MODULE_FIRMWARE(FIRMWARE_TAHITI);
+#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
MODULE_FIRMWARE(FIRMWARE_BONAIRE);
MODULE_FIRMWARE(FIRMWARE_KABINI);
@@ -126,6 +132,14 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+ case CHIP_TAHITI:
+ case CHIP_VERDE:
+ case CHIP_PITCAIRN:
+ case CHIP_OLAND:
+ fw_name = FIRMWARE_TAHITI;
+ break;
+#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_BONAIRE:
fw_name = FIRMWARE_BONAIRE;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
index 127269a0a90c..cfa6959db43d 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
@@ -91,6 +91,44 @@ static int uvd_v4_0_early_init(void *handle)
return 0;
}
+static int uvd_v4_0_sw_init(void *handle)
+{
+ struct amdgpu_ring *ring;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int r;
+
+ /* UVD TRAP */
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
+ if (r)
+ return r;
+
+ r = amdgpu_uvd_sw_init(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_uvd_resume(adev);
+ if (r)
+ return r;
+
+ ring = &adev->uvd.ring;
+ sprintf(ring->name, "uvd");
+ r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+
+ return r;
+}
+
+static int uvd_v4_0_sw_fini(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = amdgpu_uvd_suspend(adev);
+ if (r)
+ return r;
+
+ return amdgpu_uvd_sw_fini(adev);
+}
+
/**
* uvd_v4_0_ring_emit_fence - emit an fence & trap command
*
@@ -229,6 +267,8 @@ static const struct amd_ip_funcs uvd_v4_0_ip_funcs = {
.name = "uvd_v4_0",
.early_init = uvd_v4_0_early_init,
.late_init = NULL,
+ .sw_init = uvd_v4_0_sw_init,
+ .sw_fini = uvd_v4_0_sw_fini,
};
static const struct amdgpu_ring_funcs uvd_v4_0_ring_funcs = {
--
2.15.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 6/7] drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (4 preceding siblings ...)
2017-11-08 22:38 ` [RFC 5/7] drm/amdgpu/uvd4: add sw init and fini stages' " Piotr Redlewski
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 22:38 ` [RFC 7/7] drm/amdgpu: enable UVD for SI Piotr Redlewski
2017-11-08 23:54 ` [RFC 0/7] UVD support for SI in amdgpu Alex Deucher
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Add logic for starting, stopping, suspending and resuming uvd block
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
drivers/gpu/drm/amd/amdgpu/si.c | 250 ++++++++++++++++-
drivers/gpu/drm/amd/amdgpu/sid.h | 22 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 488 ++++++++++++++++++++++++++++++++++
4 files changed, 736 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 9430d4809b53..0744117ee7d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1695,13 +1695,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
-#if 0
- if (adev->has_uvd) {
- WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
- WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
- WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
- }
-#endif
gfx_v6_0_tiling_mode_table_init(adev);
gfx_v6_0_setup_rb(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 2ac1c2be8ca4..bc6fd1ff4f86 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -971,6 +971,28 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
}
+static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
+{
+ unsigned long flags;
+ u32 r;
+
+ spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
+ WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
+ r = RREG32(mmUVD_CTX_DATA);
+ spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
+ return r;
+}
+
+static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
+ WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
+ WREG32(mmUVD_CTX_DATA, (v));
+ spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
+}
+
static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
{GRBM_STATUS},
{GB_ADDR_CONFIG},
@@ -1219,9 +1241,231 @@ static u32 si_get_xclk(struct amdgpu_device *adev)
return reference_clock;
}
-//xxx:not implemented
+
+static unsigned si_uvd_calc_upll_post_div(unsigned vco_freq,
+ unsigned target_freq,
+ unsigned pd_min,
+ unsigned pd_even)
+{
+ unsigned post_div = vco_freq / target_freq;
+
+ /* adjust to post divider minimum value */
+ if (post_div < pd_min)
+ post_div = pd_min;
+
+ /* we alway need a frequency less than or equal the target */
+ if ((vco_freq / post_div) > target_freq)
+ post_div += 1;
+
+ /* post dividers above a certain value must be even */
+ if (post_div > pd_even && post_div % 2)
+ post_div += 1;
+
+ return post_div;
+}
+
+/**
+ * si_uvd_calc_upll_dividers - calc UPLL clock dividers
+ *
+ * @adev: amdgpu_device pointer
+ * @vclk: wanted VCLK
+ * @dclk: wanted DCLK
+ * @vco_min: minimum VCO frequency
+ * @vco_max: maximum VCO frequency
+ * @fb_factor: factor to multiply vco freq with
+ * @fb_mask: limit and bitmask for feedback divider
+ * @pd_min: post divider minimum
+ * @pd_max: post divider maximum
+ * @pd_even: post divider must be even above this value
+ * @optimal_fb_div: resulting feedback divider
+ * @optimal_vclk_div: resulting vclk post divider
+ * @optimal_dclk_div: resulting dclk post divider
+ *
+ * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
+ * Returns zero on success -EINVAL on error.
+ */
+int si_uvd_calc_upll_dividers(struct amdgpu_device *adev,
+ unsigned vclk, unsigned dclk,
+ unsigned vco_min, unsigned vco_max,
+ unsigned fb_factor, unsigned fb_mask,
+ unsigned pd_min, unsigned pd_max,
+ unsigned pd_even,
+ unsigned *optimal_fb_div,
+ unsigned *optimal_vclk_div,
+ unsigned *optimal_dclk_div)
+{
+ unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq;
+
+ /* start off with something large */
+ unsigned optimal_score = ~0;
+
+ /* loop through vco from low to high */
+ vco_min = max(max(vco_min, vclk), dclk);
+ for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
+
+ uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
+ unsigned vclk_div, dclk_div, score;
+
+ do_div(fb_div, ref_freq);
+
+ /* fb div out of range ? */
+ if (fb_div > fb_mask)
+ break; /* it can oly get worse */
+
+ fb_div &= fb_mask;
+
+ /* calc vclk divider with current vco freq */
+ vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk,
+ pd_min, pd_even);
+ if (vclk_div > pd_max)
+ break; /* vco is too big, it has to stop */
+
+ /* calc dclk divider with current vco freq */
+ dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk,
+ pd_min, pd_even);
+ if (vclk_div > pd_max)
+ break; /* vco is too big, it has to stop */
+
+ /* calc score with current vco freq */
+ score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
+
+ /* determine if this vco setting is better than current optimal settings */
+ if (score < optimal_score) {
+ *optimal_fb_div = fb_div;
+ *optimal_vclk_div = vclk_div;
+ *optimal_dclk_div = dclk_div;
+ optimal_score = score;
+ if (optimal_score == 0)
+ break; /* it can't get better than this */
+ }
+ }
+
+ /* did we found a valid setup ? */
+ if (optimal_score == ~0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev,
+ unsigned cg_upll_func_cntl)
+{
+ unsigned i;
+
+ /* make sure UPLL_CTLREQ is deasserted */
+ WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
+
+ mdelay(10);
+
+ /* assert UPLL_CTLREQ */
+ WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
+
+ /* wait for CTLACK and CTLACK2 to get asserted */
+ for (i = 0; i < 100; ++i) {
+ uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
+ if ((RREG32(cg_upll_func_cntl) & mask) == mask)
+ break;
+ mdelay(10);
+ }
+
+ /* deassert UPLL_CTLREQ */
+ WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
+
+ if (i == 100) {
+ DRM_ERROR("Timeout setting UVD clocks!\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
{
+ unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
+ int r;
+
+ /* bypass vclk and dclk with bclk */
+ WREG32_P(CG_UPLL_FUNC_CNTL_2,
+ VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
+ ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
+
+ /* put PLL in bypass mode */
+ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
+
+ if (!vclk || !dclk) {
+ /* keep the Bypass mode */
+ return 0;
+ }
+
+ r = si_uvd_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,
+ 16384, 0x03FFFFFF, 0, 128, 5,
+ &fb_div, &vclk_div, &dclk_div);
+
+ if (r)
+ return r;
+
+ /* set RESET_ANTI_MUX to 0 */
+ WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
+
+ /* set VCO_MODE to 1 */
+ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
+
+ /* disable sleep mode */
+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
+
+ /* deassert UPLL_RESET */
+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
+
+ mdelay(1);
+
+ r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
+ if (r)
+ return r;
+
+ /* assert UPLL_RESET again */
+ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
+
+ /* disable spread spectrum. */
+ WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
+
+ /* set feedback divider */
+ WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
+
+ /* set ref divider to 0 */
+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
+
+ if (fb_div < 307200)
+ WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
+ else
+ WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
+
+ /* set PDIV_A and PDIV_B */
+ WREG32_P(CG_UPLL_FUNC_CNTL_2,
+ UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
+ ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
+
+ /* give the PLL some time to settle */
+ mdelay(15);
+
+ /* deassert PLL_RESET */
+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
+
+ mdelay(15);
+
+ /* switch from bypass mode to normal mode */
+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
+
+ r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
+ if (r)
+ return r;
+
+ /* switch VCLK and DCLK selection */
+ WREG32_P(CG_UPLL_FUNC_CNTL_2,
+ VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
+ ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
+
+ mdelay(100);
+
return 0;
}
@@ -1260,8 +1504,8 @@ static int si_common_early_init(void *handle)
adev->pcie_wreg = &si_pcie_wreg;
adev->pciep_rreg = &si_pciep_rreg;
adev->pciep_wreg = &si_pciep_wreg;
- adev->uvd_ctx_rreg = NULL;
- adev->uvd_ctx_wreg = NULL;
+ adev->uvd_ctx_rreg = &si_uvd_ctx_rreg;
+ adev->uvd_ctx_wreg = &si_uvd_ctx_wreg;
adev->didt_rreg = NULL;
adev->didt_wreg = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index 42556e2fafd4..1fbe62e95c94 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -1621,27 +1621,7 @@
/*
* UVD
*/
-#define UVD_UDEC_ADDR_CONFIG 0x3bd3
-#define UVD_UDEC_DB_ADDR_CONFIG 0x3bd4
-#define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
-#define UVD_RBC_RB_RPTR 0x3da4
-#define UVD_RBC_RB_WPTR 0x3da5
-#define UVD_STATUS 0x3daf
-
-#define UVD_CGC_CTRL 0x3dc2
-# define DCM (1 << 0)
-# define CG_DT(x) ((x) << 2)
-# define CG_DT_MASK (0xf << 2)
-# define CLK_OD(x) ((x) << 6)
-# define CLK_OD_MASK (0x1f << 6)
-
- /* UVD CTX indirect */
-#define UVD_CGC_MEM_CTRL 0xC0
-#define UVD_CGC_CTRL2 0xC1
-# define DYN_OR_EN (1 << 0)
-# define DYN_RR_EN (1 << 1)
-# define G_DIV_ID(x) ((x) << 2)
-# define G_DIV_ID_MASK (0x7 << 2)
+#define UVD_VCPU_CHIP_ID 0x3d35
/*
* PM4
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
index cfa6959db43d..e5f5e19657fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
@@ -36,8 +36,12 @@
#include "bif/bif_3_0_d.h"
+static void uvd_v4_0_mc_resume(struct amdgpu_device *adev);
static void uvd_v4_0_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v4_0_set_irq_funcs(struct amdgpu_device *adev);
+static int uvd_v4_0_start(struct amdgpu_device *adev);
+static void uvd_v4_0_stop(struct amdgpu_device *adev);
+static void uvd_v4_0_set_dcm(struct amdgpu_device *adev, bool sw_mode);
/**
* uvd_v4_0_ring_get_rptr - get read pointer
@@ -114,6 +118,8 @@ static int uvd_v4_0_sw_init(void *handle)
sprintf(ring->name, "uvd");
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+ /* TODO: move mc programming to hw init */
+ uvd_v4_0_mc_resume(adev);
return r;
}
@@ -129,6 +135,333 @@ static int uvd_v4_0_sw_fini(void *handle)
return amdgpu_uvd_sw_fini(adev);
}
+static void uvd_v4_0_enable_mgcg(struct amdgpu_device *adev,
+ bool enable)
+{
+ u32 orig, data;
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
+ data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
+ data |= 0x3fff;
+ WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
+
+ orig = data = RREG32(mmUVD_CGC_CTRL);
+ data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+ if (orig != data)
+ WREG32(mmUVD_CGC_CTRL, data);
+
+ WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
+ WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
+ } else {
+ data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
+ data &= ~0x3fff;
+ WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
+
+ orig = data = RREG32(mmUVD_CGC_CTRL);
+ data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+ if (orig != data)
+ WREG32(mmUVD_CGC_CTRL, data);
+
+ WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
+ WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
+ }
+}
+
+/**
+ * uvd_v4_0_hw_init - start and test UVD block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Initialize the hardware, boot up the VCPU and do some testing
+ */
+static int uvd_v4_0_hw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring = &adev->uvd.ring;
+ uint32_t tmp;
+ int r;
+
+ uvd_v4_0_enable_mgcg(adev, true);
+ amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
+ uvd_v4_0_start(adev);
+
+ ring->ready = true;
+ r = amdgpu_ring_test_ring(ring);
+ if (r) {
+ ring->ready = false;
+ goto done;
+ }
+
+ r = amdgpu_ring_alloc(ring, 10);
+ if (r) {
+ DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
+ goto done;
+ }
+
+ tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0xFFFFF);
+
+ tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0xFFFFF);
+
+ tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0xFFFFF);
+
+ /* Clear timeout status bits */
+ amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
+ amdgpu_ring_write(ring, 0x8);
+
+ amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
+ amdgpu_ring_write(ring, 3);
+
+ amdgpu_ring_commit(ring);
+
+done:
+ if (!r)
+ DRM_INFO("UVD initialized successfully.\n");
+
+ return r;
+}
+
+/**
+ * uvd_v4_0_hw_fini - stop the hardware block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Stop the UVD block, mark ring as not ready any more
+ */
+static int uvd_v4_0_hw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring = &adev->uvd.ring;
+
+ if (RREG32(mmUVD_STATUS) != 0)
+ uvd_v4_0_stop(adev);
+
+ ring->ready = false;
+
+ return 0;
+}
+
+static int uvd_v4_0_suspend(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = uvd_v4_0_hw_fini(adev);
+ if (r)
+ return r;
+
+ return amdgpu_uvd_suspend(adev);
+}
+
+static int uvd_v4_0_resume(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = amdgpu_uvd_resume(adev);
+ if (r)
+ return r;
+
+ return uvd_v4_0_hw_init(adev);
+}
+
+/**
+ * uvd_v4_0_start - start UVD block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Setup and start the UVD block
+ */
+static int uvd_v4_0_start(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring = &adev->uvd.ring;
+ uint32_t rb_bufsz;
+ int i, j, r;
+ u32 tmp;
+ /* disable byte swapping */
+ u32 lmi_swap_cntl = 0;
+ u32 mp_swap_cntl = 0;
+
+ /* set uvd busy */
+ WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
+
+ uvd_v4_0_set_dcm(adev, true);
+ WREG32(mmUVD_CGC_GATE, 0);
+
+ /* take UVD block out of reset */
+ WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
+ mdelay(5);
+
+ /* enable VCPU clock */
+ WREG32(mmUVD_VCPU_CNTL, 1 << 9);
+
+ /* disable interupt */
+ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
+
+#ifdef __BIG_ENDIAN
+ /* swap (8 in 32) RB and IB */
+ lmi_swap_cntl = 0xa;
+ mp_swap_cntl = 0;
+#endif
+ WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
+ WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
+ /* initialize UVD memory controller */
+ WREG32(mmUVD_LMI_CTRL, 0x203108);
+
+ tmp = RREG32(mmUVD_MPC_CNTL);
+ WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
+
+ WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
+ WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
+ WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
+ WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
+ WREG32(mmUVD_MPC_SET_ALU, 0);
+ WREG32(mmUVD_MPC_SET_MUX, 0x88);
+
+ uvd_v4_0_mc_resume(adev);
+
+ tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
+ WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
+
+ /* enable UMC */
+ WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
+
+ WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
+
+ WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
+
+ WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+
+ mdelay(10);
+
+ for (i = 0; i < 10; ++i) {
+ uint32_t status;
+ for (j = 0; j < 100; ++j) {
+ status = RREG32(mmUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ }
+ r = 0;
+ if (status & 2)
+ break;
+
+ DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
+ WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+ mdelay(10);
+ WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+ mdelay(10);
+ r = -1;
+ }
+
+ if (r) {
+ DRM_ERROR("UVD not responding, giving up!!!\n");
+ return r;
+ }
+
+ /* enable interupt */
+ WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
+
+ WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
+
+ /* force RBC into idle state */
+ WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
+
+ /* Set the write pointer delay */
+ WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
+
+ /* programm the 4GB memory segment for rptr and ring buffer */
+ WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
+ (0x7 << 16) | (0x1 << 31));
+
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32(mmUVD_RBC_RB_RPTR, 0x0);
+
+ ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
+ WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
+
+ /* set the ring address */
+ WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
+
+ /* Set ring buffer size */
+ rb_bufsz = order_base_2(ring->ring_size);
+ rb_bufsz = (0x1 << 8) | rb_bufsz;
+ WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
+
+ return 0;
+}
+
+
+/**
+ * uvd_v4_0_stop - stop UVD block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * stop the UVD block
+ */
+static void uvd_v4_0_stop(struct amdgpu_device *adev)
+{
+ uint32_t i, j;
+ uint32_t status;
+
+ WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
+
+ for (i = 0; i < 10; ++i) {
+ for (j = 0; j < 100; ++j) {
+ status = RREG32(mmUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(1);
+ }
+ if (status & 2)
+ break;
+ }
+
+ for (i = 0; i < 10; ++i) {
+ for (j = 0; j < 100; ++j) {
+ status = RREG32(mmUVD_LMI_STATUS);
+ if (status & 0xf)
+ break;
+ mdelay(1);
+ }
+ if (status & 0xf)
+ break;
+ }
+
+ /* Stall UMC and register bus before resetting VCPU */
+ WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
+
+ for (i = 0; i < 10; ++i) {
+ for (j = 0; j < 100; ++j) {
+ status = RREG32(mmUVD_LMI_STATUS);
+ if (status & 0x240)
+ break;
+ mdelay(1);
+ }
+ if (status & 0x240)
+ break;
+ }
+
+ WREG32_P(0x3D49, 0, ~(1 << 2));
+
+ WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
+
+ /* put LMI, VCPU, RBC etc... into reset */
+ WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
+
+ WREG32(mmUVD_STATUS, 0);
+
+ uvd_v4_0_set_dcm(adev, false);
+}
+
/**
* uvd_v4_0_ring_emit_fence - emit an fence & trap command
*
@@ -245,6 +578,126 @@ static void uvd_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, ib->length_dw);
}
+/**
+ * uvd_v4_0_mc_resume - memory controller programming
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Let the UVD memory controller know it's offsets
+ */
+static void uvd_v4_0_mc_resume(struct amdgpu_device *adev)
+{
+ uint64_t addr;
+ uint32_t size, chip_id;
+ const struct common_firmware_header *hdr;
+
+ hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+ /* programm the VCPU memory controller bits 0-27 */
+ addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
+ size = (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) -
+ AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
+ WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
+ WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
+
+ addr += size;
+ size = AMDGPU_UVD_HEAP_SIZE >> 3;
+ WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
+ WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
+
+ addr += size;
+ size = (AMDGPU_UVD_STACK_SIZE +
+ (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
+ WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
+ WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
+
+ /* bits 28-31 */
+ addr = (adev->uvd.gpu_addr >> 28) & 0xF;
+ WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
+
+ /* bits 32-39 */
+ addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
+ WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
+
+ WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+ WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+ WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+
+ /* tell firmware which hardware it is running on */
+ switch (adev->asic_type) {
+ case CHIP_TAHITI:
+ chip_id = 0x01000014;
+ break;
+ case CHIP_VERDE:
+ chip_id = 0x01000015;
+ break;
+ case CHIP_PITCAIRN:
+ case CHIP_OLAND:
+ chip_id = 0x01000016;
+ break;
+ default:
+ return;
+ }
+ WREG32(UVD_VCPU_CHIP_ID, chip_id);
+}
+
+static void uvd_v4_0_set_dcm(struct amdgpu_device *adev,
+ bool sw_mode)
+{
+ u32 tmp, tmp2;
+
+ WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
+
+ tmp = RREG32(mmUVD_CGC_CTRL);
+ tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
+ tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
+ (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
+ (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
+
+ if (sw_mode) {
+ tmp &= ~0x7ffff800;
+ tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
+ UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
+ (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
+ } else {
+ tmp |= 0x7ffff800;
+ tmp2 = 0;
+ }
+
+ WREG32(mmUVD_CGC_CTRL, tmp);
+ WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
+}
+
+static bool uvd_v4_0_is_idle(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
+}
+
+static int uvd_v4_0_wait_for_idle(void *handle)
+{
+ unsigned i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
+ return 0;
+ }
+ return -ETIMEDOUT;
+}
+
+static int uvd_v4_0_soft_reset(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ uvd_v4_0_stop(adev);
+
+ WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
+ mdelay(5);
+
+ return uvd_v4_0_start(adev);
+}
+
static int uvd_v4_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned int type,
@@ -263,12 +716,47 @@ static int uvd_v4_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
+static int uvd_v4_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+{
+ return 0;
+}
+
+static int uvd_v4_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
+{
+ /* This doesn't actually powergate the UVD block.
+ * That's done in the dpm code via the SMC. This
+ * just re-inits the block as necessary. The actual
+ * gating still happens in the dpm code. We should
+ * revisit this when there is a cleaner line between
+ * the smc and the hw blocks
+ */
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (state == AMD_PG_STATE_GATE) {
+ uvd_v4_0_stop(adev);
+ return 0;
+ } else {
+ return uvd_v4_0_start(adev);
+ }
+}
+
static const struct amd_ip_funcs uvd_v4_0_ip_funcs = {
.name = "uvd_v4_0",
.early_init = uvd_v4_0_early_init,
.late_init = NULL,
.sw_init = uvd_v4_0_sw_init,
.sw_fini = uvd_v4_0_sw_fini,
+ .hw_init = uvd_v4_0_hw_init,
+ .hw_fini = uvd_v4_0_hw_fini,
+ .suspend = uvd_v4_0_suspend,
+ .resume = uvd_v4_0_resume,
+ .is_idle = uvd_v4_0_is_idle,
+ .wait_for_idle = uvd_v4_0_wait_for_idle,
+ .soft_reset = uvd_v4_0_soft_reset,
+ .set_clockgating_state = uvd_v4_0_set_clockgating_state,
+ .set_powergating_state = uvd_v4_0_set_powergating_state,
};
static const struct amdgpu_ring_funcs uvd_v4_0_ring_funcs = {
--
2.15.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 7/7] drm/amdgpu: enable UVD for SI
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (5 preceding siblings ...)
2017-11-08 22:38 ` [RFC 6/7] drm/amdgpu/uvd4: add hardware specific " Piotr Redlewski
@ 2017-11-08 22:38 ` Piotr Redlewski
2017-11-08 23:54 ` [RFC 0/7] UVD support for SI in amdgpu Alex Deucher
7 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-08 22:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++-
drivers/gpu/drm/amd/amdgpu/si.c | 5 +++--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6a025c476b37..5c1bae35d2aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -38,7 +38,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
amdgpu_amdkfd_gfx_v7.o
-amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
+amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o \
+ dce_v6_0.o si_dpm.o si_smc.o uvd_v4_0.o
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index bc6fd1ff4f86..0e0445602215 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -38,6 +38,7 @@
#include "gmc_v6_0.h"
#include "si_dma.h"
#include "dce_v6_0.h"
+#include "uvd_v4_0.h"
#include "si.h"
#include "dce_virtual.h"
#include "gca/gfx_6_0_d.h"
@@ -2214,7 +2215,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_dma_ip_block);
- /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
+ amdgpu_ip_block_add(adev, &uvd_v4_0_ip_block);
/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
case CHIP_OLAND:
@@ -2228,7 +2229,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_dma_ip_block);
- /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
+ amdgpu_ip_block_add(adev, &uvd_v4_0_ip_block);
/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
case CHIP_HAINAN:
--
2.15.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (6 preceding siblings ...)
2017-11-08 22:38 ` [RFC 7/7] drm/amdgpu: enable UVD for SI Piotr Redlewski
@ 2017-11-08 23:54 ` Alex Deucher
[not found] ` <CADnq5_Oc98DJ8+d-qAv5Q4GQ5aasw0s+tXgHjyMFtG4KCR1Z5w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
7 siblings, 1 reply; 24+ messages in thread
From: Alex Deucher @ 2017-11-08 23:54 UTC (permalink / raw)
To: Piotr Redlewski; +Cc: amd-gfx list
On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
> Hi,
>
> Following series implements UVD support for SI in amdgpu driver. Code is based
> on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
> it requires tahiti uvd firmware with added header - I've created simple script
> to produce exactly this, so if anyone is interested it can be found here:
> https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
>
> Code is based on amd-staging-drm-next branch in Alex's tree. After applying
> these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
> and mpv.
>
> Some comments/issues for the patches:
> 1. To make uvd work, I had to bring back fb location programming. Using location
> programmed by vbios, vram location is not available for uvd mc (at least on my
> machine) due to too wide address. Starting address is 40-bit long for fb, but
> uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
> in radeon driver)
Something else must be going on. The vram location is irrelevant with
respect to the limitations of UVD. I think the limitations with UVD
are more to do with the location of the active buffers relative to
each other rather than the absolute location of some aperture in the
GPU's address space. CI has the same limitation as I recall so there
is probably a bug somewhere. Windows has used the fb location as set
by the vbios since evergreen, so it definitely should work.
> 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
> offsets before starting other engines. Because of that I set it in .sw_init
> function. In my opinion this should be fixed as it generally doesn't follow
> amdgpu driver architecture (hardware setup during software setup stage) and
> probably will break suspending and resume (I didn't test it). As I mentioned,
> I couldn't figure out why this is happening, so I count on help with finding fix
> for this.
> 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
> this file is generated, so fix should be made wherever it is generated from. For
> now I removed offending lines just to silence the compiler warnings.
> 4. I'm not sure whether I choose the right version for the uvd. Existing code in
> si.c suggested that it should be 3.1, however I went with the 4.0, because for
> this version there are available new style headers.
I think the regs are pretty much the same between 3.x and 4.x so it
should be fine.
Alex
>
> Regards,
> Piotr
>
> Piotr Redlewski (7):
> drm/amdgpu: remove duplicated definitions of some of the SI registers
> drm/amdgpu/uvd4: fix some register's mask and shift definitions
> drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> drm/amdgpu: enable UVD for SI
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
> drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
> drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
> .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
> 13 files changed, 1273 insertions(+), 68 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
>
> --
> 2.15.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <CADnq5_Oc98DJ8+d-qAv5Q4GQ5aasw0s+tXgHjyMFtG4KCR1Z5w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-11-09 8:42 ` Christian König
[not found] ` <c2e6d813-401b-2bfc-6118-3df1c3e7c046-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-09 9:54 ` Piotr Redlewski
1 sibling, 1 reply; 24+ messages in thread
From: Christian König @ 2017-11-09 8:42 UTC (permalink / raw)
To: Alex Deucher, Piotr Redlewski; +Cc: amd-gfx list
Am 09.11.2017 um 00:54 schrieb Alex Deucher:
> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
>> Hi,
>>
>> Following series implements UVD support for SI in amdgpu driver. Code is based
>> on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
>> it requires tahiti uvd firmware with added header - I've created simple script
>> to produce exactly this, so if anyone is interested it can be found here:
>> https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
>>
>> Code is based on amd-staging-drm-next branch in Alex's tree. After applying
>> these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
>> and mpv.
>>
>> Some comments/issues for the patches:
>> 1. To make uvd work, I had to bring back fb location programming. Using location
>> programmed by vbios, vram location is not available for uvd mc (at least on my
>> machine) due to too wide address. Starting address is 40-bit long for fb, but
>> uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
>> in radeon driver)
> Something else must be going on. The vram location is irrelevant with
> respect to the limitations of UVD. I think the limitations with UVD
> are more to do with the location of the active buffers relative to
> each other rather than the absolute location of some aperture in the
> GPU's address space. CI has the same limitation as I recall so there
> is probably a bug somewhere. Windows has used the fb location as set
> by the vbios since evergreen, so it definitely should work.
>
>> 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
>> offsets before starting other engines. Because of that I set it in .sw_init
>> function. In my opinion this should be fixed as it generally doesn't follow
>> amdgpu driver architecture (hardware setup during software setup stage) and
>> probably will break suspending and resume (I didn't test it). As I mentioned,
>> I couldn't figure out why this is happening, so I count on help with finding fix
>> for this.
It's just that your initialization order is incorrect.
Try to add the UVD block a bit earlier (before the PP lib block I think)
in si_set_ip_blocks.
Regards,
Christian.
>> 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
>> this file is generated, so fix should be made wherever it is generated from. For
>> now I removed offending lines just to silence the compiler warnings.
>> 4. I'm not sure whether I choose the right version for the uvd. Existing code in
>> si.c suggested that it should be 3.1, however I went with the 4.0, because for
>> this version there are available new style headers.
> I think the regs are pretty much the same between 3.x and 4.x so it
> should be fine.
>
> Alex
>
>
>> Regards,
>> Piotr
>>
>> Piotr Redlewski (7):
>> drm/amdgpu: remove duplicated definitions of some of the SI registers
>> drm/amdgpu/uvd4: fix some register's mask and shift definitions
>> drm/amdgpu/gmc6: don't use vram location programmed by the vbios
>> drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
>> drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
>> drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
>> drm/amdgpu: enable UVD for SI
>>
>> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
>> drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
>> drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
>> .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
>> 13 files changed, 1273 insertions(+), 68 deletions(-)
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
>>
>> --
>> 2.15.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <CADnq5_Oc98DJ8+d-qAv5Q4GQ5aasw0s+tXgHjyMFtG4KCR1Z5w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-11-09 8:42 ` Christian König
@ 2017-11-09 9:54 ` Piotr Redlewski
[not found] ` <20171109095407.GA1481-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
1 sibling, 1 reply; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-09 9:54 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
> > Hi,
> >
> > Following series implements UVD support for SI in amdgpu driver. Code is based
> > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
> > it requires tahiti uvd firmware with added header - I've created simple script
> > to produce exactly this, so if anyone is interested it can be found here:
> > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> >
> > Code is based on amd-staging-drm-next branch in Alex's tree. After applying
> > these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
> > and mpv.
> >
> > Some comments/issues for the patches:
> > 1. To make uvd work, I had to bring back fb location programming. Using location
> > programmed by vbios, vram location is not available for uvd mc (at least on my
> > machine) due to too wide address. Starting address is 40-bit long for fb, but
> > uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
> > in radeon driver)
>
> Something else must be going on. The vram location is irrelevant with
> respect to the limitations of UVD. I think the limitations with UVD
> are more to do with the location of the active buffers relative to
> each other rather than the absolute location of some aperture in the
> GPU's address space. CI has the same limitation as I recall so there
> is probably a bug somewhere. Windows has used the fb location as set
> by the vbios since evergreen, so it definitely should work.
>
If this is the case, then there must be something missing in UVD mc controller
programming. When using vbios, I get following location:
amdgpu 0000:01:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
When UVD bo is created, it starts at address 0xf400243000 and this value is used
for programming UVD mc offsets. Programming is done in the following way:
addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
Because address of the bo is wider than 32-bit, this won't work. It would be the
same if UVD bo would be created at the beginning of the VRAM.
Any ideas how to handle this?
> > 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
> > offsets before starting other engines. Because of that I set it in .sw_init
> > function. In my opinion this should be fixed as it generally doesn't follow
> > amdgpu driver architecture (hardware setup during software setup stage) and
> > probably will break suspending and resume (I didn't test it). As I mentioned,
> > I couldn't figure out why this is happening, so I count on help with finding fix
> > for this.
> > 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
> > this file is generated, so fix should be made wherever it is generated from. For
> > now I removed offending lines just to silence the compiler warnings.
> > 4. I'm not sure whether I choose the right version for the uvd. Existing code in
> > si.c suggested that it should be 3.1, however I went with the 4.0, because for
> > this version there are available new style headers.
>
> I think the regs are pretty much the same between 3.x and 4.x so it
> should be fine.
Great.
Regards,
Piotr
>
> Alex
>
>
> >
> > Regards,
> > Piotr
> >
> > Piotr Redlewski (7):
> > drm/amdgpu: remove duplicated definitions of some of the SI registers
> > drm/amdgpu/uvd4: fix some register's mask and shift definitions
> > drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> > drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> > drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> > drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> > drm/amdgpu: enable UVD for SI
> >
> > drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
> > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
> > drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
> > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
> > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
> > drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
> > drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
> > drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
> > drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
> > .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
> > 13 files changed, 1273 insertions(+), 68 deletions(-)
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
> >
> > --
> > 2.15.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <20171109095407.GA1481-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
@ 2017-11-09 10:09 ` Christian König
[not found] ` <77b5d341-42e2-91bd-f586-747451cfe6d6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Christian König @ 2017-11-09 10:09 UTC (permalink / raw)
To: Piotr Redlewski, Alex Deucher; +Cc: amd-gfx list
Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
>> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
>>> Hi,
>>>
>>> Following series implements UVD support for SI in amdgpu driver. Code is based
>>> on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
>>> it requires tahiti uvd firmware with added header - I've created simple script
>>> to produce exactly this, so if anyone is interested it can be found here:
>>> https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
>>>
>>> Code is based on amd-staging-drm-next branch in Alex's tree. After applying
>>> these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
>>> and mpv.
>>>
>>> Some comments/issues for the patches:
>>> 1. To make uvd work, I had to bring back fb location programming. Using location
>>> programmed by vbios, vram location is not available for uvd mc (at least on my
>>> machine) due to too wide address. Starting address is 40-bit long for fb, but
>>> uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
>>> in radeon driver)
>> Something else must be going on. The vram location is irrelevant with
>> respect to the limitations of UVD. I think the limitations with UVD
>> are more to do with the location of the active buffers relative to
>> each other rather than the absolute location of some aperture in the
>> GPU's address space. CI has the same limitation as I recall so there
>> is probably a bug somewhere. Windows has used the fb location as set
>> by the vbios since evergreen, so it definitely should work.
>>
> If this is the case, then there must be something missing in UVD mc controller
> programming. When using vbios, I get following location:
> amdgpu 0000:01:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
>
> When UVD bo is created, it starts at address 0xf400243000 and this value is used
> for programming UVD mc offsets. Programming is done in the following way:
> addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
>
> Because address of the bo is wider than 32-bit, this won't work. It would be the
> same if UVD bo would be created at the beginning of the VRAM.
>
> Any ideas how to handle this?
Are you programming UVD_LMI_EXT40_ADDR?
But I'm not sure if we ever handled that correctly in the SI code.
Regards,
Christian.
>
>>> 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
>>> offsets before starting other engines. Because of that I set it in .sw_init
>>> function. In my opinion this should be fixed as it generally doesn't follow
>>> amdgpu driver architecture (hardware setup during software setup stage) and
>>> probably will break suspending and resume (I didn't test it). As I mentioned,
>>> I couldn't figure out why this is happening, so I count on help with finding fix
>>> for this.
>>> 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
>>> this file is generated, so fix should be made wherever it is generated from. For
>>> now I removed offending lines just to silence the compiler warnings.
>>> 4. I'm not sure whether I choose the right version for the uvd. Existing code in
>>> si.c suggested that it should be 3.1, however I went with the 4.0, because for
>>> this version there are available new style headers.
>> I think the regs are pretty much the same between 3.x and 4.x so it
>> should be fine.
> Great.
>
> Regards,
> Piotr
>> Alex
>>
>>
>>> Regards,
>>> Piotr
>>>
>>> Piotr Redlewski (7):
>>> drm/amdgpu: remove duplicated definitions of some of the SI registers
>>> drm/amdgpu/uvd4: fix some register's mask and shift definitions
>>> drm/amdgpu/gmc6: don't use vram location programmed by the vbios
>>> drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
>>> drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
>>> drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
>>> drm/amdgpu: enable UVD for SI
>>>
>>> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
>>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
>>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
>>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
>>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
>>> drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
>>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
>>> drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
>>> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
>>> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
>>> .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
>>> 13 files changed, 1273 insertions(+), 68 deletions(-)
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
>>>
>>> --
>>> 2.15.0
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <77b5d341-42e2-91bd-f586-747451cfe6d6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-11-09 10:53 ` Piotr Redlewski
[not found] ` <20171109105316.GA616-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-09 10:53 UTC (permalink / raw)
To: christian.koenig-5C7GfCeVMHo; +Cc: Alex Deucher, amd-gfx list
On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> > On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> > > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
> > > > Hi,
> > > >
> > > > Following series implements UVD support for SI in amdgpu driver. Code is based
> > > > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
> > > > it requires tahiti uvd firmware with added header - I've created simple script
> > > > to produce exactly this, so if anyone is interested it can be found here:
> > > > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> > > >
> > > > Code is based on amd-staging-drm-next branch in Alex's tree. After applying
> > > > these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
> > > > and mpv.
> > > >
> > > > Some comments/issues for the patches:
> > > > 1. To make uvd work, I had to bring back fb location programming. Using location
> > > > programmed by vbios, vram location is not available for uvd mc (at least on my
> > > > machine) due to too wide address. Starting address is 40-bit long for fb, but
> > > > uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
> > > > in radeon driver)
> > > Something else must be going on. The vram location is irrelevant with
> > > respect to the limitations of UVD. I think the limitations with UVD
> > > are more to do with the location of the active buffers relative to
> > > each other rather than the absolute location of some aperture in the
> > > GPU's address space. CI has the same limitation as I recall so there
> > > is probably a bug somewhere. Windows has used the fb location as set
> > > by the vbios since evergreen, so it definitely should work.
> > >
> > If this is the case, then there must be something missing in UVD mc controller
> > programming. When using vbios, I get following location:
> > amdgpu 0000:01:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
> >
> > When UVD bo is created, it starts at address 0xf400243000 and this value is used
> > for programming UVD mc offsets. Programming is done in the following way:
> > addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> > WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
> >
> > Because address of the bo is wider than 32-bit, this won't work. It would be the
> > same if UVD bo would be created at the beginning of the VRAM.
> >
> > Any ideas how to handle this?
>
> Are you programming UVD_LMI_EXT40_ADDR?
>
> But I'm not sure if we ever handled that correctly in the SI code.
Yes, I do it exactly the same as it is done in radeon (and CIK in amdgpu):
/* bits 32-39 */
addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
Regards,
Piotr
>
> Regards,
> Christian.
>
> >
> > > > 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
> > > > offsets before starting other engines. Because of that I set it in .sw_init
> > > > function. In my opinion this should be fixed as it generally doesn't follow
> > > > amdgpu driver architecture (hardware setup during software setup stage) and
> > > > probably will break suspending and resume (I didn't test it). As I mentioned,
> > > > I couldn't figure out why this is happening, so I count on help with finding fix
> > > > for this.
> > > > 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
> > > > this file is generated, so fix should be made wherever it is generated from. For
> > > > now I removed offending lines just to silence the compiler warnings.
> > > > 4. I'm not sure whether I choose the right version for the uvd. Existing code in
> > > > si.c suggested that it should be 3.1, however I went with the 4.0, because for
> > > > this version there are available new style headers.
> > > I think the regs are pretty much the same between 3.x and 4.x so it
> > > should be fine.
> > Great.
> >
> > Regards,
> > Piotr
> > > Alex
> > >
> > >
> > > > Regards,
> > > > Piotr
> > > >
> > > > Piotr Redlewski (7):
> > > > drm/amdgpu: remove duplicated definitions of some of the SI registers
> > > > drm/amdgpu/uvd4: fix some register's mask and shift definitions
> > > > drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> > > > drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> > > > drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> > > > drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> > > > drm/amdgpu: enable UVD for SI
> > > >
> > > > drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> > > > drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
> > > > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
> > > > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
> > > > drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
> > > > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
> > > > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
> > > > drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
> > > > drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
> > > > drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
> > > > drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
> > > > drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
> > > > .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
> > > > 13 files changed, 1273 insertions(+), 68 deletions(-)
> > > > create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
> > > > create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
> > > >
> > > > --
> > > > 2.15.0
> > > >
> > > > _______________________________________________
> > > > amd-gfx mailing list
> > > > amd-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <20171109105316.GA616-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
@ 2017-11-09 12:17 ` Christian König
[not found] ` <ffb4d853-1ec8-af2c-8622-26fc0e3a373b-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Christian König @ 2017-11-09 12:17 UTC (permalink / raw)
To: Piotr Redlewski; +Cc: Alex Deucher, amd-gfx list
Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:
> On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
>> Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
>>> On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
>>>> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
>>>>> Hi,
>>>>>
>>>>> Following series implements UVD support for SI in amdgpu driver. Code is based
>>>>> on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
>>>>> it requires tahiti uvd firmware with added header - I've created simple script
>>>>> to produce exactly this, so if anyone is interested it can be found here:
>>>>> https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
>>>>>
>>>>> Code is based on amd-staging-drm-next branch in Alex's tree. After applying
>>>>> these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
>>>>> and mpv.
>>>>>
>>>>> Some comments/issues for the patches:
>>>>> 1. To make uvd work, I had to bring back fb location programming. Using location
>>>>> programmed by vbios, vram location is not available for uvd mc (at least on my
>>>>> machine) due to too wide address. Starting address is 40-bit long for fb, but
>>>>> uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
>>>>> in radeon driver)
>>>> Something else must be going on. The vram location is irrelevant with
>>>> respect to the limitations of UVD. I think the limitations with UVD
>>>> are more to do with the location of the active buffers relative to
>>>> each other rather than the absolute location of some aperture in the
>>>> GPU's address space. CI has the same limitation as I recall so there
>>>> is probably a bug somewhere. Windows has used the fb location as set
>>>> by the vbios since evergreen, so it definitely should work.
>>>>
>>> If this is the case, then there must be something missing in UVD mc controller
>>> programming. When using vbios, I get following location:
>>> amdgpu 0000:01:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
>>>
>>> When UVD bo is created, it starts at address 0xf400243000 and this value is used
>>> for programming UVD mc offsets. Programming is done in the following way:
>>> addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
>>> WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
>>>
>>> Because address of the bo is wider than 32-bit, this won't work. It would be the
>>> same if UVD bo would be created at the beginning of the VRAM.
>>>
>>> Any ideas how to handle this?
>> Are you programming UVD_LMI_EXT40_ADDR?
>>
>> But I'm not sure if we ever handled that correctly in the SI code.
> Yes, I do it exactly the same as it is done in radeon (and CIK in amdgpu):
> /* bits 32-39 */
> addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
> WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
Ok, I've checked the firmware in the meantime and found that we never
released firmware which supports the full 40bit addressing.
That's why this will never work correctly. Going to check if we can get
updated firmware out of the door.
Regards,
Christian.
>
> Regards,
> Piotr
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <ffb4d853-1ec8-af2c-8622-26fc0e3a373b-5C7GfCeVMHo@public.gmane.org>
@ 2017-11-09 14:25 ` Piotr Redlewski
0 siblings, 0 replies; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-09 14:25 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, amd-gfx list
On Thu, Nov 09, 2017 at 01:17:36PM +0100, Christian König wrote:
> Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:
> > On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> > > Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> > > > On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> > > > > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
> > > > > > Hi,
> > > > > >
> > > > > > Following series implements UVD support for SI in amdgpu driver. Code is based
> > > > > > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
> > > > > > it requires tahiti uvd firmware with added header - I've created simple script
> > > > > > to produce exactly this, so if anyone is interested it can be found here:
> > > > > > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> > > > > >
> > > > > > Code is based on amd-staging-drm-next branch in Alex's tree. After applying
> > > > > > these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
> > > > > > and mpv.
> > > > > >
> > > > > > Some comments/issues for the patches:
> > > > > > 1. To make uvd work, I had to bring back fb location programming. Using location
> > > > > > programmed by vbios, vram location is not available for uvd mc (at least on my
> > > > > > machine) due to too wide address. Starting address is 40-bit long for fb, but
> > > > > > uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
> > > > > > in radeon driver)
> > > > > Something else must be going on. The vram location is irrelevant with
> > > > > respect to the limitations of UVD. I think the limitations with UVD
> > > > > are more to do with the location of the active buffers relative to
> > > > > each other rather than the absolute location of some aperture in the
> > > > > GPU's address space. CI has the same limitation as I recall so there
> > > > > is probably a bug somewhere. Windows has used the fb location as set
> > > > > by the vbios since evergreen, so it definitely should work.
> > > > >
> > > > If this is the case, then there must be something missing in UVD mc controller
> > > > programming. When using vbios, I get following location:
> > > > amdgpu 0000:01:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
> > > >
> > > > When UVD bo is created, it starts at address 0xf400243000 and this value is used
> > > > for programming UVD mc offsets. Programming is done in the following way:
> > > > addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> > > > WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
> > > >
> > > > Because address of the bo is wider than 32-bit, this won't work. It would be the
> > > > same if UVD bo would be created at the beginning of the VRAM.
> > > >
> > > > Any ideas how to handle this?
> > > Are you programming UVD_LMI_EXT40_ADDR?
> > >
> > > But I'm not sure if we ever handled that correctly in the SI code.
> > Yes, I do it exactly the same as it is done in radeon (and CIK in amdgpu):
> > /* bits 32-39 */
> > addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
> > WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
>
> Ok, I've checked the firmware in the meantime and found that we never
> released firmware which supports the full 40bit addressing.
>
> That's why this will never work correctly. Going to check if we can get
> updated firmware out of the door.
Ok, so let's wait for the new firmware. Thanks for your help Christian.
Regards,
Piotr
>
> Regards,
> Christian.
>
> >
> > Regards,
> > Piotr
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <c2e6d813-401b-2bfc-6118-3df1c3e7c046-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-11-09 14:37 ` Piotr Redlewski
[not found] ` <20171109143743.GB547-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Piotr Redlewski @ 2017-11-09 14:37 UTC (permalink / raw)
To: christian.koenig-5C7GfCeVMHo; +Cc: Alex Deucher, amd-gfx list
On Thu, Nov 09, 2017 at 09:42:57AM +0100, Christian König wrote:
> Am 09.11.2017 um 00:54 schrieb Alex Deucher:
> > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
> > > Hi,
> > >
> > > Following series implements UVD support for SI in amdgpu driver. Code is based
> > > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
> > > it requires tahiti uvd firmware with added header - I've created simple script
> > > to produce exactly this, so if anyone is interested it can be found here:
> > > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> > >
> > > Code is based on amd-staging-drm-next branch in Alex's tree. After applying
> > > these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
> > > and mpv.
> > >
> > > Some comments/issues for the patches:
> > > 1. To make uvd work, I had to bring back fb location programming. Using location
> > > programmed by vbios, vram location is not available for uvd mc (at least on my
> > > machine) due to too wide address. Starting address is 40-bit long for fb, but
> > > uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
> > > in radeon driver)
> > Something else must be going on. The vram location is irrelevant with
> > respect to the limitations of UVD. I think the limitations with UVD
> > are more to do with the location of the active buffers relative to
> > each other rather than the absolute location of some aperture in the
> > GPU's address space. CI has the same limitation as I recall so there
> > is probably a bug somewhere. Windows has used the fb location as set
> > by the vbios since evergreen, so it definitely should work.
> >
> > > 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
> > > offsets before starting other engines. Because of that I set it in .sw_init
> > > function. In my opinion this should be fixed as it generally doesn't follow
> > > amdgpu driver architecture (hardware setup during software setup stage) and
> > > probably will break suspending and resume (I didn't test it). As I mentioned,
> > > I couldn't figure out why this is happening, so I count on help with finding fix
> > > for this.
>
> It's just that your initialization order is incorrect.
>
> Try to add the UVD block a bit earlier (before the PP lib block I think) in
> si_set_ip_blocks.
Unfortunately it looks that's not it. I've tried to move up the UVD block in
the blocks' list, and no matter where it is put it won't boot without
configuring UVD mc in the software init phase. Moreover, even with UVD mc
initialization in the software init, UVD won't boot when placed before gfx
block. I don't know whether this means anything.
Any other ideas?
Regards,
Piotr
>
> Regards,
> Christian.
>
> > > 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
> > > this file is generated, so fix should be made wherever it is generated from. For
> > > now I removed offending lines just to silence the compiler warnings.
> > > 4. I'm not sure whether I choose the right version for the uvd. Existing code in
> > > si.c suggested that it should be 3.1, however I went with the 4.0, because for
> > > this version there are available new style headers.
> > I think the regs are pretty much the same between 3.x and 4.x so it
> > should be fine.
> >
> > Alex
> >
> >
> > > Regards,
> > > Piotr
> > >
> > > Piotr Redlewski (7):
> > > drm/amdgpu: remove duplicated definitions of some of the SI registers
> > > drm/amdgpu/uvd4: fix some register's mask and shift definitions
> > > drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> > > drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> > > drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> > > drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> > > drm/amdgpu: enable UVD for SI
> > >
> > > drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
> > > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
> > > drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
> > > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
> > > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
> > > drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
> > > drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
> > > drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
> > > drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
> > > drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
> > > .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
> > > 13 files changed, 1273 insertions(+), 68 deletions(-)
> > > create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
> > > create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
> > >
> > > --
> > > 2.15.0
> > >
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <20171109143743.GB547-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
@ 2017-11-09 14:44 ` Christian König
0 siblings, 0 replies; 24+ messages in thread
From: Christian König @ 2017-11-09 14:44 UTC (permalink / raw)
To: Piotr Redlewski; +Cc: Alex Deucher, amd-gfx list
Am 09.11.2017 um 15:37 schrieb Piotr Redlewski:
> On Thu, Nov 09, 2017 at 09:42:57AM +0100, Christian König wrote:
>> Am 09.11.2017 um 00:54 schrieb Alex Deucher:
>>> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski@gmail.com> wrote:
>>>> Hi,
>>>>
>>>> Following series implements UVD support for SI in amdgpu driver. Code is based
>>>> on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
>>>> it requires tahiti uvd firmware with added header - I've created simple script
>>>> to produce exactly this, so if anyone is interested it can be found here:
>>>> https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
>>>>
>>>> Code is based on amd-staging-drm-next branch in Alex's tree. After applying
>>>> these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
>>>> and mpv.
>>>>
>>>> Some comments/issues for the patches:
>>>> 1. To make uvd work, I had to bring back fb location programming. Using location
>>>> programmed by vbios, vram location is not available for uvd mc (at least on my
>>>> machine) due to too wide address. Starting address is 40-bit long for fb, but
>>>> uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
>>>> in radeon driver)
>>> Something else must be going on. The vram location is irrelevant with
>>> respect to the limitations of UVD. I think the limitations with UVD
>>> are more to do with the location of the active buffers relative to
>>> each other rather than the absolute location of some aperture in the
>>> GPU's address space. CI has the same limitation as I recall so there
>>> is probably a bug somewhere. Windows has used the fb location as set
>>> by the vbios since evergreen, so it definitely should work.
>>>
>>>> 2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
>>>> offsets before starting other engines. Because of that I set it in .sw_init
>>>> function. In my opinion this should be fixed as it generally doesn't follow
>>>> amdgpu driver architecture (hardware setup during software setup stage) and
>>>> probably will break suspending and resume (I didn't test it). As I mentioned,
>>>> I couldn't figure out why this is happening, so I count on help with finding fix
>>>> for this.
>> It's just that your initialization order is incorrect.
>>
>> Try to add the UVD block a bit earlier (before the PP lib block I think) in
>> si_set_ip_blocks.
> Unfortunately it looks that's not it. I've tried to move up the UVD block in
> the blocks' list, and no matter where it is put it won't boot without
> configuring UVD mc in the software init phase. Moreover, even with UVD mc
> initialization in the software init, UVD won't boot when placed before gfx
> block. I don't know whether this means anything.
>
> Any other ideas?
Yeah, I see this won't work without further modifications.
Need to discuss internally how we want to fix this.
Going to leave you a note when I know more,
Christian.
>
> Regards,
> Piotr
>
>> Regards,
>> Christian.
>>
>>>> 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
>>>> this file is generated, so fix should be made wherever it is generated from. For
>>>> now I removed offending lines just to silence the compiler warnings.
>>>> 4. I'm not sure whether I choose the right version for the uvd. Existing code in
>>>> si.c suggested that it should be 3.1, however I went with the 4.0, because for
>>>> this version there are available new style headers.
>>> I think the regs are pretty much the same between 3.x and 4.x so it
>>> should be fine.
>>>
>>> Alex
>>>
>>>
>>>> Regards,
>>>> Piotr
>>>>
>>>> Piotr Redlewski (7):
>>>> drm/amdgpu: remove duplicated definitions of some of the SI registers
>>>> drm/amdgpu/uvd4: fix some register's mask and shift definitions
>>>> drm/amdgpu/gmc6: don't use vram location programmed by the vbios
>>>> drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
>>>> drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
>>>> drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
>>>> drm/amdgpu: enable UVD for SI
>>>>
>>>> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +
>>>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 114 ++-
>>>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 5 +
>>>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 -
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 40 +-
>>>> drivers/gpu/drm/amd/amdgpu/si.c | 256 ++++++-
>>>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +
>>>> drivers/gpu/drm/amd/amdgpu/sid.h | 52 +-
>>>> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c | 810 +++++++++++++++++++++
>>>> drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h | 29 +
>>>> .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -
>>>> 13 files changed, 1273 insertions(+), 68 deletions(-)
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h
>>>>
>>>> --
>>>> 2.15.0
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
2019-12-05 15:32 ` Deucher, Alexander
@ 2020-01-04 22:45 ` Alexandre Demers
0 siblings, 0 replies; 24+ messages in thread
From: Alexandre Demers @ 2020-01-04 22:45 UTC (permalink / raw)
To: Deucher, Alexander, Christian König, Matthew Taylor, amd-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3481 bytes --]
Hi there,
As you may remember, I was working on porting VCE 1.0 to amdgpu around
the time Piotr Redlewski sent the UVD patches. I would prefer to go the
way proposed by Alex Deucher than to see SI support being dropped. I've
been using the amdgpu on a 280X ever since it was possible. While there
were some quirks in the beginning, it is plenty usable and performant
ever since.
Also, using amdgpu comes with some benefits unavailable with the radeon
driver on a gaming perspective.
Now, if my work on porting VCE 1.0 has stalled, it's because I'm now a
father and I had only so little time to work on it. The code I was
working on is still dormant (some of it was sent on my github repo) and
I'm pretty sure I was almost done with it.
Please, don't drop SI support from amdgpu. If it was only for me, amdgpu
would be the default driver over radeon and people missing the UVD and
VCE features should be the ones overriding the default choice. But this
may not work for the majority (I don't know) and I understand that
radeon is still the default for GCN 1.0/1.1.
Cheers,
Alexandre Demers
On 2019-12-05 10:32, Deucher, Alexander wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> You could enable UVD support on amdgpu using the original firmware
> from radeon, but you'd have to adjust the memory map on the GPU for SI
> to match radeon. So updated firmware is not a requirement per se,
> it's just needed to keep the memory map the same as other GPUs.
>
> Alex
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of
> Christian König <ckoenig.leichtzumerken@gmail.com>
> *Sent:* Thursday, December 5, 2019 10:19 AM
> *To:* Matthew Taylor <mat@sharrow.me.uk>;
> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
> *Subject:* Re: [RFC 0/7] UVD support for SI in amdgpu
> Hi Matthew,
>
> Am 05.12.19 um 15:16 schrieb Matthew Taylor:
>> Hi,
>>
>> Back in November 2017, Piotr Redlewski, provided some patches for UVD
>> support in the SI cards, the thread had the same subject as this
>> message.
>>
>> The outcome of a conversation between himself and other developers on
>> the list was to wait for something in updated firmware. As this was
>> over 2 years ago, I was wondering if the firmware has been updated
>> sufficiently for Piotr's patches to be reconsidered or modified to
>> deliver the UVD support for the SI cards?
>
> we discussed that internally quite lengthy and the firmware will
> probably never be released.
>
> To be honest we actually considering dropping SI support completely
> from amdgpu.
>
> Regards,
> Christian.
>
>>
>> Thanks for you help
>>
>> Kind Regards
>>
>> Matthew Taylor
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org <mailto:amd-gfx@lists.freedesktop.org>
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx <https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C14121ef4f0a049ddc3ea08d77996852f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637111559776723411&sdata=SpbvepoL17ImHwW7V5spbH46ze%2FNp7ll%2FqV86kE%2BBfU%3D&reserved=0>
>
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
2019-12-05 15:19 ` Christian König
@ 2019-12-05 15:32 ` Deucher, Alexander
2020-01-04 22:45 ` Alexandre Demers
0 siblings, 1 reply; 24+ messages in thread
From: Deucher, Alexander @ 2019-12-05 15:32 UTC (permalink / raw)
To: Christian König, Matthew Taylor, amd-gfx
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[AMD Official Use Only - Internal Distribution Only]
You could enable UVD support on amdgpu using the original firmware from radeon, but you'd have to adjust the memory map on the GPU for SI to match radeon. So updated firmware is not a requirement per se, it's just needed to keep the memory map the same as other GPUs.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Christian König <ckoenig.leichtzumerken@gmail.com>
Sent: Thursday, December 5, 2019 10:19 AM
To: Matthew Taylor <mat@sharrow.me.uk>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [RFC 0/7] UVD support for SI in amdgpu
Hi Matthew,
Am 05.12.19 um 15:16 schrieb Matthew Taylor:
Hi,
Back in November 2017, Piotr Redlewski, provided some patches for UVD support in the SI cards, the thread had the same subject as this message.
The outcome of a conversation between himself and other developers on the list was to wait for something in updated firmware. As this was over 2 years ago, I was wondering if the firmware has been updated sufficiently for Piotr's patches to be reconsidered or modified to deliver the UVD support for the SI cards?
we discussed that internally quite lengthy and the firmware will probably never be released.
To be honest we actually considering dropping SI support completely from amdgpu.
Regards,
Christian.
Thanks for you help
Kind Regards
Matthew Taylor
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
2019-12-05 14:16 Matthew Taylor
@ 2019-12-05 15:19 ` Christian König
2019-12-05 15:32 ` Deucher, Alexander
0 siblings, 1 reply; 24+ messages in thread
From: Christian König @ 2019-12-05 15:19 UTC (permalink / raw)
To: Matthew Taylor, amd-gfx
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Hi Matthew,
Am 05.12.19 um 15:16 schrieb Matthew Taylor:
> Hi,
>
> Back in November 2017, Piotr Redlewski, provided some patches for UVD
> support in the SI cards, the thread had the same subject as this message.
>
> The outcome of a conversation between himself and other developers on
> the list was to wait for something in updated firmware. As this was
> over 2 years ago, I was wondering if the firmware has been updated
> sufficiently for Piotr's patches to be reconsidered or modified to
> deliver the UVD support for the SI cards?
we discussed that internally quite lengthy and the firmware will
probably never be released.
To be honest we actually considering dropping SI support completely from
amdgpu.
Regards,
Christian.
>
> Thanks for you help
>
> Kind Regards
>
> Matthew Taylor
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [RFC 0/7] UVD support for SI in amdgpu
@ 2019-12-05 14:16 Matthew Taylor
2019-12-05 15:19 ` Christian König
0 siblings, 1 reply; 24+ messages in thread
From: Matthew Taylor @ 2019-12-05 14:16 UTC (permalink / raw)
To: amd-gfx
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Hi,
Back in November 2017, Piotr Redlewski, provided some patches for UVD
support in the SI cards, the thread had the same subject as this message.
The outcome of a conversation between himself and other developers on the
list was to wait for something in updated firmware. As this was over 2
years ago, I was wondering if the firmware has been updated sufficiently
for Piotr's patches to be reconsidered or modified to deliver the UVD
support for the SI cards?
Thanks for you help
Kind Regards
Matthew Taylor
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
[not found] ` <DM5PR01MB26993AD32256C0F95A140D339BB20-o+Qcv1auejyUPCpdaV7NxV5F3wEVaoLpobIHt/V7iKVBDgjK7y7TUQ@public.gmane.org>
@ 2018-12-31 15:19 ` Alex Deucher
0 siblings, 0 replies; 24+ messages in thread
From: Alex Deucher @ 2018-12-31 15:19 UTC (permalink / raw)
To: Nikos Fytilis; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Dec 31, 2018 at 10:02 AM Nikos Fytilis <n-fit@live.com> wrote:
>
> Hi,
>
> Last message about these patches was about waiting for a firmware blob. Whatever did happen to them and are they functional?
We haven't had time to delve into reworking the firmware to handle the
address space changes, so if someone wants to pursue UVD support for
SI on amdgpu, it's probably easiest to just port the radeon code
directly and put vram at 0 in the internal address space like radeon
does for SI.
Alex
>
> Thanks for your efforts,
> Nikos
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
@ 2018-12-31 14:51 Nikos Fytilis
[not found] ` <DM5PR01MB26993AD32256C0F95A140D339BB20-o+Qcv1auejyUPCpdaV7NxV5F3wEVaoLpobIHt/V7iKVBDgjK7y7TUQ@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Nikos Fytilis @ 2018-12-31 14:51 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
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Hi,
Last message about these patches was about waiting for a firmware blob. Whatever did happen to them and are they functional?
Thanks for your efforts,
Nikos
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 0/7] UVD support for SI in amdgpu
@ 2018-10-27 10:53 Federico Cuello
0 siblings, 0 replies; 24+ messages in thread
From: Federico Cuello @ 2018-10-27 10:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
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> Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:
> > On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> >> Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> >>> On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> >>>> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski <predlewski at
gmail.com> wrote:
> >>>>> Hi,
> >>>>>
> >>>>> Following series implements UVD support for SI in amdgpu driver.
Code is based
> >>>>> on CIK's UVD support in amdgpu and SI's UVD support in radeon
drivers. To work,
> >>>>> it requires tahiti uvd firmware with added header - I've created
simple script
> >>>>> to produce exactly this, so if anyone is interested it can be found
here:
> >>>>> https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> >>>>>
> >>>>> Code is based on amd-staging-drm-next branch in Alex's tree. After
applying
> >>>>> these patches, uvd boots up and seems to work ok. I've tested it
with vdpauinfo
> >>>>> and mpv.
> >>>>>
> >>>>> Some comments/issues for the patches:
> >>>>> 1. To make uvd work, I had to bring back fb location programming.
Using location
> >>>>> programmed by vbios, vram location is not available for uvd mc (at
least on my
> >>>>> machine) due to too wide address. Starting address is 40-bit long
for fb, but
> >>>>> uvd mc supports only 32-bits (judging by comments in amdgpu code
and actual code
> >>>>> in radeon driver)
> >>>> Something else must be going on. The vram location is irrelevant
with
> >>>> respect to the limitations of UVD. I think the limitations with UVD
> >>>> are more to do with the location of the active buffers relative to
> >>>> each other rather than the absolute location of some aperture in the
> >>>> GPU's address space. CI has the same limitation as I recall so there
> >>>> is probably a bug somewhere. Windows has used the fb location as set
> >>>> by the vbios since evergreen, so it definitely should work.
> >>>>
> >>> If this is the case, then there must be something missing in UVD mc
controller
> >>> programming. When using vbios, I get following location:
> >>> amdgpu 0000:01:00.0: VRAM: 2048M 0x000000F400000000 -
0x000000F47FFFFFFF (2048M used)
> >>>
> >>> When UVD bo is created, it starts at address 0xf400243000 and this
value is used
> >>> for programming UVD mc offsets. Programming is done in the following
way:
> >>> addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> >>> WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
> >>>
> >>> Because address of the bo is wider than 32-bit, this won't work. It
would be the
> >>> same if UVD bo would be created at the beginning of the VRAM.
> >>>
> >>> Any ideas how to handle this?
> >> Are you programming UVD_LMI_EXT40_ADDR?
> >>
> >> But I'm not sure if we ever handled that correctly in the SI code.
> > Yes, I do it exactly the same as it is done in radeon (and CIK in
amdgpu):
> > /* bits 32-39 */
> > addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
> > WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
>
> Ok, I've checked the firmware in the meantime and found that we never
> released firmware which supports the full 40bit addressing.
>
> That's why this will never work correctly. Going to check if we can get
> updated firmware out of the door.
Hi Christian,
Did you manage to publish the updated firmware? I can't see it in the
linux-firmware tree.
Thanks,
Federico
> Regards,
> Christian.
>
> >
> > Regards,
> > Piotr
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^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2020-01-04 22:45 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-08 22:38 [RFC 0/7] UVD support for SI in amdgpu Piotr Redlewski
[not found] ` <20171108223839.579-1-predlewski-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-08 22:38 ` [RFC 1/7] drm/amdgpu: remove duplicated definitions of some of the SI registers Piotr Redlewski
2017-11-08 22:38 ` [RFC 2/7] drm/amdgpu/uvd4: fix some register's mask and shift definitions Piotr Redlewski
2017-11-08 22:38 ` [RFC 3/7] drm/amdgpu/gmc6: don't use vram location programmed by the vbios Piotr Redlewski
2017-11-08 22:38 ` [RFC 4/7] drm/amdgpu/uvd4: add early init stage functions for uvd 4.0 Piotr Redlewski
2017-11-08 22:38 ` [RFC 5/7] drm/amdgpu/uvd4: add sw init and fini stages' " Piotr Redlewski
2017-11-08 22:38 ` [RFC 6/7] drm/amdgpu/uvd4: add hardware specific " Piotr Redlewski
2017-11-08 22:38 ` [RFC 7/7] drm/amdgpu: enable UVD for SI Piotr Redlewski
2017-11-08 23:54 ` [RFC 0/7] UVD support for SI in amdgpu Alex Deucher
[not found] ` <CADnq5_Oc98DJ8+d-qAv5Q4GQ5aasw0s+tXgHjyMFtG4KCR1Z5w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-11-09 8:42 ` Christian König
[not found] ` <c2e6d813-401b-2bfc-6118-3df1c3e7c046-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-09 14:37 ` Piotr Redlewski
[not found] ` <20171109143743.GB547-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
2017-11-09 14:44 ` Christian König
2017-11-09 9:54 ` Piotr Redlewski
[not found] ` <20171109095407.GA1481-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
2017-11-09 10:09 ` Christian König
[not found] ` <77b5d341-42e2-91bd-f586-747451cfe6d6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-09 10:53 ` Piotr Redlewski
[not found] ` <20171109105316.GA616-vEgOWn/6yzlBufL/7O8DmyZi+YwRKgec@public.gmane.org>
2017-11-09 12:17 ` Christian König
[not found] ` <ffb4d853-1ec8-af2c-8622-26fc0e3a373b-5C7GfCeVMHo@public.gmane.org>
2017-11-09 14:25 ` Piotr Redlewski
2018-10-27 10:53 Federico Cuello
2018-12-31 14:51 Nikos Fytilis
[not found] ` <DM5PR01MB26993AD32256C0F95A140D339BB20-o+Qcv1auejyUPCpdaV7NxV5F3wEVaoLpobIHt/V7iKVBDgjK7y7TUQ@public.gmane.org>
2018-12-31 15:19 ` Alex Deucher
2019-12-05 14:16 Matthew Taylor
2019-12-05 15:19 ` Christian König
2019-12-05 15:32 ` Deucher, Alexander
2020-01-04 22:45 ` Alexandre Demers
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