[PATCH 00/73] DC Linux Patches Nov 9, 2017

[PATCH 00/73] DC Linux Patches Nov 9, 2017

[Harry Wentland]

 * Whole bunch of Raven (DCN) work
 * Bunch of cleanups


Andrew Jiang (7):
  drm/amd/display: Don't use dc_link in link_encoder
  drm/amd/display: Report pitch_alignment for DCN
  drm/amd/display: Loosen plane_info and scaling_info checks
  drm/amd/display: Remove legacy unused workaround
  drm/amd/display: Add update flags in to determine surface update type
  drm/amd/display: Rename pitch_alignment to linear_pitch_alignment
  drm/amd/display: Add check update surfaces for stream wrapper

Arun Pandey (1):
  drm/amd/display: Added Opp and Diags Interface for P to I

Bhawanpreet Lakha (1):
  drm/amd/display: add flip_immediate to commit update for stream

Charlene Liu (2):
  drm/amd/display: fix AZ clock not enabled before program AZ endpoint
  drm/amd/display: Do post_update_surfaces on new state

Dmytro Laktyushkin (6):
  drm/amd/display: cache pwl params and scl_data to avoid extra
    programming
  drm/amd/display: fix regamma programming
  drm/amd/display: fix uninitialized variable warning
  drm/amd/display: remove unnecessary waits in dcn10
  drm/amd/display: add warning on long reg_wait
  drm/amd/display: remove dcn10 wait on tg unlock

Eric Bernstein (3):
  drm/amd/display: Call ipp_program_bias_and_scale only if available
  drm/amd/display: Add OPP DPG blank function
  drm/amd/display: Remove unused OPP functions from interface

Eric Yang (4):
  drm/amd/display: get remote dpcd caps for timing validation
  drm/amd/display: fix MST link training fail division by 0
  drm/amd/display: always call set output tf
  drm/amd/display: combine output signal and signal

Harry Wentland (12):
  drm/amd/display: Both timing_sync and multisync need stream_count > 1
  drm/amd/display: Bunch of indentation cleanups in color stuff
  drm/amd/display: Fix some more color indentations
  drm/amd/display: Remove extra arr_points element
  drm/amd/display: Bunch more color indentation cleanups
  drm/amd/display: Remove unused register read in program_pwl
  drm/amd/display: A few more color indentation changes
  drm/amd/display: Fix formatting for null pointer dereference fix
  drm/amd/display: Move dc_stream interface to separate header
  drm/amd/display: Move dc_link interface to separate header
  drm/amd/display: Remove unnecessary dc_stream vtable
  drm/amd/display: Fix Linux after optimize frontend programming

Hersen Wu (1):
  drm/amd/display: send display_count msg so SMU can enter S0i2

Jerry (Fangzhi) Zuo (2):
  drm/amd/display: Miss register MST encoder cbs
  drm/amd/display: Check aux channel before MST resume

Ken Chalmers (2):
  drm/amd/display: use num_timing_generator instead of pipe_count
  drm/amd/display: fix dcn10_hubbub_wm_read_state

Leo (Sunpeng) Li (6):
  drm/amd/display: Fix warnings on S3 resume
  drm/amd/display: Remove dangling planes on dc commit state
  drm/amd/display: Change frontend/backend programming sequence
  drm/amd/display: Early return on stream programming failure
  drm/amd/display: Fix unused variable warning
  drm/amd/display: Fix use before initialize warning

Mikita Lipski (1):
  drm/amd/display: Multi display synchronization logic

Roman Li (2):
  drm/amd/display: use configurable FBC option in dm
  drm/amd/display: Fix unbalanced locking in surface apply

SivapiriyanKumarasamy (1):
  drm/amd/display: Add transfer function to dc_surface_update

Tony Cheng (8):
  drm/amd/display: dal 3.1.11
  drm/amd/display: dal 3.1.12
  drm/amd/display: dal 3.1.13
  drm/amd/display: dal 3.1.14
  drm/amd/display: dal 3.1.15
  drm/amd/display: dal 3.1.16
  drm/amd/display: fix plane update prior to stream enablement
  drm/amd/display: remove stream_func vtable

Yongqiang Sun (8):
  drm/amd/display: Enalbe blank data double buffer after mpc
    disconnected.
  drm/amd/display: Add tg_init interface.
  drm/amd/display: Refactor disable front end pipes.
  drm/amd/display: Modified front end initiail in init_hw
  drm/amd/display: Fixed not set scaler bug.
  drm/amd/display: Apply work around for stutter.
  drm/amd/display: Optimize programming front end
  drm/amd/display: Optimize front end programming.

Yue Hin Lau (6):
  drm/amd/display: create new function prototype update_dchub for dcn
  drm/amd/display: function renaming for hubbub
  drm/amd/display: hubbub function flipping true and false
  drm/amd/display: Only update dchub if hubbub is available
  drm/amd/display: call set csc_default if enable adjustment is false
  drm/amd/display: renaming dpp function to follow naming convention

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 100 ++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |   4 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    |  12 +-
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   3 +
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 458 ++++++-----
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  10 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |  11 +-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |  17 +-
 drivers/gpu/drm/amd/display/dc/dc.h                | 528 ++----------
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h       |  28 +-
 drivers/gpu/drm/amd/display/dc/dc_helper.c         |   7 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h       |  16 +
 drivers/gpu/drm/amd/display/dc/dc_link.h           | 207 +++++
 drivers/gpu/drm/amd/display/dc/dc_stream.h         | 289 +++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     |  31 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     |   9 -
 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c       |  33 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  |  34 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |   5 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 278 +++----
 .../amd/display/dc/dce100/dce100_hw_sequencer.c    |   2 +
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 305 ++++---
 .../amd/display/dc/dce110/dce110_hw_sequencer.h    |   4 +-
 .../amd/display/dc/dce110/dce110_opp_regamma_v.c   |   2 +-
 .../display/dc/dce110/dce110_timing_generator.c    | 265 ++++--
 .../display/dc/dce110/dce110_timing_generator.h    |   6 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |  75 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  30 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    |  31 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |   5 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c    |  42 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h    |   9 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 887 +++++++++++----------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  11 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   |  45 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   |  77 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   4 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 122 ++-
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h        |  38 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h       |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h  |   2 +-
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h        |  12 +
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  11 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  21 +-
 .../amd/display/dc/virtual/virtual_link_encoder.c  |   3 +-
 .../drm/amd/display/modules/freesync/freesync.c    |  84 +-
 51 files changed, 2298 insertions(+), 1887 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dc_link.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dc_stream.h

-- 
2.14.1

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[PATCH 01/73] drm/amd/display: Multi display synchronization logic

[Harry Wentland]

From: Mikita Lipski <mikita.lipski@amd.com>

This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one

There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underflow and other potential
corruptions.

Multi display synchronization is using the
same functions as timing_sync in order to minimize
redunduncy and decision to disable synchronization is
based on trigger parametre set in DM

Feature is developed for DCN1 and DCE11

Change-Id: I605c576250f13d68f010de03390090233be3385e
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  54 ++++-
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  26 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |   3 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h       |  16 ++
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  46 +++-
 .../display/dc/dce110/dce110_timing_generator.c    | 265 +++++++++++++++++----
 .../display/dc/dce110/dce110_timing_generator.h    |   6 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  29 ++-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |  66 ++++-
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   5 +
 11 files changed, 456 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ccfbf14c0f09..de901fdd53cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2275,6 +2275,56 @@ static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
 	return 0;
 }
 
+static void set_multisync_trigger_params(
+		struct dc_stream_state *stream)
+{
+	if (stream->triggered_crtc_reset.enabled) {
+		stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
+		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
+	}
+}
+
+static void set_master_stream(struct dc_stream_state *stream_set[],
+			      int stream_count)
+{
+	int j, highest_rfr = 0, master_stream = 0;
+
+	for (j = 0;  j < stream_count; j++) {
+		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
+			int refresh_rate = 0;
+
+			refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
+				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
+			if (refresh_rate > highest_rfr) {
+				highest_rfr = refresh_rate;
+				master_stream = j;
+			}
+		}
+	}
+	for (j = 0;  j < stream_count; j++) {
+		if (stream_set[j] && j != master_stream)
+			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
+	}
+}
+
+static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
+{
+	int i = 0;
+
+	if (context->stream_count < 2)
+		return;
+	for (i = 0; i < context->stream_count ; i++) {
+		if (!context->streams[i])
+			continue;
+		/* TODO: add a function to read AMD VSDB bits and will set
+		 * crtc_sync_master.multi_sync_enabled flag
+		 * For now its set to false
+		 */
+		set_multisync_trigger_params(context->streams[i]);
+	}
+	set_master_stream(context->streams, context->stream_count);
+}
+
 static struct dc_stream_state *
 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 		       const struct drm_display_mode *drm_mode,
@@ -4143,8 +4193,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 		}
 	}
 
-	if (dm_state->context)
+	if (dm_state->context) {
+		dm_enable_per_frame_crtc_master_sync(dm_state->context);
 		WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
+	}
 
 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 725a29f70b88..270e84a210c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -674,6 +674,28 @@ void dc_destroy(struct dc **dc)
 	*dc = NULL;
 }
 
+static void enable_timing_multisync(
+		struct dc *dc,
+		struct dc_state *ctx)
+{
+	int i = 0, multisync_count = 0;
+	int pipe_count = dc->res_pool->pipe_count;
+	struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
+
+	for (i = 0; i < pipe_count; i++) {
+		if (!ctx->res_ctx.pipe_ctx[i].stream ||
+				!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
+			continue;
+		multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
+		multisync_count++;
+	}
+
+	if (multisync_count > 1) {
+		dc->hwss.enable_per_frame_crtc_position_reset(
+			dc, multisync_count, multisync_pipes);
+	}
+}
+
 static void program_timing_sync(
 		struct dc *dc,
 		struct dc_state *ctx)
@@ -852,7 +874,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	}
 	result = dc->hwss.apply_ctx_to_hw(dc, context);
 
-	program_timing_sync(dc, context);
+	if (context->stream_count > 1)
+		enable_timing_multisync(dc, context);
+		program_timing_sync(dc, context);
 
 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4019e7417c88..a51a9c748c1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -607,6 +607,9 @@ struct dc_stream_state {
 
 	/* from stream struct */
 	struct kref refcount;
+
+	struct crtc_trigger_info triggered_crtc_reset;
+
 };
 
 struct dc_stream_update {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index ea58d106fb55..587c0bb3d4ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -673,6 +673,22 @@ enum dc_timing_3d_format {
 	TIMING_3D_FORMAT_MAX,
 };
 
+enum trigger_delay {
+	TRIGGER_DELAY_NEXT_PIXEL = 0,
+	TRIGGER_DELAY_NEXT_LINE,
+};
+
+enum crtc_event {
+	CRTC_EVENT_VSYNC_RISING = 0,
+	CRTC_EVENT_VSYNC_FALLING
+};
+
+struct crtc_trigger_info {
+	bool enabled;
+	struct dc_stream_state *event_source;
+	enum crtc_event event;
+	enum trigger_delay delay;
+};
 
 struct dc_crtc_timing {
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6e0ea5459b74..b4504f1f49c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2455,20 +2455,16 @@ static void dce110_enable_timing_synchronization(
 
 	for (i = 1 /* skip the master */; i < group_size; i++)
 		grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
-					grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
-
-
+				grouped_pipes[i]->stream_res.tg,
+				gsl_params.gsl_group);
 
 	for (i = 1 /* skip the master */; i < group_size; i++) {
 		DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
 		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
-		/* Regardless of success of the wait above, remove the reset or
-		 * the driver will start timing out on Display requests. */
-		DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
-		grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
+		grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
+				grouped_pipes[i]->stream_res.tg);
 	}
 
-
 	/* GSL Vblank synchronization is a one time sync mechanism, assumption
 	 * is that the sync'ed displays will not drift out of sync over time*/
 	DC_SYNC_INFO("GSL: Restoring register states.\n");
@@ -2478,6 +2474,39 @@ static void dce110_enable_timing_synchronization(
 	DC_SYNC_INFO("GSL: Set-up complete.\n");
 }
 
+static void dce110_enable_per_frame_crtc_position_reset(
+		struct dc *dc,
+		int group_size,
+		struct pipe_ctx *grouped_pipes[])
+{
+	struct dc_context *dc_ctx = dc->ctx;
+	struct dcp_gsl_params gsl_params = { 0 };
+	int i;
+
+	gsl_params.gsl_group = 0;
+	gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
+
+	for (i = 0; i < group_size; i++)
+		grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
+					grouped_pipes[i]->stream_res.tg, &gsl_params);
+
+	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
+
+	for (i = 1; i < group_size; i++)
+		grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
+				grouped_pipes[i]->stream_res.tg,
+				gsl_params.gsl_master,
+				&grouped_pipes[i]->stream->triggered_crtc_reset);
+
+	DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
+	for (i = 1; i < group_size; i++)
+		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
+
+	for (i = 0; i < group_size; i++)
+		grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
+
+}
+
 static void init_hw(struct dc *dc)
 {
 	int i;
@@ -2974,6 +3003,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.power_down = dce110_power_down,
 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
 	.enable_timing_synchronization = dce110_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
 	.update_info_frame = dce110_update_info_frame,
 	.enable_stream = dce110_enable_stream,
 	.disable_stream = dce110_disable_stream,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 67ac737eaa7e..08e49dd3d9d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1224,26 +1224,46 @@ void dce110_timing_generator_setup_global_swap_lock(
 
 	/* This pipe will belong to GSL Group zero. */
 	set_reg_field_value(value,
-			1,
-			DCP_GSL_CONTROL,
-			DCP_GSL0_EN);
+			    1,
+			    DCP_GSL_CONTROL,
+			    DCP_GSL0_EN);
 
 	set_reg_field_value(value,
-			gsl_params->gsl_master == tg->inst,
-			DCP_GSL_CONTROL,
-			DCP_GSL_MASTER_EN);
+			    gsl_params->gsl_master == tg->inst,
+			    DCP_GSL_CONTROL,
+			    DCP_GSL_MASTER_EN);
 
 	set_reg_field_value(value,
-			HFLIP_READY_DELAY,
-			DCP_GSL_CONTROL,
-			DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
+			    HFLIP_READY_DELAY,
+			    DCP_GSL_CONTROL,
+			    DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
 
 	/* Keep signal low (pending high) during 6 lines.
 	 * Also defines minimum interval before re-checking signal. */
 	set_reg_field_value(value,
-			HFLIP_CHECK_DELAY,
-			DCP_GSL_CONTROL,
-			DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
+			    HFLIP_CHECK_DELAY,
+			    DCP_GSL_CONTROL,
+			    DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
+
+	dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value);
+	value = 0;
+
+	set_reg_field_value(value,
+			    gsl_params->gsl_master,
+			    DCIO_GSL0_CNTL,
+			    DCIO_GSL0_VSYNC_SEL);
+
+	set_reg_field_value(value,
+			    0,
+			    DCIO_GSL0_CNTL,
+			    DCIO_GSL0_TIMING_SYNC_SEL);
+
+	set_reg_field_value(value,
+			    0,
+			    DCIO_GSL0_CNTL,
+			    DCIO_GSL0_GLOBAL_UNLOCK_SEL);
+
+	dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value);
 
 
 	{
@@ -1253,38 +1273,38 @@ void dce110_timing_generator_setup_global_swap_lock(
 				CRTC_REG(mmCRTC_V_TOTAL));
 
 		set_reg_field_value(value,
-				0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */
-				DCP_GSL_CONTROL,
-				DCP_GSL_SYNC_SOURCE);
+				    0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */
+				    DCP_GSL_CONTROL,
+				    DCP_GSL_SYNC_SOURCE);
 
 		/* Checkpoint relative to end of frame */
 		check_point = get_reg_field_value(value_crtc_vtotal,
-				CRTC_V_TOTAL,
-				CRTC_V_TOTAL);
+						  CRTC_V_TOTAL,
+						  CRTC_V_TOTAL);
 
 		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0);
 	}
 
 	set_reg_field_value(value,
-			1,
-			DCP_GSL_CONTROL,
-			DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
+			    1,
+			    DCP_GSL_CONTROL,
+			    DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
 
 	dm_write_reg(tg->ctx, address, value);
 
 	/********************************************************************/
 	address = CRTC_REG(mmCRTC_GSL_CONTROL);
 
-	value = 0;
+	value = dm_read_reg(tg->ctx, address);
 	set_reg_field_value(value,
-			check_point - FLIP_READY_BACK_LOOKUP,
-			CRTC_GSL_CONTROL,
-			CRTC_GSL_CHECK_LINE_NUM);
+			    check_point - FLIP_READY_BACK_LOOKUP,
+			    CRTC_GSL_CONTROL,
+			    CRTC_GSL_CHECK_LINE_NUM);
 
 	set_reg_field_value(value,
-			VFLIP_READY_DELAY,
-			CRTC_GSL_CONTROL,
-			CRTC_GSL_FORCE_DELAY);
+			    VFLIP_READY_DELAY,
+			    CRTC_GSL_CONTROL,
+			    CRTC_GSL_FORCE_DELAY);
 
 	dm_write_reg(tg->ctx, address, value);
 }
@@ -1555,6 +1575,138 @@ void dce110_timing_generator_enable_reset_trigger(
 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
 }
 
+void dce110_timing_generator_enable_crtc_reset(
+		struct timing_generator *tg,
+		int source_tg_inst,
+		struct crtc_trigger_info *crtc_tp)
+{
+	uint32_t value = 0;
+	uint32_t rising_edge = 0;
+	uint32_t falling_edge = 0;
+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
+	/* Setup trigger edge */
+	switch (crtc_tp->event) {
+	case CRTC_EVENT_VSYNC_RISING:
+			rising_edge = 1;
+			break;
+
+	case CRTC_EVENT_VSYNC_FALLING:
+		falling_edge = 1;
+		break;
+	}
+
+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
+
+	set_reg_field_value(value,
+			    source_tg_inst,
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_SOURCE_SELECT);
+
+	set_reg_field_value(value,
+			    TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_POLARITY_SELECT);
+
+	set_reg_field_value(value,
+			    rising_edge,
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_RISING_EDGE_DETECT_CNTL);
+
+	set_reg_field_value(value,
+			    falling_edge,
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL);
+
+	set_reg_field_value(value,
+			    1, /* clear trigger status */
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_CLEAR);
+
+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
+
+	/**************************************************************/
+
+	switch (crtc_tp->delay) {
+	case TRIGGER_DELAY_NEXT_LINE:
+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
+
+		set_reg_field_value(value,
+				    0, /* force H count to H_TOTAL and V count to V_TOTAL */
+				    CRTC_FORCE_COUNT_NOW_CNTL,
+				    CRTC_FORCE_COUNT_NOW_MODE);
+
+		set_reg_field_value(value,
+				    0, /* TriggerB - we never use TriggerA */
+				    CRTC_FORCE_COUNT_NOW_CNTL,
+				    CRTC_FORCE_COUNT_NOW_TRIG_SEL);
+
+		set_reg_field_value(value,
+				    1, /* clear trigger status */
+				    CRTC_FORCE_COUNT_NOW_CNTL,
+				    CRTC_FORCE_COUNT_NOW_CLEAR);
+
+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
+
+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+
+		set_reg_field_value(value,
+				    1,
+				    CRTC_VERT_SYNC_CONTROL,
+				    CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
+
+		set_reg_field_value(value,
+				    2,
+				    CRTC_VERT_SYNC_CONTROL,
+				    CRTC_AUTO_FORCE_VSYNC_MODE);
+
+		break;
+
+	case TRIGGER_DELAY_NEXT_PIXEL:
+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+
+		set_reg_field_value(value,
+				    1,
+				    CRTC_VERT_SYNC_CONTROL,
+				    CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
+
+		set_reg_field_value(value,
+				    0,
+				    CRTC_VERT_SYNC_CONTROL,
+				    CRTC_AUTO_FORCE_VSYNC_MODE);
+
+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value);
+
+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
+
+		set_reg_field_value(value,
+				    2, /* force H count to H_TOTAL and V count to V_TOTAL */
+				    CRTC_FORCE_COUNT_NOW_CNTL,
+				    CRTC_FORCE_COUNT_NOW_MODE);
+
+		set_reg_field_value(value,
+				    1, /* TriggerB - we never use TriggerA */
+				    CRTC_FORCE_COUNT_NOW_CNTL,
+				    CRTC_FORCE_COUNT_NOW_TRIG_SEL);
+
+		set_reg_field_value(value,
+				    1, /* clear trigger status */
+				    CRTC_FORCE_COUNT_NOW_CNTL,
+				    CRTC_FORCE_COUNT_NOW_CLEAR);
+
+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
+		break;
+	}
+
+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
+
+	set_reg_field_value(value,
+			    2,
+			    CRTC_MASTER_UPDATE_MODE,
+			    MASTER_UPDATE_MODE);
+
+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
+}
 void dce110_timing_generator_disable_reset_trigger(
 	struct timing_generator *tg)
 {
@@ -1564,34 +1716,48 @@ void dce110_timing_generator_disable_reset_trigger(
 	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
 
 	set_reg_field_value(value,
-			0, /* force counter now mode is disabled */
-			CRTC_FORCE_COUNT_NOW_CNTL,
-			CRTC_FORCE_COUNT_NOW_MODE);
+			    0, /* force counter now mode is disabled */
+			    CRTC_FORCE_COUNT_NOW_CNTL,
+			    CRTC_FORCE_COUNT_NOW_MODE);
 
 	set_reg_field_value(value,
-			1, /* clear trigger status */
-			CRTC_FORCE_COUNT_NOW_CNTL,
-			CRTC_FORCE_COUNT_NOW_CLEAR);
+			    1, /* clear trigger status */
+			    CRTC_FORCE_COUNT_NOW_CNTL,
+			    CRTC_FORCE_COUNT_NOW_CLEAR);
 
 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
 
+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+
+	set_reg_field_value(value,
+			    1,
+			    CRTC_VERT_SYNC_CONTROL,
+			    CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
+
+	set_reg_field_value(value,
+			    0,
+			    CRTC_VERT_SYNC_CONTROL,
+			    CRTC_AUTO_FORCE_VSYNC_MODE);
+
+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value);
+
 	/********************************************************************/
 	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
 
 	set_reg_field_value(value,
-			TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
-			CRTC_TRIGB_CNTL,
-			CRTC_TRIGB_SOURCE_SELECT);
+			    TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_SOURCE_SELECT);
 
 	set_reg_field_value(value,
-			TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-			CRTC_TRIGB_CNTL,
-			CRTC_TRIGB_POLARITY_SELECT);
+			    TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_POLARITY_SELECT);
 
 	set_reg_field_value(value,
-			1, /* clear trigger status */
-			CRTC_TRIGB_CNTL,
-			CRTC_TRIGB_CLEAR);
+			    1, /* clear trigger status */
+			    CRTC_TRIGB_CNTL,
+			    CRTC_TRIGB_CLEAR);
 
 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
 }
@@ -1611,10 +1777,16 @@ bool dce110_timing_generator_did_triggered_reset_occur(
 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t value = dm_read_reg(tg->ctx,
 			CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-
-	return get_reg_field_value(value,
-			CRTC_FORCE_COUNT_NOW_CNTL,
-			CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
+	uint32_t value1 = dm_read_reg(tg->ctx,
+			CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
+	bool force = get_reg_field_value(value,
+					 CRTC_FORCE_COUNT_NOW_CNTL,
+					 CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
+	bool vert_sync = get_reg_field_value(value1,
+					     CRTC_VERT_SYNC_CONTROL,
+					     CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED) != 0;
+
+	return (force || vert_sync);
 }
 
 /**
@@ -1928,6 +2100,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = {
 		.setup_global_swap_lock =
 				dce110_timing_generator_setup_global_swap_lock,
 		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
+		.enable_crtc_reset = dce110_timing_generator_enable_crtc_reset,
 		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
 		.tear_down_global_swap_lock =
 				dce110_timing_generator_tear_down_global_swap_lock,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index 82737dea6984..232747c7c60b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -174,6 +174,12 @@ void dce110_timing_generator_setup_global_swap_lock(
 void dce110_timing_generator_tear_down_global_swap_lock(
 	struct timing_generator *tg);
 
+/* Reset crtc position on master VSync */
+void dce110_timing_generator_enable_crtc_reset(
+	struct timing_generator *tg,
+	int source,
+	struct crtc_trigger_info *crtc_tp);
+
 /* Reset slave controllers on master VSync */
 void dce110_timing_generator_enable_reset_trigger(
 	struct timing_generator *tg,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d5759210cc7b..3a2457f8f2d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1304,14 +1304,15 @@ static void dcn10_enable_timing_synchronization(
 
 	for (i = 1; i < group_size; i++)
 		grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
-				grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst);
-
+				grouped_pipes[i]->stream_res.tg,
+				grouped_pipes[0]->stream_res.tg->inst);
 
 	DC_SYNC_INFO("Waiting for trigger\n");
 
 	/* Need to get only check 1 pipe for having reset as all the others are
 	 * synchronized. Look at last pipe programmed to reset.
 	 */
+
 	wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
 	for (i = 1; i < group_size; i++)
 		grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
@@ -1320,6 +1321,29 @@ static void dcn10_enable_timing_synchronization(
 	DC_SYNC_INFO("Sync complete\n");
 }
 
+static void dcn10_enable_per_frame_crtc_position_reset(
+	struct dc *dc,
+	int group_size,
+	struct pipe_ctx *grouped_pipes[])
+{
+	struct dc_context *dc_ctx = dc->ctx;
+	int i;
+
+	DC_SYNC_INFO("Setting up\n");
+	for (i = 0; i < group_size; i++)
+		grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
+				grouped_pipes[i]->stream_res.tg,
+				grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
+				&grouped_pipes[i]->stream->triggered_crtc_reset);
+
+	DC_SYNC_INFO("Waiting for trigger\n");
+
+	for (i = 1; i < group_size; i++)
+		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
+
+	DC_SYNC_INFO("Multi-display sync is complete\n");
+}
+
 static void print_rq_dlg_ttu(
 		struct dc *core_dc,
 		struct pipe_ctx *pipe_ctx)
@@ -2485,6 +2509,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.power_down = dce110_power_down,
 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
 	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
 	.update_info_frame = dce110_update_info_frame,
 	.enable_stream = dce110_enable_stream,
 	.disable_stream = dce110_disable_stream,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index fced178c8c79..c178cc0bd426 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -610,12 +610,28 @@ static bool tgn10_did_triggered_reset_occur(
 	struct timing_generator *tg)
 {
 	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-	uint32_t occurred;
+	uint32_t occurred_force, occurred_vsync;
 
 	REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
-		OTG_FORCE_COUNT_NOW_OCCURRED, &occurred);
+		OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
 
-	return occurred != 0;
+	REG_GET(OTG_VERT_SYNC_CONTROL,
+		OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
+
+	return occurred_vsync != 0 || occurred_force != 0;
+}
+
+static void tgn10_disable_reset_trigger(struct timing_generator *tg)
+{
+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+	REG_WRITE(OTG_TRIGA_CNTL, 0);
+
+	REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+		OTG_FORCE_COUNT_NOW_CLEAR, 1);
+
+	REG_SET(OTG_VERT_SYNC_CONTROL, 0,
+		OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
 }
 
 static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst)
@@ -652,14 +668,49 @@ static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_t
 			OTG_FORCE_COUNT_NOW_MODE, 2);
 }
 
-static void tgn10_disable_reset_trigger(struct timing_generator *tg)
+void tgn10_enable_crtc_reset(
+		struct timing_generator *tg,
+		int source_tg_inst,
+		struct crtc_trigger_info *crtc_tp)
 {
 	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+	uint32_t falling_edge = 0;
+	uint32_t rising_edge = 0;
 
-	REG_WRITE(OTG_TRIGA_CNTL, 0);
+	switch (crtc_tp->event) {
 
-	REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-			OTG_FORCE_COUNT_NOW_CLEAR, 1);
+	case CRTC_EVENT_VSYNC_RISING:
+		rising_edge = 1;
+		break;
+
+	case CRTC_EVENT_VSYNC_FALLING:
+		falling_edge = 1;
+		break;
+	}
+
+	REG_SET_4(OTG_TRIGA_CNTL, 0,
+		 /* vsync signal from selected OTG pipe based
+		  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+		  */
+		  OTG_TRIGA_SOURCE_SELECT, 20,
+		  OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+		  /* always detect falling edge */
+		  OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
+		  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
+
+	switch (crtc_tp->delay) {
+	case TRIGGER_DELAY_NEXT_LINE:
+		REG_SET(OTG_VERT_SYNC_CONTROL, 0,
+				OTG_AUTO_FORCE_VSYNC_MODE, 1);
+		break;
+	case TRIGGER_DELAY_NEXT_PIXEL:
+		REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+			/* force H count to H_TOTAL and V count to V_TOTAL in
+			 * progressive mode and V_TOTAL-1 in interlaced mode
+			 */
+			OTG_FORCE_COUNT_NOW_MODE, 2);
+		break;
+	}
 }
 
 static void tgn10_wait_for_state(struct timing_generator *tg,
@@ -1174,6 +1225,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.set_blank_color = tgn10_program_blank_color,
 		.did_triggered_reset_occur = tgn10_did_triggered_reset_occur,
 		.enable_reset_trigger = tgn10_enable_reset_trigger,
+		.enable_crtc_reset = tgn10_enable_crtc_reset,
 		.disable_reset_trigger = tgn10_disable_reset_trigger,
 		.lock = tgn10_lock,
 		.unlock = tgn10_unlock,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index c6ab38c5b2be..75f7a01b9175 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -158,7 +158,11 @@ struct timing_generator_funcs {
 							const struct dcp_gsl_params *gsl_params);
 	void (*unlock)(struct timing_generator *tg);
 	void (*lock)(struct timing_generator *tg);
-	void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst);
+	void (*enable_reset_trigger)(struct timing_generator *tg,
+				     int source_tg_inst);
+	void (*enable_crtc_reset)(struct timing_generator *tg,
+				  int source_tg_inst,
+				  struct crtc_trigger_info *crtc_tp);
 	void (*disable_reset_trigger)(struct timing_generator *tg);
 	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
 	void (*enable_advanced_request)(struct timing_generator *tg,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 8734689a9245..cebbba345889 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -114,6 +114,11 @@ struct hw_sequencer_funcs {
 			int group_size,
 			struct pipe_ctx *grouped_pipes[]);
 
+	void (*enable_per_frame_crtc_position_reset)(
+			struct dc *dc,
+			int group_size,
+			struct pipe_ctx *grouped_pipes[]);
+
 	void (*enable_display_pipe_clock_gating)(
 					struct dc_context *ctx,
 					bool clock_gating);
-- 
2.14.1

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amd-gfx@lists.freedesktop.org
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[PATCH 02/73] drm/amd/display: create new function prototype update_dchub for dcn

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

dcn version of update_dchub now uses hubbub instead of hwseq

Change-Id: I6335897c721870cf023346dc52d65071a2f1cf8a
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +++++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c     | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 3a2457f8f2d1..ced6c41876a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2493,7 +2493,10 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
 	}
 }
 
-
+void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+{
+	hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+}
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
 	.program_gamut_remap = program_gamut_remap,
@@ -2503,6 +2506,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
 	.set_plane_config = set_plane_config,
 	.update_plane_addr = dcn10_update_plane_addr,
+	.update_dchub = dcn10_update_dchub,
 	.update_pending_status = dcn10_update_pending_status,
 	.set_input_transfer_func = dcn10_set_input_transfer_func,
 	.set_output_transfer_func = dcn10_set_output_transfer_func,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 701ed09d5bba..2e6122c4670a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1459,7 +1459,7 @@ static bool construct(
 	pool->base.hubbub = dcn10_hubbub_create(ctx);
 	if (pool->base.hubbub == NULL) {
 		BREAK_TO_DEBUGGER();
-		dm_error("DC: failed to create mpc!\n");
+		dm_error("DC: failed to create hubbub!\n");
 		goto fail;
 	}
 
-- 
2.14.1

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[PATCH 03/73] drm/amd/display: fix AZ clock not enabled before program AZ endpoint

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: Ie8683cbe4791557054eba856aee6e06c948fc1f0
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 31 ++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index d882adf746a5..81c40f8864db 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -348,29 +348,44 @@ static void set_audio_latency(
 
 void dce_aud_az_enable(struct audio *audio)
 {
+	struct dce_audio *aud = DCE_AUD(audio);
 	uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 
-	if (get_reg_field_value(value,
+	set_reg_field_value(value, 1,
 			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-			AUDIO_ENABLED) != 1)
+			CLOCK_GATING_DISABLE);
 		set_reg_field_value(value, 1,
 			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 			AUDIO_ENABLED);
 
 	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+
+	dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+			"\n\t========= AUDIO:dce_aud_az_enable: index: %u  data: 0x%x\n",
+			audio->inst, value);
 }
 
 void dce_aud_az_disable(struct audio *audio)
 {
 	uint32_t value;
+	struct dce_audio *aud = DCE_AUD(audio);
 
 	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 
 	set_reg_field_value(value, 0,
 		AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 		AUDIO_ENABLED);
+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 
+	set_reg_field_value(value, 0,
+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+			CLOCK_GATING_DISABLE);
 	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+	dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+			"\n\t========= AUDIO:dce_aud_az_disable: index: %u  data: 0x%x\n",
+			audio->inst, value);
 }
 
 void dce_aud_az_configure(
@@ -390,6 +405,11 @@ void dce_aud_az_configure(
 	bool is_ac3_supported = false;
 	union audio_sample_rates sample_rate;
 	uint32_t strlen = 0;
+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+	set_reg_field_value(value, 1,
+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+			CLOCK_GATING_DISABLE);
+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 
 	/* Speaker Allocation */
 	/*
@@ -852,6 +872,7 @@ static bool dce_aud_endpoint_valid(struct audio *audio)
 void dce_aud_hw_init(
 		struct audio *audio)
 {
+	uint32_t value;
 	struct dce_audio *aud = DCE_AUD(audio);
 
 	/* we only need to program the following registers once, so we only do
@@ -863,6 +884,12 @@ void dce_aud_hw_init(
 	 * Suport R6 - 44.1khz
 	 * Suport R7 - 48khz
 	 */
+	/*disable clock gating before write to endpoint register*/
+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+	set_reg_field_value(value, 1,
+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+			CLOCK_GATING_DISABLE);
+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 	REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
 			AUDIO_RATE_CAPABILITIES, 0x70);
 
-- 
2.14.1

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[PATCH 04/73] drm/amd/display: function renaming for hubbub

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

following the naming convention with correct prefix

Change-Id: Ie4f2485f76ec9dc54a9aabea6f14a1119167d44e
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c    | 16 +++----
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h    |  9 ++--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 55 +++++++++++++---------
 3 files changed, 43 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index f60e90cff1bb..b1c9ba241ba4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -75,7 +75,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
-void verify_allow_pstate_change_high(
+bool hubbub1_verify_allow_pstate_change_high(
 	struct hubbub *hubbub)
 {
 	/* pstate latency is ~20us so if we wait over 40us and pstate allow
@@ -89,7 +89,6 @@ void verify_allow_pstate_change_high(
 	static unsigned int pstate_wait_expected_timeout_us = 40;
 	static unsigned int max_sampled_pstate_wait_us; /* data collection */
 	static bool forced_pstate_allow; /* help with revert wa */
-	static bool should_log_hw_state; /* prevent hw state log by default */
 
 	unsigned int debug_index = 0x7;
 	unsigned int debug_data;
@@ -140,7 +139,7 @@ void verify_allow_pstate_change_high(
 						"pstate took longer than expected ~%dus\n",
 						i);
 
-			return;
+			return false;
 		}
 		if (max_sampled_pstate_wait_us < i)
 			max_sampled_pstate_wait_us = i;
@@ -156,14 +155,11 @@ void verify_allow_pstate_change_high(
 		     DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
 	forced_pstate_allow = true;
 
-	if (should_log_hw_state) {
-		dcn10_log_hw_state(hubbub->ctx->dc);
-	}
-
 	dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
 			"pstate TEST_DEBUG_DATA: 0x%X\n",
 			debug_data);
-	BREAK_TO_DEBUGGER();
+
+	return true;
 }
 
 static uint32_t convert_and_clamp(
@@ -182,7 +178,7 @@ static uint32_t convert_and_clamp(
 }
 
 
-void program_watermarks(
+void hubbub1_program_watermarks(
 		struct hubbub *hubbub,
 		struct dcn_watermark_set *watermarks,
 		unsigned int refclk_mhz)
@@ -472,7 +468,7 @@ void hubbub1_update_dchub(
 	dh_data->dchub_info_valid = false;
 }
 
-void toggle_watermark_change_req(struct hubbub *hubbub)
+void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
 {
 	uint32_t watermark_change_req;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index e9abb881bd3f..d5c97844312f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -191,18 +191,15 @@ void hubbub1_update_dchub(
 	struct hubbub *hubbub,
 	struct dchub_init_data *dh_data);
 
-void dcn10_log_hw_state(
-		struct dc *dc);
-
-void verify_allow_pstate_change_high(
+bool hubbub1_verify_allow_pstate_change_high(
 	struct hubbub *hubbub);
 
-void program_watermarks(
+void hubbub1_program_watermarks(
 		struct hubbub *hubbub,
 		struct dcn_watermark_set *watermarks,
 		unsigned int refclk_mhz);
 
-void toggle_watermark_change_req(
+void hubbub1_toggle_watermark_change_req(
 		struct hubbub *hubbub);
 
 void hubbub1_wm_read_state(struct hubbub *hubbub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ced6c41876a7..e2dc834e89d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -544,6 +544,19 @@ static void reset_back_end_for_pipe(
 					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 }
 
+void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+{
+	static bool should_log_hw_state; /* prevent hw state log by default */
+
+	if (hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
+		if (should_log_hw_state) {
+			dcn10_log_hw_state(dc);
+		}
+
+		BREAK_TO_DEBUGGER();
+	}
+}
+
 /* trigger HW to start disconnect plane from stream on the next vsync */
 static void plane_atomic_disconnect(struct dc *dc,
 		int fe_idx)
@@ -571,10 +584,10 @@ static void plane_atomic_disconnect(struct dc *dc,
 		return;
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	hubp->funcs->dcc_control(hubp, false, false);
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 
 	mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
 			dc->res_pool->opps[opp_id]->inst, fe_idx);
@@ -602,7 +615,7 @@ static void plane_atomic_disable(struct dc *dc,
 	hubp->funcs->set_blank(hubp, true);
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 
 	REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
 			HUBP_CLOCK_ENABLE, 0);
@@ -614,7 +627,7 @@ static void plane_atomic_disable(struct dc *dc,
 				OPP_PIPE_CLOCK_EN, 0);
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 }
 
 static void reset_front_end(
@@ -638,7 +651,7 @@ static void reset_front_end(
 	tg->funcs->unlock(tg);
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 
 	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
 		REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
@@ -670,7 +683,7 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
 			"Power gated front end %d\n", fe_idx);
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 }
 
 static void dcn10_init_hw(struct dc *dc)
@@ -1243,7 +1256,7 @@ static void dcn10_pipe_control_lock(
 		return;
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 
 	if (lock)
 		pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
@@ -1251,7 +1264,7 @@ static void dcn10_pipe_control_lock(
 		pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 }
 
 static bool wait_for_reset_trigger_to_occur(
@@ -1475,7 +1488,7 @@ static void dcn10_power_on_fe(
 	struct dce_hwseq *hws = dc->hwseq;
 
 	if (dc->debug.sanity_checks) {
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
 	power_on_plane(dc->hwseq,
@@ -1527,7 +1540,7 @@ static void dcn10_power_on_fe(
 	}
 
 	if (dc->debug.sanity_checks) {
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 }
 
@@ -1960,11 +1973,11 @@ static void program_all_pipe_in_tree(
 		 * this OTG. this is done only one time.
 		 */
 		/* watermark is for all pipes */
-		program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz);
+		hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz);
 
 		if (dc->debug.sanity_checks) {
 			/* pstate stuck check after watermark update */
-			verify_allow_pstate_change_high(dc->res_pool->hubbub);
+			dcn10_verify_allow_pstate_change_high(dc);
 		}
 
 		pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
@@ -1995,7 +2008,7 @@ static void program_all_pipe_in_tree(
 		 * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
 		 * both driver and fw accessing same register
 		 */
-		toggle_watermark_change_req(dc->res_pool->hubbub);
+		hubbub1_toggle_watermark_change_req(dc->res_pool->hubbub);
 
 		update_dchubp_dpp(dc, pipe_ctx, context);
 
@@ -2018,7 +2031,7 @@ static void program_all_pipe_in_tree(
 
 	if (dc->debug.sanity_checks) {
 		/* pstate stuck check after each pipe is programmed */
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
 	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
@@ -2085,7 +2098,7 @@ static void dcn10_apply_ctx_for_surface(
 	int i, be_idx;
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 
 	be_idx = -1;
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2168,7 +2181,7 @@ static void dcn10_apply_ctx_for_surface(
 				hubp->funcs->hubp_disconnect(hubp);
 
 			if (dc->debug.sanity_checks)
-				verify_allow_pstate_change_high(dc->res_pool->hubbub);
+				dcn10_verify_allow_pstate_change_high(dc);
 
 			old_pipe_ctx->top_pipe = NULL;
 			old_pipe_ctx->bottom_pipe = NULL;
@@ -2246,7 +2259,7 @@ static void dcn10_apply_ctx_for_surface(
 			);
 
 	if (dc->debug.sanity_checks)
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 }
 
 static void dcn10_set_bandwidth(
@@ -2260,7 +2273,7 @@ static void dcn10_set_bandwidth(
 	struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
 
 	if (dc->debug.sanity_checks) {
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
@@ -2316,7 +2329,7 @@ static void dcn10_set_bandwidth(
 	dcn10_pplib_apply_display_requirements(dc, context);
 
 	if (dc->debug.sanity_checks) {
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
 	/* need to fix this function.  not doing the right thing here */
@@ -2441,7 +2454,7 @@ static void dcn10_wait_for_mpcc_disconnect(
 	int i;
 
 	if (dc->debug.sanity_checks) {
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
 	if (!pipe_ctx->stream_res.opp)
@@ -2459,7 +2472,7 @@ static void dcn10_wait_for_mpcc_disconnect(
 	}
 
 	if (dc->debug.sanity_checks) {
-		verify_allow_pstate_change_high(dc->res_pool->hubbub);
+		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
 }
-- 
2.14.1

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[PATCH 05/73] drm/amd/display: Do post_update_surfaces on new state

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: I98a09a622bbcf92e52377eb5eb14970bc604adc2
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 270e84a210c8..f3fd062bcdd2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1427,10 +1427,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
 				stream_update,
 				update_type,
 				context);
-
-	if (update_type >= UPDATE_TYPE_FULL)
-		dc_post_update_surfaces_to_stream(dc);
-
+	/*update current_State*/
 	if (dc->current_state != context) {
 
 		struct dc_state *old = dc->current_state;
@@ -1439,6 +1436,9 @@ void dc_commit_updates_for_stream(struct dc *dc,
 		dc_release_state(old);
 
 	}
+	/*let's use current_state to update watermark etc*/
+	if (update_type >= UPDATE_TYPE_FULL)
+		dc_post_update_surfaces_to_stream(dc);
 
 	return;
 
-- 
2.14.1

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[PATCH 06/73] drm/amd/display: hubbub function flipping true and false

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

no logic change

Change-Id: I31bdbba1abeb64d54e385456b58839160b1e188b
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c       | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index b1c9ba241ba4..23c4573f7a34 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -139,7 +139,7 @@ bool hubbub1_verify_allow_pstate_change_high(
 						"pstate took longer than expected ~%dus\n",
 						i);
 
-			return false;
+			return true;
 		}
 		if (max_sampled_pstate_wait_us < i)
 			max_sampled_pstate_wait_us = i;
@@ -159,7 +159,7 @@ bool hubbub1_verify_allow_pstate_change_high(
 			"pstate TEST_DEBUG_DATA: 0x%X\n",
 			debug_data);
 
-	return true;
+	return false;
 }
 
 static uint32_t convert_and_clamp(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e2dc834e89d3..0bdf06969c83 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -548,7 +548,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 {
 	static bool should_log_hw_state; /* prevent hw state log by default */
 
-	if (hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
+	if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 		if (should_log_hw_state) {
 			dcn10_log_hw_state(dc);
 		}
-- 
2.14.1

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[PATCH 07/73] drm/amd/display: dal 3.1.11

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: Iec51322a9e35f8ad8729168df7e6c88d42799e8c
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a51a9c748c1a..79e2ddbc3399 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.10"
+#define DC_VER "3.1.11"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 08/73] drm/amd/display: use configurable FBC option in dm

[Harry Wentland]

From: Roman Li <Roman.Li@amd.com>

Replace ENABLE_FBC macro with config option CONFIG_DRM_AMD_DC_FBC
in dm. DC code has been already updated the same way.

Change-Id: I8c0e8deb6fe1387a7364822d12c2cc5beb888998
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Shirish Shankarappa <Shirish.S@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index de901fdd53cc..77fb1b54694b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -344,7 +344,7 @@ static void hotplug_notify_work_func(struct work_struct *work)
 	drm_kms_helper_hotplug_event(dev);
 }
 
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
 #include "dal_asic_id.h"
 /* Allocate memory for FBC compressed data  */
 /* TODO: Dynamic allocation */
@@ -422,7 +422,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	else
 		init_data.log_mask = DC_MIN_LOG_MASK;
 
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
 	if (adev->family == FAMILY_CZ)
 		amdgpu_dm_initialize_fbc(adev);
 	init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 6b81e124ea57..450379d684cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -72,7 +72,7 @@ struct irq_list_head {
 	struct work_struct work;
 };
 
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
 struct dm_comressor_info {
 	void *cpu_addr;
 	struct amdgpu_bo *bo_ptr;
@@ -142,7 +142,7 @@ struct amdgpu_display_manager {
 	 * Caches device atomic state for suspend/resume
 	 */
 	struct drm_atomic_state *cached_state;
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
 	struct dm_comressor_info compressor;
 #endif
 };
-- 
2.14.1

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[PATCH 09/73] drm/amd/display: Call ipp_program_bias_and_scale only if available

[Harry Wentland]

From: Eric Bernstein <eric.bernstein@amd.com>

Also move some register definitions to common DCN regs.

Change-Id: I6da468797abb0662e144aff073c62ab6a3ad430e
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h         | 16 ++++++++--------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    |  3 ++-
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 3a6ebd14eea2..880e366568a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -73,6 +73,9 @@
 	SRI(RECOUT_START, DSCL, id), \
 	SRI(RECOUT_SIZE, DSCL, id), \
 	SRI(OBUF_CONTROL, DSCL, id), \
+	SRI(CM_ICSC_CONTROL, CM, id), \
+	SRI(CM_ICSC_C11_C12, CM, id), \
+	SRI(CM_ICSC_C33_C34, CM, id), \
 	SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
 	SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
 	SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
@@ -124,9 +127,6 @@
 	SRI(CM_OCSC_CONTROL, CM, id), \
 	SRI(CM_OCSC_C11_C12, CM, id), \
 	SRI(CM_OCSC_C33_C34, CM, id), \
-	SRI(CM_ICSC_CONTROL, CM, id), \
-	SRI(CM_ICSC_C11_C12, CM, id), \
-	SRI(CM_ICSC_C33_C34, CM, id), \
 	SRI(CM_BNS_VALUES_R, CM, id), \
 	SRI(CM_BNS_VALUES_G, CM, id), \
 	SRI(CM_BNS_VALUES_B, CM, id), \
@@ -239,6 +239,11 @@
 	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
 	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
 	TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
+	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
+	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
+	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
+	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
+	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
 	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
 	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
 	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
@@ -327,11 +332,6 @@
 	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
 	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
 	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
-	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
-	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
-	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
-	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
-	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
 	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
 	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
 	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0bdf06969c83..f79871d1227d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1903,7 +1903,8 @@ static void update_dchubp_dpp(
 
 	//set scale and bias registers
 	build_prescale_params(&bns_params, plane_state);
-	dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params);
+	if (dpp->funcs->ipp_program_bias_and_scale)
+		dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params);
 
 	mpcc_cfg.dpp_id = hubp->inst;
 	mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
-- 
2.14.1

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[PATCH 10/73] drm/amd/display: Only update dchub if hubbub is available

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

Change-Id: Id3ccff0209ae76330eb346c4ffd3aa3b6bf1909b
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f79871d1227d..ebb39b8c1551 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2509,7 +2509,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
 
 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
 {
-	hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+	if (hws->ctx->dc->res_pool->hubbub != NULL)
+		hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
 }
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
-- 
2.14.1

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[PATCH 11/73] drm/amd/display: get remote dpcd caps for timing validation

[Harry Wentland]

From: Eric Yang <Eric.Yang2@amd.com>

Change-Id: Iebe803ec074af7648329af111217da2a50f8426c
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c    |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dc.h              |  1 +
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h     | 28 +++++++++++++++++++++++-
 4 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index be9a182d6fb3..a6a762a26fd2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1869,7 +1869,7 @@ enum dc_status dc_link_validate_mode_timing(
 		const struct dc_crtc_timing *timing)
 {
 	uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
-	struct dc_dongle_caps *dongle_caps = &link->link_status.dpcd_caps->dongle_caps;
+	struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
 
 	/* A hack to avoid failing any modes for EDID override feature on
 	 * topology change such as lower quality cable for DP or different dongle
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e97b42a03a2..cd87d85f1ce2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2132,7 +2132,7 @@ static void get_active_converter_info(
 
 				union dwnstream_port_caps_byte3_hdmi
 					hdmi_caps = {.raw = det_caps[3] };
-				union dwnstream_port_caps_byte1
+				union dwnstream_port_caps_byte2
 					hdmi_color_caps = {.raw = det_caps[2] };
 				link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
 					det_caps[1] * 25000;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 79e2ddbc3399..ee05b8ee3785 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1031,6 +1031,7 @@ struct dc_sink {
 
 	/* private to dc_sink.c */
 	struct kref refcount;
+
 };
 
 void dc_sink_retain(struct dc_sink *sink);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 77e2de69cca3..2726b02e006b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -255,7 +255,7 @@ enum dpcd_downstream_port_detailed_type {
 	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 };
 
-union dwnstream_port_caps_byte1 {
+union dwnstream_port_caps_byte2 {
 	struct {
 		uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
 		uint8_t RESERVED:6;
@@ -298,6 +298,32 @@ union dwnstream_port_caps_byte3_hdmi {
 
 /*4-byte structure for detailed capabilities of a down-stream port
 (DP-to-TMDS converter).*/
+union dwnstream_portxcaps {
+	struct {
+		union dwnstream_port_caps_byte0 byte0;
+		unsigned char max_TMDS_clock;   //byte1
+		union dwnstream_port_caps_byte2 byte2;
+
+		union {
+			union dwnstream_port_caps_byte3_dvi byteDVI;
+			union dwnstream_port_caps_byte3_hdmi byteHDMI;
+		} byte3;
+	} bytes;
+
+	unsigned char raw[4];
+};
+
+union downstream_port {
+	struct {
+		unsigned char   present:1;
+		unsigned char   type:2;
+		unsigned char   format_conv:1;
+		unsigned char   detailed_caps:1;
+		unsigned char   reserved:3;
+	} bits;
+	unsigned char raw;
+};
+
 
 union sink_status {
 	struct {
-- 
2.14.1

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[PATCH 12/73] drm/amd/display: Enalbe blank data double buffer after mpc disconnected.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: I60d84f57d93870769fdb2d8f1e870121c2a28f15
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 19 ++++++++++++++-----
 .../gpu/drm/amd/display/dc/inc/hw/timing_generator.h  |  2 ++
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index c178cc0bd426..5d1edb017b1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -290,6 +290,16 @@ static void tgn10_program_timing(
 
 }
 
+static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, bool enable)
+{
+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+	uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
+
+	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+			OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
+}
+
 /**
  * unblank_crtc
  * Call ASIC Control Object to UnBlank CRTC.
@@ -306,8 +316,7 @@ static void tgn10_unblank_crtc(struct timing_generator *tg)
 	 * this check will be removed.
 	 */
 	if (vertical_interrupt_enable)
-		REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-				OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 1);
+		tgn10_set_blank_data_double_buffer(tg, true);
 
 	REG_UPDATE_2(OTG_BLANK_CONTROL,
 			OTG_BLANK_DATA_EN, 0,
@@ -334,8 +343,7 @@ static void tgn10_blank_crtc(struct timing_generator *tg)
 			OTG_BLANK_DATA_EN, 1,
 			1, 100000);
 
-	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-			OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
+	tgn10_set_blank_data_double_buffer(tg, false);
 }
 
 static void tgn10_set_blank(struct timing_generator *tg,
@@ -1234,7 +1242,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.set_static_screen_control = tgn10_set_static_screen_control,
 		.set_test_pattern = tgn10_set_test_pattern,
 		.program_stereo = tgn10_program_stereo,
-		.is_stereo_left_eye = tgn10_is_stereo_left_eye
+		.is_stereo_left_eye = tgn10_is_stereo_left_eye,
+		.set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer
 };
 
 void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 75f7a01b9175..83f0b1d49e8b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -182,6 +182,8 @@ struct timing_generator_funcs {
 	void (*program_stereo)(struct timing_generator *tg,
 		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 	bool (*is_stereo_left_eye)(struct timing_generator *tg);
+
+	void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
 };
 
 #endif
-- 
2.14.1

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[PATCH 13/73] drm/amd/display: Add tg_init interface.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Clear OPTC underflow status when init_hw.

Change-Id: I96953ee2d842a53ee343da88cffbef1eac2df95b
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c     |  2 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 10 +++++++++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h |  2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h      |  2 ++
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ebb39b8c1551..dc37551399ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -742,6 +742,8 @@ static void dcn10_init_hw(struct dc *dc)
 		hwss_wait_for_blank_complete(tg);
 
 		dcn10_power_down_fe(dc, i);
+
+		tg->funcs->tg_init(tg);
 	}
 
 	for (i = 0; i < dc->res_pool->audio_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 5d1edb017b1c..819c4edd77a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1213,6 +1213,13 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
 			OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
 }
 
+static void tgn10_tg_init(struct timing_generator *tg)
+{
+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+	tgn10_set_blank_data_double_buffer(tg, true);
+	REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
+}
 
 static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.validate_timing = tgn10_validate_timing,
@@ -1243,7 +1250,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.set_test_pattern = tgn10_set_test_pattern,
 		.program_stereo = tgn10_program_stereo,
 		.is_stereo_left_eye = tgn10_is_stereo_left_eye,
-		.set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer
+		.set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer,
+		.tg_init = tgn10_tg_init,
 };
 
 void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index 395820606013..bb1cbfdc3554 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -210,6 +210,7 @@ struct dcn_tg_registers {
 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
 	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
 	SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
 	SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
 	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
@@ -330,6 +331,7 @@ struct dcn_tg_registers {
 	type OPTC_SRC_SEL;\
 	type OPTC_SEG0_SRC_SEL;\
 	type OPTC_UNDERFLOW_OCCURRED_STATUS;\
+	type OPTC_UNDERFLOW_CLEAR;\
 	type OPPBUF_ACTIVE_WIDTH;\
 	type OPPBUF_3D_VACT_SPACE1_SIZE;\
 	type VTG0_ENABLE;\
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 83f0b1d49e8b..f77dca87cbbc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -184,6 +184,8 @@ struct timing_generator_funcs {
 	bool (*is_stereo_left_eye)(struct timing_generator *tg);
 
 	void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
+
+	void (*tg_init)(struct timing_generator *tg);
 };
 
 #endif
-- 
2.14.1

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[PATCH 14/73] drm/amd/display: Both timing_sync and multisync need stream_count > 1

[Harry Wentland]

Previous code threw a warning about misleading indentation

Change-Id: I93e5998448e2c80d1b084231a3ef575bc1a0dfdd
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f3fd062bcdd2..6219dd000049 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -874,9 +874,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	}
 	result = dc->hwss.apply_ctx_to_hw(dc, context);
 
-	if (context->stream_count > 1)
+	if (context->stream_count > 1) {
 		enable_timing_multisync(dc, context);
 		program_timing_sync(dc, context);
+	}
 
 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-- 
2.14.1

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[PATCH 15/73] drm/amd/display: Don't use dc_link in link_encoder

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

dc_link is at a higher level than link_encoder, and we only want
higher-level components to be able to access lower-level ones,
not the other way around.

Change-Id: I634b117b386938fb7ddba50c50484fadd54ad485
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 +++---
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 34 +++++++---------
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  5 +--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 46 ++++++++++++----------
 .../amd/display/dc/dce110/dce110_hw_sequencer.h    |  4 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 ++
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  2 +-
 .../amd/display/dc/virtual/virtual_link_encoder.c  |  3 +-
 10 files changed, 57 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a6a762a26fd2..3b394a5f1c66 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1798,7 +1798,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
 		else
 			dp_disable_link_phy_mst(link, signal);
 	} else
-		link->link_enc->funcs->disable_output(link->link_enc, signal, link);
+		link->link_enc->funcs->disable_output(link->link_enc, signal);
 }
 
 bool dp_active_dongle_validate_timing(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 9a33b471270a..f2902569be2e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -89,7 +89,7 @@ void dp_enable_link_phy(
 
 	if (dc_is_dp_sst_signal(signal)) {
 		if (signal == SIGNAL_TYPE_EDP) {
-			link->dc->hwss.edp_power_control(link->link_enc, true);
+			link->dc->hwss.edp_power_control(link, true);
 			link_enc->funcs->enable_dp_output(
 						link_enc,
 						link_settings,
@@ -140,10 +140,10 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 	if (signal == SIGNAL_TYPE_EDP) {
 		link->dc->hwss.edp_backlight_control(link, false);
 		edp_receiver_ready_T9(link);
-		link->link_enc->funcs->disable_output(link->link_enc, signal, link);
-		link->dc->hwss.edp_power_control(link->link_enc, false);
+		link->link_enc->funcs->disable_output(link->link_enc, signal);
+		link->dc->hwss.edp_power_control(link, false);
 	} else
-		link->link_enc->funcs->disable_output(link->link_enc, signal, link);
+		link->link_enc->funcs->disable_output(link->link_enc, signal);
 
 	/* Clear current link setting.*/
 	memset(&link->cur_link_settings, 0,
@@ -286,8 +286,7 @@ void dp_retrain_link_dp_test(struct dc_link *link,
 
 			link->link_enc->funcs->disable_output(
 					link->link_enc,
-					SIGNAL_TYPE_DISPLAY_PORT,
-					link);
+					SIGNAL_TYPE_DISPLAY_PORT);
 
 			/* Clear current link setting. */
 			memset(&link->cur_link_settings, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index fe88852b4774..bad70c6b3aad 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -845,8 +845,6 @@ void dce110_link_encoder_hw_init(
 
 		ASSERT(result == BP_RESULT_OK);
 
-	} else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-		ctx->dc->hwss.edp_power_control(enc, true);
 	}
 	aux_initialize(enc110);
 
@@ -1033,8 +1031,7 @@ void dce110_link_encoder_enable_dp_mst_output(
  */
 void dce110_link_encoder_disable_output(
 	struct link_encoder *enc,
-	enum signal_type signal,
-	struct dc_link *link)
+	enum signal_type signal)
 {
 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 	struct dc_context *ctx = enc110->base.ctx;
@@ -1045,8 +1042,6 @@ void dce110_link_encoder_disable_output(
 		/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
 		return;
 	}
-	if (enc110->base.connector.id == CONNECTOR_ID_EDP)
-		ctx->dc->hwss.edp_backlight_control(link, false);
 	/* Power-down RX and disable GPU PHY should be paired.
 	 * Disabling PHY without powering down RX may cause
 	 * symbol lock loss, on which we will get DP Sink interrupt. */
@@ -1078,19 +1073,20 @@ void dce110_link_encoder_disable_output(
 	if (dc_is_dp_signal(signal))
 		link_encoder_disable(enc110);
 
-	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-		/* power down eDP panel */
-		/* TODO: Power control cause regression, we should implement
-		 * it properly, for now just comment it.
-		 *
-		 * link_encoder_edp_wait_for_hpd_ready(
-			link_enc,
-			link_enc->connector,
-			false);
-
-		 * link_encoder_edp_power_control(
-				link_enc, false); */
-	}
+	/*
+	 * TODO: Power control cause regression, we should implement
+	 * it properly, for now just comment it.
+	 */
+//	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
+//		/* power down eDP panel */
+//		link_encoder_edp_wait_for_hpd_ready(
+//				enc,
+//				enc->connector,
+//				false);
+//
+//		link_encoder_edp_power_control(
+//				enc, false);
+//	}
 }
 
 void dce110_link_encoder_dp_set_lane_settings(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 494067dedd03..8ca9afe47a2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -228,9 +228,8 @@ void dce110_link_encoder_enable_dp_mst_output(
 
 /* disable PHY output */
 void dce110_link_encoder_disable_output(
-	struct link_encoder *link_enc,
-	enum signal_type signal,
-	struct dc_link *link);
+	struct link_encoder *enc,
+	enum signal_type signal);
 
 /* set DP lane settings */
 void dce110_link_encoder_dp_set_lane_settings(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b4504f1f49c0..4135de2d7203 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -814,11 +814,11 @@ static enum bp_result link_transmitter_control(
  * eDP only.
  */
 void hwss_edp_wait_for_hpd_ready(
-	struct link_encoder *enc,
-	bool power_up)
+		struct dc_link *link,
+		bool power_up)
 {
-	struct dc_context *ctx = enc->ctx;
-	struct graphics_object_id connector = enc->connector;
+	struct dc_context *ctx = link->ctx;
+	struct graphics_object_id connector = link->link_enc->connector;
 	struct gpio *hpd;
 	bool edp_hpd_high = false;
 	uint32_t time_elapsed = 0;
@@ -882,16 +882,16 @@ void hwss_edp_wait_for_hpd_ready(
 }
 
 void hwss_edp_power_control(
-	struct link_encoder *enc,
-	bool power_up)
+		struct dc_link *link,
+		bool power_up)
 {
-	struct dc_context *ctx = enc->ctx;
+	struct dc_context *ctx = link->ctx;
 	struct dce_hwseq *hwseq = ctx->dc->hwseq;
 	struct bp_transmitter_control cntl = { 0 };
 	enum bp_result bp_result;
 
 
-	if (dal_graphics_object_id_get_connector_id(enc->connector)
+	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 			!= CONNECTOR_ID_EDP) {
 		BREAK_TO_DEBUGGER();
 		return;
@@ -907,11 +907,11 @@ void hwss_edp_power_control(
 		cntl.action = power_up ?
 			TRANSMITTER_CONTROL_POWER_ON :
 			TRANSMITTER_CONTROL_POWER_OFF;
-		cntl.transmitter = enc->transmitter;
-		cntl.connector_obj_id = enc->connector;
+		cntl.transmitter = link->link_enc->transmitter;
+		cntl.connector_obj_id = link->link_enc->connector;
 		cntl.coherent = false;
 		cntl.lanes_number = LANE_COUNT_FOUR;
-		cntl.hpd_sel = enc->hpd_source;
+		cntl.hpd_sel = link->link_enc->hpd_source;
 
 		bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 
@@ -925,7 +925,7 @@ void hwss_edp_power_control(
 				__func__, (power_up ? "On":"Off"));
 	}
 
-	hwss_edp_wait_for_hpd_ready(enc, true);
+	hwss_edp_wait_for_hpd_ready(link, true);
 }
 
 /*todo: cloned in stream enc, fix*/
@@ -934,14 +934,14 @@ void hwss_edp_power_control(
  * eDP only. Control the backlight of the eDP panel
  */
 void hwss_edp_backlight_control(
-	struct dc_link *link,
-	bool enable)
+		struct dc_link *link,
+		bool enable)
 {
-	struct dce_hwseq *hws = link->dc->hwseq;
-	struct dc_context *ctx = link->dc->ctx;
+	struct dc_context *ctx = link->ctx;
+	struct dce_hwseq *hws = ctx->dc->hwseq;
 	struct bp_transmitter_control cntl = { 0 };
 
-	if (dal_graphics_object_id_get_connector_id(link->link_id)
+	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 		!= CONNECTOR_ID_EDP) {
 		BREAK_TO_DEBUGGER();
 		return;
@@ -982,7 +982,7 @@ void hwss_edp_backlight_control(
 	 * Enable it in the future if necessary.
 	 */
 	/* dc_service_sleep_in_milliseconds(50); */
-	link_transmitter_control(link->dc->ctx->dc_bios, &cntl);
+	link_transmitter_control(ctx->dc_bios, &cntl);
 }
 
 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
@@ -1398,12 +1398,14 @@ static void power_down_encoders(struct dc *dc)
 
 			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
 				dp_receiver_power_ctrl(dc->links[i], false);
-			if (connector_id == CONNECTOR_ID_EDP)
+			if (connector_id == CONNECTOR_ID_EDP) {
 				signal = SIGNAL_TYPE_EDP;
+				hwss_edp_backlight_control(dc->links[i], false);
+			}
 		}
 
 		dc->links[i]->link_enc->funcs->disable_output(
-				dc->links[i]->link_enc, signal, dc->links[i]);
+				dc->links[i]->link_enc, signal);
 	}
 }
 
@@ -2539,6 +2541,10 @@ static void init_hw(struct dc *dc)
 		 * required signal (which may be different from the
 		 * default signal on connector). */
 		struct dc_link *link = dc->links[i];
+
+		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
+			dc->hwss.edp_power_control(link, true);
+
 		link->link_enc->funcs->hw_init(link->link_enc);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index 4d72bb99be93..2dd6ac637572 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -70,8 +70,8 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
 void dp_receiver_power_ctrl(struct dc_link *link, bool on);
 
 void hwss_edp_power_control(
-	struct link_encoder *enc,
-	bool power_up);
+		struct dc_link *link,
+		bool power_up);
 
 void hwss_edp_backlight_control(
 	struct dc_link *link,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index dc37551399ba..51b7cfe9581f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -723,6 +723,9 @@ static void dcn10_init_hw(struct dc *dc)
 		 */
 		struct dc_link *link = dc->links[i];
 
+		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
+			dc->hwss.edp_power_control(link, true);
+
 		link->link_enc->funcs->hw_init(link->link_enc);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 3d33bcda7059..8a08f0a97f94 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -111,7 +111,7 @@ struct link_encoder_funcs {
 		const struct dc_link_settings *link_settings,
 		enum clock_source_id clock_source);
 	void (*disable_output)(struct link_encoder *link_enc,
-		enum signal_type signal, struct dc_link *link);
+		enum signal_type signal);
 	void (*dp_set_lane_settings)(struct link_encoder *enc,
 		const struct link_training_settings *link_settings);
 	void (*dp_set_phy_pattern)(struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index cebbba345889..f3c5468854bd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -184,7 +184,7 @@ struct hw_sequencer_funcs {
 	void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
 	void (*optimize_shared_resources)(struct dc *dc);
 	void (*edp_power_control)(
-			struct link_encoder *enc,
+			struct dc_link *link,
 			bool enable);
 	void (*edp_backlight_control)(
 			struct dc_link *link,
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index 88c2bde3f039..57a54a7b89e5 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -58,8 +58,7 @@ static void virtual_link_encoder_enable_dp_mst_output(
 
 static void virtual_link_encoder_disable_output(
 	struct link_encoder *link_enc,
-	enum signal_type signal,
-	struct dc_link *link) {}
+	enum signal_type signal) {}
 
 static void virtual_link_encoder_dp_set_lane_settings(
 	struct link_encoder *enc,
-- 
2.14.1

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[PATCH 16/73] drm/amd/display: cache pwl params and scl_data to avoid extra programming

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

This saves us about 5000 reg writes per full update. This translates to about
40000 writes over the course of single eDP bootup.

Change-Id: If8e0c7bac744d8a3e2c56271c09453152025ccc8
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 41 ++++++++++------------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  6 ++--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  3 ++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 10 +++---
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h        |  8 ++---
 5 files changed, 30 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index c5f4d5caf976..e9cf9d1514eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -178,32 +178,14 @@ void dpp_reset(struct dpp *dpp_base)
 	dpp->filter_h = NULL;
 	dpp->filter_v = NULL;
 
-	/* set boundary mode to 0 */
-	REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
+	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
+	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
 }
 
 
 
 static void dpp1_cm_set_regamma_pwl(
-	struct dpp *dpp_base, const struct pwl_params *params)
-{
-	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-
-	dpp1_cm_power_on_regamma_lut(dpp_base, true);
-	dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
-
-	if (dpp->is_write_to_ram_a_safe)
-		dpp1_cm_program_regamma_luta_settings(dpp_base, params);
-	else
-		dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
-
-	dpp1_cm_program_regamma_lut(
-			dpp_base, params->rgb_resulted, params->hw_points_num);
-}
-
-static void dpp1_cm_set_regamma_mode(
-	struct dpp *dpp_base,
-	enum opp_regamma mode)
+	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
 {
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 	uint32_t re_mode = 0;
@@ -221,13 +203,27 @@ static void dpp1_cm_set_regamma_mode(
 		re_mode = 2;
 		break;
 	case OPP_REGAMMA_USER:
+		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
+			return;
+
+		dpp1_cm_power_on_regamma_lut(dpp_base, true);
+		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
+
+		if (dpp->is_write_to_ram_a_safe)
+			dpp1_cm_program_regamma_luta_settings(dpp_base, params);
+		else
+			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
+
+		dpp1_cm_program_regamma_lut(
+				dpp_base, params->rgb_resulted, params->hw_points_num);
+		dpp->pwl_data = *params;
+
 		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
 		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
 		break;
 	default:
 		break;
 	}
-
 	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
 	REG_UPDATE_2(OBUF_CONTROL,
 			OBUF_BYPASS, obuf_bypass,
@@ -454,7 +450,6 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
 		.opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
 		.opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
 		.opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
-		.opp_set_regamma_mode = dpp1_cm_set_regamma_mode,
 		.ipp_program_bias_and_scale = dpp1_program_bias_and_scale,
 		.ipp_set_degamma = dpp1_set_degamma,
 		.ipp_program_input_lut		= dpp1_program_input_lut,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 880e366568a3..8b894ebc4e17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -54,7 +54,6 @@
 	SRI(LB_MEMORY_CTRL, DSCL, id), \
 	SRI(DSCL_AUTOCAL, DSCL, id), \
 	SRI(SCL_BLACK_OFFSET, DSCL, id), \
-	SRI(DSCL_CONTROL, DSCL, id), \
 	SRI(SCL_TAP_CONTROL, DSCL, id), \
 	SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
 	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
@@ -194,7 +193,6 @@
 	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
 	TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
 	TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
-	TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
@@ -440,7 +438,6 @@
 	type AUTOCAL_PIPE_ID; \
 	type SCL_BLACK_OFFSET_RGB_Y; \
 	type SCL_BLACK_OFFSET_CBCR; \
-	type SCL_BOUNDARY_MODE; \
 	type SCL_V_NUM_TAPS; \
 	type SCL_H_NUM_TAPS; \
 	type SCL_V_NUM_TAPS_C; \
@@ -1038,7 +1035,6 @@ struct dcn_dpp_registers {
 	uint32_t LB_MEMORY_CTRL;
 	uint32_t DSCL_AUTOCAL;
 	uint32_t SCL_BLACK_OFFSET;
-	uint32_t DSCL_CONTROL;
 	uint32_t SCL_TAP_CONTROL;
 	uint32_t SCL_COEF_RAM_TAP_SELECT;
 	uint32_t SCL_COEF_RAM_TAP_DATA;
@@ -1284,6 +1280,8 @@ struct dcn10_dpp {
 	int lb_memory_size;
 	int lb_bits_per_entry;
 	bool is_write_to_ram_a_safe;
+	struct scaler_data scl_data;
+	struct pwl_params pwl_data;
 };
 
 enum dcn10_input_csc_select {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index cbad36410b32..242a568294e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -648,6 +648,8 @@ void dpp1_dscl_set_scaler_manual_scale(
 	bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
 				&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
 
+	if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
+		return;
 	/* Recout */
 	dpp1_dscl_set_recout(dpp, &scl_data->recout);
 
@@ -699,4 +701,5 @@ void dpp1_dscl_set_scaler_manual_scale(
 		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
 
 	dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
+	dpp->scl_data = *scl_data;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 51b7cfe9581f..7579e51761cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1235,13 +1235,12 @@ static bool dcn10_set_output_transfer_func(
 			TF_TYPE_PREDEFINED &&
 		stream->out_transfer_func->tf ==
 			TRANSFER_FUNCTION_SRGB) {
-		dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_SRGB);
+		dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 	} else if (dcn10_translate_regamma_to_hw_format(
 				stream->out_transfer_func, &dpp->regamma_params)) {
-			dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params);
-			dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_USER);
+			dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
 	} else {
-		dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_BYPASS);
+		dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
 	}
 
 	return true;
@@ -2118,8 +2117,7 @@ static void dcn10_apply_ctx_for_surface(
 
 	if (num_planes == 0) {
 		for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
-			struct pipe_ctx *old_pipe_ctx =
-							&dc->current_state->res_ctx.pipe_ctx[i];
+			struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 
 			if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) {
 				old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 6eca95931ee1..71078d184289 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -92,11 +92,9 @@ struct dpp_funcs {
 			const struct pwl_params *params);
 
 	void (*opp_program_regamma_pwl)(
-		struct dpp *dpp, const struct pwl_params *params);
-
-	void (*opp_set_regamma_mode)(
-			struct dpp *dpp_base,
-			enum opp_regamma mode);
+		struct dpp *dpp,
+		const struct pwl_params *params,
+		enum opp_regamma mode);
 
 	void (*ipp_program_bias_and_scale)(
 			struct dpp *dpp,
-- 
2.14.1

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[PATCH 17/73] drm/amd/display: dal 3.1.12

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: I7c519d233b07bb45e27277aaa0ce046f54a94ef8
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ee05b8ee3785..cb1e39288fa3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.11"
+#define DC_VER "3.1.12"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 18/73] drm/amd/display: Add OPP DPG blank function

[Harry Wentland]

From: Eric Bernstein <eric.bernstein@amd.com>

Added a function to blank data using OPP DPG.
Clean up code to prepare for pseudocode review with HW.

Change-Id: Iac5e99e1eb72b8dd74c244e8d06d54bae9ab3ce2
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 62 +++++++++++++++---------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 45 +++--------------
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h      |  6 +++
 3 files changed, 51 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index a136f70b7a3c..71385a004f52 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -38,6 +38,24 @@
 	oppn10->base.ctx
 
 
+enum dpg_mode {
+	/* RGB colour block mode */
+	DPG_MODE_RGB_COLOUR_BLOCK,
+	/* YCbCr-601 colour block mode */
+	DPG_MODE_YCBCR_601_COLOUR_BLOCK,
+	/* YCbCr-709 colour block mode */
+	DPG_MODE_YCBCR_709_COLOUR_BLOCK,
+	/* Vertical bar mode */
+	DPG_MODE_VERTICAL_BAR,
+	/* Horizontal bar mode */
+	DPG_MODE_HORIZONTAL_BAR,
+	/* Single ramp mode */
+	DPG_MODE_RGB_SINGLE_RAMP,
+	/* Dual ramp mode */
+	DPG_MODE_RGB_DUAL_RAMP,
+	/* RGB XR BIAS mode */
+	DPG_MODE_RGB_XR_BIAS
+};
 
 /************* FORMATTER ************/
 
@@ -47,7 +65,7 @@
  *	2) enable truncation
  *	3) HW remove 12bit FMT support for DCE11 power saving reason.
  */
-static void set_truncation(
+static void opp1_set_truncation(
 		struct dcn10_opp *oppn10,
 		const struct bit_depth_reduction_params *params)
 {
@@ -57,7 +75,7 @@ static void set_truncation(
 		FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
 }
 
-static void set_spatial_dither(
+static void opp1_set_spatial_dither(
 	struct dcn10_opp *oppn10,
 	const struct bit_depth_reduction_params *params)
 {
@@ -136,14 +154,14 @@ static void set_spatial_dither(
 			FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 }
 
-static void oppn10_program_bit_depth_reduction(
+static void opp1_program_bit_depth_reduction(
 	struct output_pixel_processor *opp,
 	const struct bit_depth_reduction_params *params)
 {
 	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 
-	set_truncation(oppn10, params);
-	set_spatial_dither(oppn10, params);
+	opp1_set_truncation(oppn10, params);
+	opp1_set_spatial_dither(oppn10, params);
 	/* TODO
 	 * set_temporal_dither(oppn10, params);
 	 */
@@ -156,7 +174,7 @@ static void oppn10_program_bit_depth_reduction(
  *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
  *		1: YCbCr 4:2:2
  */
-static void set_pixel_encoding(
+static void opp1_set_pixel_encoding(
 	struct dcn10_opp *oppn10,
 	const struct clamping_and_pixel_encoding_params *params)
 {
@@ -186,7 +204,7 @@ static void set_pixel_encoding(
  *		7 for programable
  *	2) Enable clamp if Limited range requested
  */
-static void opp_set_clamping(
+static void opp1_set_clamping(
 	struct dcn10_opp *oppn10,
 	const struct clamping_and_pixel_encoding_params *params)
 {
@@ -224,7 +242,7 @@ static void opp_set_clamping(
 
 }
 
-static void oppn10_set_dyn_expansion(
+static void opp1_set_dyn_expansion(
 	struct output_pixel_processor *opp,
 	enum dc_color_space color_sp,
 	enum dc_color_depth color_dpth,
@@ -264,17 +282,17 @@ static void oppn10_set_dyn_expansion(
 	}
 }
 
-static void opp_program_clamping_and_pixel_encoding(
+static void opp1_program_clamping_and_pixel_encoding(
 	struct output_pixel_processor *opp,
 	const struct clamping_and_pixel_encoding_params *params)
 {
 	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 
-	opp_set_clamping(oppn10, params);
-	set_pixel_encoding(oppn10, params);
+	opp1_set_clamping(oppn10, params);
+	opp1_set_pixel_encoding(oppn10, params);
 }
 
-static void oppn10_program_fmt(
+static void opp1_program_fmt(
 	struct output_pixel_processor *opp,
 	struct bit_depth_reduction_params *fmt_bit_depth,
 	struct clamping_and_pixel_encoding_params *clamping)
@@ -286,20 +304,18 @@ static void oppn10_program_fmt(
 
 	/* dithering is affected by <CrtcSourceSelect>, hence should be
 	 * programmed afterwards */
-	oppn10_program_bit_depth_reduction(
+	opp1_program_bit_depth_reduction(
 		opp,
 		fmt_bit_depth);
 
-	opp_program_clamping_and_pixel_encoding(
+	opp1_program_clamping_and_pixel_encoding(
 		opp,
 		clamping);
 
 	return;
 }
 
-
-
-static void oppn10_set_stereo_polarity(
+static void opp1_set_stereo_polarity(
 		struct output_pixel_processor *opp,
 		bool enable, bool rightEyePolarity)
 {
@@ -312,18 +328,18 @@ static void oppn10_set_stereo_polarity(
 /* Constructor, Destructor               */
 /*****************************************/
 
-static void dcn10_opp_destroy(struct output_pixel_processor **opp)
+static void opp1_destroy(struct output_pixel_processor **opp)
 {
 	kfree(TO_DCN10_OPP(*opp));
 	*opp = NULL;
 }
 
 static struct opp_funcs dcn10_opp_funcs = {
-		.opp_set_dyn_expansion = oppn10_set_dyn_expansion,
-		.opp_program_fmt = oppn10_program_fmt,
-		.opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction,
-		.opp_set_stereo_polarity = oppn10_set_stereo_polarity,
-		.opp_destroy = dcn10_opp_destroy
+		.opp_set_dyn_expansion = opp1_set_dyn_expansion,
+		.opp_program_fmt = opp1_program_fmt,
+		.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
+		.opp_set_stereo_polarity = opp1_set_stereo_polarity,
+		.opp_destroy = opp1_destroy
 };
 
 void dcn10_opp_construct(struct dcn10_opp *oppn10,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index 790ce6014832..cdb220ed858e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -78,36 +78,14 @@
 	type DPG_MODE; \
 	type DPG_VRES; \
 	type DPG_HRES; \
+	type DPG_ACTIVE_WIDTH; \
+	type DPG_ACTIVE_HEIGHT; \
 	type DPG_COLOUR0_R_CR; \
 	type DPG_COLOUR1_R_CR; \
 	type DPG_COLOUR0_B_CB; \
 	type DPG_COLOUR1_B_CB; \
 	type DPG_COLOUR0_G_Y; \
 	type DPG_COLOUR1_G_Y; \
-	type CM_OCSC_C11; \
-	type CM_OCSC_C12; \
-	type CM_OCSC_C13; \
-	type CM_OCSC_C14; \
-	type CM_OCSC_C21; \
-	type CM_OCSC_C22; \
-	type CM_OCSC_C23; \
-	type CM_OCSC_C24; \
-	type CM_OCSC_C31; \
-	type CM_OCSC_C32; \
-	type CM_OCSC_C33; \
-	type CM_OCSC_C34; \
-	type CM_COMB_C11; \
-	type CM_COMB_C12; \
-	type CM_COMB_C13; \
-	type CM_COMB_C14; \
-	type CM_COMB_C21; \
-	type CM_COMB_C22; \
-	type CM_COMB_C23; \
-	type CM_COMB_C24; \
-	type CM_COMB_C31; \
-	type CM_COMB_C32; \
-	type CM_COMB_C33; \
-	type CM_COMB_C34; \
 	type FMT_TRUNCATE_EN; \
 	type FMT_TRUNCATE_DEPTH; \
 	type FMT_TRUNCATE_MODE; \
@@ -129,33 +107,22 @@
 	type FMT_DYNAMIC_EXP_EN; \
 	type FMT_DYNAMIC_EXP_MODE; \
 	type FMT_MAP420MEM_PWR_FORCE; \
-	type FMT_STEREOSYNC_OVERRIDE
+	type FMT_STEREOSYNC_OVERRIDE;
 
 struct dcn10_opp_shift {
-	OPP_DCN10_REG_FIELD_LIST(uint8_t);
+	OPP_DCN10_REG_FIELD_LIST(uint8_t)
 };
 
 struct dcn10_opp_mask {
-	OPP_DCN10_REG_FIELD_LIST(uint32_t);
+	OPP_DCN10_REG_FIELD_LIST(uint32_t)
 };
 
 struct dcn10_opp_registers {
 	uint32_t DPG_CONTROL;
+	uint32_t DPG_DIMENSIONS;
 	uint32_t DPG_COLOUR_B_CB;
 	uint32_t DPG_COLOUR_G_Y;
 	uint32_t DPG_COLOUR_R_CR;
-	uint32_t CM_OCSC_C11_C12;
-	uint32_t CM_OCSC_C13_C14;
-	uint32_t CM_OCSC_C21_C22;
-	uint32_t CM_OCSC_C23_C24;
-	uint32_t CM_OCSC_C31_C32;
-	uint32_t CM_OCSC_C33_C34;
-	uint32_t CM_COMB_C11_C12;
-	uint32_t CM_COMB_C13_C14;
-	uint32_t CM_COMB_C21_C22;
-	uint32_t CM_COMB_C23_C24;
-	uint32_t CM_COMB_C31_C32;
-	uint32_t CM_COMB_C33_C34;
 	uint32_t FMT_BIT_DEPTH_CONTROL;
 	uint32_t FMT_CONTROL;
 	uint32_t FMT_DITHER_RAND_R_SEED;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 75adb8fec551..8141b677fda9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -284,6 +284,12 @@ struct opp_funcs {
 	void (*opp_set_test_pattern)(
 			struct output_pixel_processor *opp,
 			bool enable);
+
+	void (*opp_dpg_blank_enable)(
+			struct output_pixel_processor *opp,
+			bool enable,
+			int width,
+			int height);
 };
 
 #endif
-- 
2.14.1

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[PATCH 19/73] drm/amd/display: call set csc_default if enable adjustment is false

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

Change-Id: Id7507b6af4ab877fc10c5549985ac2633fe3f124
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h          | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c       | 6 ++----
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h               | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 8b894ebc4e17..4355cc21b111 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1381,7 +1381,7 @@ void dpp1_cm_set_output_csc_adjustment(
 
 void dpp1_cm_set_output_csc_default(
 		struct dpp *dpp_base,
-		const struct default_adjustment *default_adjust);
+		enum dc_color_space colorspace);
 
 void dpp1_cm_set_gamut_remap(
 	struct dpp *dpp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 9cb44c90e746..bb430c0ec1b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -225,14 +225,13 @@ void dpp1_cm_set_gamut_remap(
 
 void dpp1_cm_set_output_csc_default(
 		struct dpp *dpp_base,
-		const struct default_adjustment *default_adjust)
+		enum dc_color_space colorspace)
 {
 
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 	uint32_t ocsc_mode = 0;
 
-	if (default_adjust != NULL) {
-		switch (default_adjust->out_color_space) {
+	switch (colorspace) {
 		case COLOR_SPACE_SRGB:
 		case COLOR_SPACE_2020_RGB_FULLRANGE:
 			ocsc_mode = 0;
@@ -253,7 +252,6 @@ void dpp1_cm_set_output_csc_default(
 		case COLOR_SPACE_UNKNOWN:
 		default:
 			break;
-		}
 	}
 
 	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7579e51761cb..81192d68ce65 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1608,6 +1608,8 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
 			tbl_entry.color_space = color_space;
 			//tbl_entry.regval = matrix;
 			pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
+	} else {
+		pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 71078d184289..3b1486c3d05c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -64,7 +64,7 @@ struct dpp_funcs {
 
 	void (*opp_set_csc_default)(
 		struct dpp *dpp,
-		const struct default_adjustment *default_adjust);
+		enum dc_color_space colorspace);
 
 	void (*opp_set_csc_adjustment)(
 		struct dpp *dpp,
-- 
2.14.1

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[PATCH 20/73] drm/amd/display: dal 3.1.13

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: I8f2727ef40b40026483d2a0e465fb7f9b3916e31
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index cb1e39288fa3..fbafc8b93a85 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.12"
+#define DC_VER "3.1.13"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 21/73] drm/amd/display: renaming dpp function to follow naming convention

[Harry Wentland]

From: Yue Hin Lau <Yuehin.Lau@amd.com>

Change-Id: I01d8cc3095891bc44dcfb319729975b3dad6510e
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Yuehin Lau <Yuehin.Lau@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 28 ++++++++++-----------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 29 +++++++++++-----------
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h        | 28 ++++++++++-----------
 3 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index e9cf9d1514eb..21eba82aba97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -442,20 +442,20 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
 		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
 		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
-		.opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
-		.opp_set_csc_default = dpp1_cm_set_output_csc_default,
-		.opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
-		.opp_program_regamma_lut = dpp1_cm_program_regamma_lut,
-		.opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
-		.opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
-		.opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
-		.opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
-		.ipp_program_bias_and_scale = dpp1_program_bias_and_scale,
-		.ipp_set_degamma = dpp1_set_degamma,
-		.ipp_program_input_lut		= dpp1_program_input_lut,
-		.ipp_program_degamma_pwl	= dpp1_set_degamma_pwl,
-		.ipp_setup			= dpp1_cnv_setup,
-		.ipp_full_bypass		= dpp1_full_bypass,
+		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
+		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
+		.dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
+		.dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
+		.dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
+		.dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
+		.dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
+		.dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
+		.dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
+		.dpp_set_degamma = dpp1_set_degamma,
+		.dpp_program_input_lut		= dpp1_program_input_lut,
+		.dpp_program_degamma_pwl	= dpp1_set_degamma_pwl,
+		.dpp_setup			= dpp1_cnv_setup,
+		.dpp_full_bypass		= dpp1_full_bypass,
 		.set_cursor_attributes = dpp1_set_cursor_attributes,
 		.set_cursor_position = dpp1_set_cursor_position,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 81192d68ce65..2496a54c998d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -869,23 +869,23 @@ static bool dcn10_set_input_transfer_func(
 		tf = plane_state->in_transfer_func;
 
 	if (plane_state->gamma_correction && dce_use_lut(plane_state))
-		dpp_base->funcs->ipp_program_input_lut(dpp_base,
+		dpp_base->funcs->dpp_program_input_lut(dpp_base,
 				plane_state->gamma_correction);
 
 	if (tf == NULL)
-		dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
+		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 	else if (tf->type == TF_TYPE_PREDEFINED) {
 		switch (tf->tf) {
 		case TRANSFER_FUNCTION_SRGB:
-			dpp_base->funcs->ipp_set_degamma(dpp_base,
+			dpp_base->funcs->dpp_set_degamma(dpp_base,
 					IPP_DEGAMMA_MODE_HW_sRGB);
 			break;
 		case TRANSFER_FUNCTION_BT709:
-			dpp_base->funcs->ipp_set_degamma(dpp_base,
+			dpp_base->funcs->dpp_set_degamma(dpp_base,
 					IPP_DEGAMMA_MODE_HW_xvYCC);
 			break;
 		case TRANSFER_FUNCTION_LINEAR:
-			dpp_base->funcs->ipp_set_degamma(dpp_base,
+			dpp_base->funcs->dpp_set_degamma(dpp_base,
 					IPP_DEGAMMA_MODE_BYPASS);
 			break;
 		case TRANSFER_FUNCTION_PQ:
@@ -896,7 +896,7 @@ static bool dcn10_set_input_transfer_func(
 			break;
 		}
 	} else if (tf->type == TF_TYPE_BYPASS) {
-		dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
+		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 	} else {
 		/*TF_TYPE_DISTRIBUTED_POINTS*/
 		result = false;
@@ -1235,12 +1235,12 @@ static bool dcn10_set_output_transfer_func(
 			TF_TYPE_PREDEFINED &&
 		stream->out_transfer_func->tf ==
 			TRANSFER_FUNCTION_SRGB) {
-		dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
+		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 	} else if (dcn10_translate_regamma_to_hw_format(
 				stream->out_transfer_func, &dpp->regamma_params)) {
-			dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
+			dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
 	} else {
-		dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
+		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
 	}
 
 	return true;
@@ -1607,9 +1607,10 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
 
 			tbl_entry.color_space = color_space;
 			//tbl_entry.regval = matrix;
-			pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
+
+			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
 	} else {
-		pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
+		pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
 	}
 }
 
@@ -1901,7 +1902,7 @@ static void update_dchubp_dpp(
 				);
 
 	// program the input csc
-	dpp->funcs->ipp_setup(dpp,
+	dpp->funcs->dpp_setup(dpp,
 			plane_state->format,
 			EXPANSION_MODE_ZERO,
 			plane_state->input_csc_color_matrix,
@@ -1909,8 +1910,8 @@ static void update_dchubp_dpp(
 
 	//set scale and bias registers
 	build_prescale_params(&bns_params, plane_state);
-	if (dpp->funcs->ipp_program_bias_and_scale)
-		dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params);
+	if (dpp->funcs->dpp_program_bias_and_scale)
+		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 
 	mpcc_cfg.dpp_id = hubp->inst;
 	mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 3b1486c3d05c..ccb4896975c2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -62,63 +62,63 @@ struct dpp_funcs {
 			struct dpp *dpp,
 			const struct dpp_grph_csc_adjustment *adjust);
 
-	void (*opp_set_csc_default)(
+	void (*dpp_set_csc_default)(
 		struct dpp *dpp,
 		enum dc_color_space colorspace);
 
-	void (*opp_set_csc_adjustment)(
+	void (*dpp_set_csc_adjustment)(
 		struct dpp *dpp,
 		const struct out_csc_color_matrix *tbl_entry);
 
-	void (*opp_power_on_regamma_lut)(
+	void (*dpp_power_on_regamma_lut)(
 		struct dpp *dpp,
 		bool power_on);
 
-	void (*opp_program_regamma_lut)(
+	void (*dpp_program_regamma_lut)(
 			struct dpp *dpp,
 			const struct pwl_result_data *rgb,
 			uint32_t num);
 
-	void (*opp_configure_regamma_lut)(
+	void (*dpp_configure_regamma_lut)(
 			struct dpp *dpp,
 			bool is_ram_a);
 
-	void (*opp_program_regamma_lutb_settings)(
+	void (*dpp_program_regamma_lutb_settings)(
 			struct dpp *dpp,
 			const struct pwl_params *params);
 
-	void (*opp_program_regamma_luta_settings)(
+	void (*dpp_program_regamma_luta_settings)(
 			struct dpp *dpp,
 			const struct pwl_params *params);
 
-	void (*opp_program_regamma_pwl)(
+	void (*dpp_program_regamma_pwl)(
 		struct dpp *dpp,
 		const struct pwl_params *params,
 		enum opp_regamma mode);
 
-	void (*ipp_program_bias_and_scale)(
+	void (*dpp_program_bias_and_scale)(
 			struct dpp *dpp,
 			struct dc_bias_and_scale *params);
 
-	void (*ipp_set_degamma)(
+	void (*dpp_set_degamma)(
 			struct dpp *dpp_base,
 			enum ipp_degamma_mode mode);
 
-	void (*ipp_program_input_lut)(
+	void (*dpp_program_input_lut)(
 			struct dpp *dpp_base,
 			const struct dc_gamma *gamma);
 
-	void (*ipp_program_degamma_pwl)(struct dpp *dpp_base,
+	void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
 									 const struct pwl_params *params);
 
-	void (*ipp_setup)(
+	void (*dpp_setup)(
 			struct dpp *dpp_base,
 			enum surface_pixel_format format,
 			enum expansion_mode mode,
 			struct csc_transform input_csc_color_matrix,
 			enum dc_color_space input_color_space);
 
-	void (*ipp_full_bypass)(struct dpp *dpp_base);
+	void (*dpp_full_bypass)(struct dpp *dpp_base);
 
 	void (*set_cursor_attributes)(
 			struct dpp *dpp_base,
-- 
2.14.1

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[PATCH 22/73] drm/amd/display: dal 3.1.14

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: I87463dfba34a246c9ec5f2a0cf417b9943683f7e
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index fbafc8b93a85..86a9c927a312 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.13"
+#define DC_VER "3.1.14"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 23/73] drm/amd/display: Refactor disable front end pipes.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

There are different code to disable front end, it is
difficult to debug and adding new process.
This refactor makes all disable front end call the same
functions.

Change-Id: Ia88b26851bcea426104a8dd9093b912d03424c9a
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   3 +
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  15 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  10 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 262 +++++++++++----------
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   2 +-
 5 files changed, 154 insertions(+), 138 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 6d64a069648e..88a004cc2690 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1064,6 +1064,9 @@ bool dcn_validate_bandwidth(
 					hsplit_pipe->stream = NULL;
 					hsplit_pipe->top_pipe = NULL;
 					hsplit_pipe->bottom_pipe = NULL;
+					/* Clear plane_res and stream_res */
+					memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
+					memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
 					resource_build_scaling_params(pipe);
 				}
 				/* for now important to do this after pipe split for building e2e params */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6219dd000049..16d645d6da25 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -924,9 +924,11 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 	post_surface_trace(dc);
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
-		if (context->res_ctx.pipe_ctx[i].stream == NULL
-				|| context->res_ctx.pipe_ctx[i].plane_state == NULL)
-			dc->hwss.power_down_front_end(dc, i);
+		if (context->res_ctx.pipe_ctx[i].stream == NULL ||
+		    context->res_ctx.pipe_ctx[i].plane_state == NULL) {
+			context->res_ctx.pipe_ctx[i].pipe_idx = i;
+			dc->hwss.power_down_front_end(dc, &context->res_ctx.pipe_ctx[i]);
+		}
 
 	/* 3rd param should be true, temp w/a for RV*/
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -1300,8 +1302,11 @@ static void commit_planes_for_stream(struct dc *dc,
 		if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state)
 			continue;
 
-		if (!pipe_ctx->top_pipe && pipe_ctx->stream) {
-			struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream);
+		if (!pipe_ctx->top_pipe &&
+		    pipe_ctx->stream &&
+		    pipe_ctx->stream == stream) {
+			struct dc_stream_status *stream_status =
+					stream_get_status(context, pipe_ctx->stream);
 
 			dc->hwss.apply_ctx_for_surface(
 					dc, pipe_ctx->stream, stream_status->plane_count, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 4135de2d7203..a50e24f95ca9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1466,7 +1466,9 @@ static void disable_vga_and_power_gate_all_controllers(
 		enable_display_pipe_clock_gating(ctx,
 				true);
 
-		dc->hwss.power_down_front_end(dc, i);
+		dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
+		dc->hwss.power_down_front_end(dc,
+			&dc->current_state->res_ctx.pipe_ctx[i]);
 	}
 }
 
@@ -1888,7 +1890,7 @@ static void dce110_reset_hw_ctx_wrap(
 			if (old_clk)
 				old_clk->funcs->cs_power_down(old_clk);
 
-			dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
+			dc->hwss.power_down_front_end(dc, pipe_ctx_old);
 
 			pipe_ctx_old->stream = NULL;
 		}
@@ -2948,8 +2950,10 @@ static void dce110_apply_ctx_for_surface(
 	}
 }
 
-static void dce110_power_down_fe(struct dc *dc, int fe_idx)
+static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
+	int fe_idx = pipe_ctx->pipe_idx;
+
 	/* Do not power down fe when stream is active on dce*/
 	if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
 		return;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2496a54c998d..9def1038ddce 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -558,13 +558,15 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 }
 
 /* trigger HW to start disconnect plane from stream on the next vsync */
-static void plane_atomic_disconnect(struct dc *dc,
-		int fe_idx)
+static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
+	int fe_idx = pipe_ctx->pipe_idx;
 	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 	struct mpc *mpc = dc->res_pool->mpc;
 	int opp_id, z_idx;
 	int mpcc_id = -1;
+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+	struct dce_hwseq *hws = dc->hwseq;
 
 	/* look at tree rather than mi here to know if we already reset */
 	for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
@@ -583,29 +585,56 @@ static void plane_atomic_disconnect(struct dc *dc,
 	if (opp_id == dc->res_pool->pipe_count)
 		return;
 
-	if (dc->debug.sanity_checks)
-		dcn10_verify_allow_pstate_change_high(dc);
-	hubp->funcs->dcc_control(hubp, false, false);
+	mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
+					   dc->res_pool->opps[opp_id]->inst, fe_idx);
+
+	if (hubp->funcs->hubp_disconnect)
+		hubp->funcs->hubp_disconnect(hubp);
+
 	if (dc->debug.sanity_checks)
 		dcn10_verify_allow_pstate_change_high(dc);
 
-	mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
-			dc->res_pool->opps[opp_id]->inst, fe_idx);
+	if (pipe_ctx->top_pipe) {
+		pipe_ctx->top_pipe->bottom_pipe = NULL;
+		pipe_ctx->top_pipe = NULL;
+		pipe_ctx->stream = NULL;
+		memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
+		memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
+	}
+
+	if (pipe_ctx->bottom_pipe) {
+		pipe_ctx->bottom_pipe->top_pipe = NULL;
+		pipe_ctx->bottom_pipe = NULL;
+	}
+	pipe_ctx->plane_state = NULL;
+
+	/* TODO: Move to tg. */
+	REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst],
+			VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
 }
 
 /* disable HW used by plane.
  * note:  cannot disable until disconnect is complete */
-static void plane_atomic_disable(struct dc *dc,
-		int fe_idx)
+static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
+	int fe_idx = pipe_ctx->pipe_idx;
 	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 	struct mpc *mpc = dc->res_pool->mpc;
 	int opp_id = hubp->opp_id;
+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+
+	if (tg == NULL)
+		return;
 
 	if (opp_id == 0xf)
 		return;
 
+	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+		REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
+				VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
+				1, 100000);
+
 	mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
 	dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
 	/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
@@ -630,62 +659,52 @@ static void plane_atomic_disable(struct dc *dc,
 		dcn10_verify_allow_pstate_change_high(dc);
 }
 
-static void reset_front_end(
-		struct dc *dc,
-		int fe_idx)
+/* kill power to plane hw
+ * note: cannot power down until plane is disable
+ */
+static void plane_atomic_power_down(struct dc *dc, int fe_idx)
 {
 	struct dce_hwseq *hws = dc->hwseq;
-	struct timing_generator *tg;
-	int opp_id = dc->res_pool->hubps[fe_idx]->opp_id;
+	struct dpp *dpp = dc->res_pool->dpps[fe_idx];
 
-	/*Already reset*/
-	if (opp_id == 0xf)
-		return;
+	if (REG(DC_IP_REQUEST_CNTL)) {
+		REG_SET(DC_IP_REQUEST_CNTL, 0,
+				IP_REQUEST_EN, 1);
+		dpp_pg_control(hws, fe_idx, false);
+		hubp_pg_control(hws, fe_idx, false);
+		dpp->funcs->dpp_reset(dpp);
+		REG_SET(DC_IP_REQUEST_CNTL, 0,
+				IP_REQUEST_EN, 0);
+		dm_logger_write(dc->ctx->logger, LOG_DEBUG,
+				"Power gated front end %d\n", fe_idx);
+	}
+}
 
-	tg = dc->res_pool->timing_generators[opp_id];
-	tg->funcs->lock(tg);
+static void dcn10_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+	int fe_idx = pipe_ctx->pipe_idx;
+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
 
-	plane_atomic_disconnect(dc, fe_idx);
+	if (tg != NULL) {
+		tg->funcs->lock(tg);
 
-	REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
-	tg->funcs->unlock(tg);
+		plane_atomic_disconnect(dc, pipe_ctx);
 
-	if (dc->debug.sanity_checks)
-		dcn10_verify_allow_pstate_change_high(dc);
+		tg->funcs->unlock(tg);
 
-	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-		REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
-				VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
-				1, 100000);
+		if (dc->debug.sanity_checks)
+			dcn10_verify_allow_pstate_change_high(dc);
 
-	plane_atomic_disable(dc, fe_idx);
+		plane_atomic_disable(dc, pipe_ctx);
+	}
+
+	plane_atomic_power_down(dc, fe_idx);
 
 	dm_logger_write(dc->ctx->logger, LOG_DC,
 					"Reset front end %d\n",
 					fe_idx);
 }
 
-static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
-{
-	struct dce_hwseq *hws = dc->hwseq;
-	struct dpp *dpp = dc->res_pool->dpps[fe_idx];
-
-	reset_front_end(dc, fe_idx);
-
-	REG_SET(DC_IP_REQUEST_CNTL, 0,
-			IP_REQUEST_EN, 1);
-	dpp_pg_control(hws, fe_idx, false);
-	hubp_pg_control(hws, fe_idx, false);
-	dpp->funcs->dpp_reset(dpp);
-	REG_SET(DC_IP_REQUEST_CNTL, 0,
-			IP_REQUEST_EN, 0);
-	dm_logger_write(dc->ctx->logger, LOG_DEBUG,
-			"Power gated front end %d\n", fe_idx);
-
-	if (dc->debug.sanity_checks)
-		dcn10_verify_allow_pstate_change_high(dc);
-}
-
 static void dcn10_init_hw(struct dc *dc)
 {
 	int i;
@@ -744,7 +763,7 @@ static void dcn10_init_hw(struct dc *dc)
 		tg->funcs->set_blank(tg, true);
 		hwss_wait_for_blank_complete(tg);
 
-		dcn10_power_down_fe(dc, i);
+		plane_atomic_power_down(dc, i);
 
 		tg->funcs->tg_init(tg);
 	}
@@ -1988,8 +2007,6 @@ static void program_all_pipe_in_tree(
 			dcn10_verify_allow_pstate_change_high(dc);
 		}
 
-		pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
-
 		pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 		pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 		pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
@@ -2097,62 +2114,75 @@ static void ready_shared_resources(struct dc *dc, struct dc_state *context)
 		dcn10_pplib_apply_display_requirements(dc, context);
 }
 
+static struct pipe_ctx *find_top_pipe_for_stream(
+		struct dc *dc,
+		struct dc_state *context,
+		const struct dc_stream_state *stream)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *old_pipe_ctx =
+				&dc->current_state->res_ctx.pipe_ctx[i];
+
+		if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
+			continue;
+
+		if (pipe_ctx->stream != stream)
+			continue;
+
+		if (!pipe_ctx->top_pipe)
+			return pipe_ctx;
+	}
+	return NULL;
+}
+
 static void dcn10_apply_ctx_for_surface(
 		struct dc *dc,
 		const struct dc_stream_state *stream,
 		int num_planes,
 		struct dc_state *context)
 {
-	int i, be_idx;
+	int i;
+	struct timing_generator *tg;
+	bool removed_pipe[4] = { false };
+
+	struct pipe_ctx *top_pipe_to_program =
+			find_top_pipe_for_stream(dc, context, stream);
+
+	if (!top_pipe_to_program)
+		return;
+
+	tg = top_pipe_to_program->stream_res.tg;
 
 	if (dc->debug.sanity_checks)
 		dcn10_verify_allow_pstate_change_high(dc);
 
-	be_idx = -1;
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (stream == context->res_ctx.pipe_ctx[i].stream) {
-			be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
-			break;
-		}
-	}
-
-	ASSERT(be_idx != -1);
+	tg->funcs->lock(tg);
 
 	if (num_planes == 0) {
-		for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
-			struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 
-			if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) {
-				old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true);
-				dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx);
-			}
-		}
-		return;
+		/* OTG blank before remove all front end */
+		tg->funcs->set_blank(tg, true);
 	}
 
-	/* reset unused mpcc */
+	/* Disconnect unused mpcc */
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 		struct pipe_ctx *old_pipe_ctx =
 				&dc->current_state->res_ctx.pipe_ctx[i];
-		struct hubp *hubp = dc->res_pool->hubps[i];
-
-		if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
-			continue;
-
-		if (pipe_ctx->stream_res.tg &&
-			pipe_ctx->stream_res.tg->inst == be_idx &&
-			!pipe_ctx->top_pipe)
-			pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
-
 		/*
 		 * Powergate reused pipes that are not powergated
 		 * fairly hacky right now, using opp_id as indicator
+		 * TODO: After move dc_post to dc_update, this will
+		 * be removed.
 		 */
-
 		if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
-			if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
-				dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
+			if (old_pipe_ctx->stream_res.tg == tg &&
+				old_pipe_ctx->plane_res.hubp &&
+				old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
+				dcn10_power_down_fe(dc, pipe_ctx);
 				/*
 				 * power down fe will unlock when calling reset, need
 				 * to lock it back here. Messy, need rework.
@@ -2161,39 +2191,12 @@ static void dcn10_apply_ctx_for_surface(
 			}
 		}
 
+		if (!pipe_ctx->plane_state &&
+			old_pipe_ctx->plane_state &&
+			old_pipe_ctx->stream_res.tg == tg) {
 
-		if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state)
-				|| (!pipe_ctx->stream && old_pipe_ctx->stream)) {
-			if (old_pipe_ctx->stream_res.tg->inst != be_idx)
-				continue;
-
-			if (!old_pipe_ctx->top_pipe) {
-				ASSERT(0);
-				continue;
-			}
-
-			/* reset mpc */
-			dc->res_pool->mpc->funcs->remove(
-					dc->res_pool->mpc,
-					&(old_pipe_ctx->stream_res.opp->mpc_tree),
-					old_pipe_ctx->stream_res.opp->inst,
-					old_pipe_ctx->pipe_idx);
-			old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true;
-
-			/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
-					"[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
-					old_pipe_ctx->mpcc->inst);*/
-
-			if (hubp->funcs->hubp_disconnect)
-				hubp->funcs->hubp_disconnect(hubp);
-
-			if (dc->debug.sanity_checks)
-				dcn10_verify_allow_pstate_change_high(dc);
-
-			old_pipe_ctx->top_pipe = NULL;
-			old_pipe_ctx->bottom_pipe = NULL;
-			old_pipe_ctx->plane_state = NULL;
-			old_pipe_ctx->stream = NULL;
+			plane_atomic_disconnect(dc, old_pipe_ctx);
+			removed_pipe[i] = true;
 
 			dm_logger_write(dc->ctx->logger, LOG_DC,
 					"Reset mpcc for pipe %d\n",
@@ -2201,23 +2204,24 @@ static void dcn10_apply_ctx_for_surface(
 		}
 	}
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+	if (num_planes > 0)
+		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+
+	tg->funcs->unlock(tg);
 
-		if (pipe_ctx->stream != stream)
-			continue;
 
-		/* looking for top pipe to program */
-		if (!pipe_ctx->top_pipe) {
-			program_all_pipe_in_tree(dc, pipe_ctx, context);
-			if (pipe_ctx->stream_res.tg &&
-				pipe_ctx->stream_res.tg->inst == be_idx &&
-				(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
-				pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *old_pipe_ctx =
+				&dc->current_state->res_ctx.pipe_ctx[i];
+
+		if (removed_pipe[i]) {
+			plane_atomic_disable(dc, old_pipe_ctx);
+			if (num_planes == 0)
+				plane_atomic_power_down(dc, i);
 		}
 	}
 
+
 	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
 			"\n============== Watermark parameters ==============\n"
 			"a.urgent_ns: %d \n"
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index f3c5468854bd..19cfca91bb4e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -129,7 +129,7 @@ struct hw_sequencer_funcs {
 					struct dc_bios *dcb,
 					enum pipe_gating_control power_gating);
 
-	void (*power_down_front_end)(struct dc *dc, int fe_idx);
+	void (*power_down_front_end)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 
 	void (*power_on_front_end)(struct dc *dc,
 			struct pipe_ctx *pipe,
-- 
2.14.1

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[PATCH 24/73] drm/amd/display: fix MST link training fail division by 0

[Harry Wentland]

From: Eric Yang <Eric.Yang2@amd.com>

When link training fail in MST case, we will divide by 0
when calculating avg_time_slots_per_mtp, so we cannot
proceed.

Change-Id: Iae7aef320deb3c204f3450544c36f89b075a5c21
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 3b394a5f1c66..7b0e43c0685c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2386,9 +2386,11 @@ void core_link_enable_stream(
 
 			/* Abort stream enable *unless* the failure was due to
 			 * DP link training - some DP monitors will recover and
-			 * show the stream anyway.
+			 * show the stream anyway. But MST displays can't proceed
+			 * without link training.
 			 */
-			if (status != DC_FAIL_DP_LINK_TRAINING) {
+			if (status != DC_FAIL_DP_LINK_TRAINING ||
+					pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 				BREAK_TO_DEBUGGER();
 				return;
 			}
-- 
2.14.1

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[PATCH 25/73] drm/amd/display: Bunch of indentation cleanups in color stuff

[Harry Wentland]

Trying to align with kernel coding style and make it a bit more
readable.

Change-Id: I7d4a06e221509a1b063c539223add2b73462a599
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 170 ++++++++-------------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  10 +-
 2 files changed, 68 insertions(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index ae32af31eff1..4ff874a43f7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1260,124 +1260,87 @@ static void program_pwl(
 			REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
 }
 
-static void regamma_config_regions_and_segments(
-	struct dce_transform *xfm_dce,
-	const struct pwl_params *params)
+static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
+						const struct pwl_params *params)
 {
 	const struct gamma_curve *curve;
 
-	{
-		REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
-			REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
-			REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
-	}
-	{
-		REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
-			REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
-
-	}
-	{
-		REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
-			REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
-	}
-	{
-		REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
-			REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
-			REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope);
-	}
-
-	curve = params->arr_curve_points;
+	REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
+		  REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
+		  REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-	}
+	REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
+		REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
 
-	curve += 2;
+	REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
+		REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+	REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
+		  REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
+		  REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope);
 
-	}
+	curve = params->arr_curve_points;
 
+	REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 	curve += 2;
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
-	}
-
+	REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 	curve += 2;
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
-	}
-
+	REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 	curve += 2;
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
-	}
-
+	REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 	curve += 2;
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
-	}
-
+	REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 	curve += 2;
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-
-	}
+	REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+	curve += 2;
 
+	REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 	curve += 2;
 
-	{
-		REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
-			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-	}
+	REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 }
 
 
 
-void dce110_opp_program_regamma_pwl(
-	struct transform *xfm,
-	const struct pwl_params *params)
+void dce110_opp_program_regamma_pwl(struct transform *xfm,
+				    const struct pwl_params *params)
 {
 	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
 
@@ -1388,9 +1351,8 @@ void dce110_opp_program_regamma_pwl(
 	program_pwl(xfm_dce, params);
 }
 
-void dce110_opp_power_on_regamma_lut(
-	struct transform *xfm,
-	bool power_on)
+void dce110_opp_power_on_regamma_lut(struct transform *xfm,
+				     bool power_on)
 {
 	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
 
@@ -1406,29 +1368,25 @@ void dce110_opp_power_on_regamma_lut(
 }
 
 void dce110_opp_set_regamma_mode(struct transform *xfm,
-		enum opp_regamma mode)
+				 enum opp_regamma mode)
 {
 	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
 
 	REG_SET(REGAMMA_CONTROL, 0,
-			GRPH_REGAMMA_MODE, mode);
+		GRPH_REGAMMA_MODE, mode);
 }
 
 static const struct transform_funcs dce_transform_funcs = {
 	.transform_reset = dce_transform_reset,
-	.transform_set_scaler =
-		dce_transform_set_scaler,
-	.transform_set_gamut_remap =
-		dce_transform_set_gamut_remap,
+	.transform_set_scaler = dce_transform_set_scaler,
+	.transform_set_gamut_remap = dce_transform_set_gamut_remap,
 	.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
 	.opp_set_csc_default = dce110_opp_set_csc_default,
 	.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
 	.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
 	.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
-	.transform_set_pixel_storage_depth =
-		dce_transform_set_pixel_storage_depth,
-	.transform_get_optimal_number_of_taps =
-		dce_transform_get_optimal_number_of_taps
+	.transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth,
+	.transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps
 };
 
 /*****************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index a50e24f95ca9..81cf6c68588e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -650,13 +650,11 @@ static bool dce110_set_output_transfer_func(
 	xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 
 	if (stream->out_transfer_func &&
-		stream->out_transfer_func->type ==
-			TF_TYPE_PREDEFINED &&
-		stream->out_transfer_func->tf ==
-			TRANSFER_FUNCTION_SRGB) {
+	    stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
+	    stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
-	} else if (dce110_translate_regamma_to_hw_format(
-				stream->out_transfer_func, &xfm->regamma_params)) {
+	} else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
+							 &xfm->regamma_params)) {
 		xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 	} else {
-- 
2.14.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 26/73] drm/amd/display: Fix some more color indentations

[Harry Wentland]

Change-Id: Ib7290f11372f258308a5e8be69f964e0407c54d6
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 11 ++----
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  7 ++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 35 +++++++----------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 44 ++++++++--------------
 4 files changed, 36 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 77fb1b54694b..1c7f22146bc9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2119,6 +2119,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
 					     const struct drm_connector *connector)
 {
 	struct dc_crtc_timing *timing_out = &stream->timing;
+	struct dc_transfer_func *tf = dc_create_transfer_func();
 
 	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
 
@@ -2162,13 +2163,9 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
 
 	stream->output_color_space = get_output_color_space(timing_out);
 
-	{
-		struct dc_transfer_func *tf = dc_create_transfer_func();
-
-		tf->type = TF_TYPE_PREDEFINED;
-		tf->tf = TRANSFER_FUNCTION_SRGB;
-		stream->out_transfer_func = tf;
-	}
+	tf->type = TF_TYPE_PREDEFINED;
+	tf->tf = TRANSFER_FUNCTION_SRGB;
+	stream->out_transfer_func = tf;
 }
 
 static void fill_audio_info(struct audio_info *audio_info,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 16d645d6da25..7fe62beb2d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1337,10 +1337,9 @@ static void commit_planes_for_stream(struct dc *dc,
 				continue;
 
 			/* work around to program degamma regs for split pipe after set mode. */
-			if (srf_updates[i].in_transfer_func || (pipe_ctx->top_pipe &&
-					pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state))
-				dc->hwss.set_input_transfer_func(
-						pipe_ctx, pipe_ctx->plane_state);
+			if (srf_updates[i].in_transfer_func ||
+			    (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state))
+				dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 81cf6c68588e..8d9a6b504046 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -257,9 +257,9 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 	}
 }
 
-static bool dce110_set_input_transfer_func(
-	struct pipe_ctx *pipe_ctx,
-	const struct dc_plane_state *plane_state)
+static bool
+dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+			       const struct dc_plane_state *plane_state)
 {
 	struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 	const struct dc_transfer_func *tf = NULL;
@@ -280,25 +280,19 @@ static bool dce110_set_input_transfer_func(
 
 	if (tf == NULL) {
 		/* Default case if no input transfer function specified */
-		ipp->funcs->ipp_set_degamma(ipp,
-				IPP_DEGAMMA_MODE_HW_sRGB);
+		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 	} else if (tf->type == TF_TYPE_PREDEFINED) {
 		switch (tf->tf) {
 		case TRANSFER_FUNCTION_SRGB:
-			ipp->funcs->ipp_set_degamma(ipp,
-					IPP_DEGAMMA_MODE_HW_sRGB);
+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 			break;
 		case TRANSFER_FUNCTION_BT709:
-			ipp->funcs->ipp_set_degamma(ipp,
-					IPP_DEGAMMA_MODE_HW_xvYCC);
+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 			break;
 		case TRANSFER_FUNCTION_LINEAR:
-			ipp->funcs->ipp_set_degamma(ipp,
-					IPP_DEGAMMA_MODE_BYPASS);
+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 			break;
 		case TRANSFER_FUNCTION_PQ:
-			result = false;
-			break;
 		default:
 			result = false;
 			break;
@@ -640,9 +634,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 	return true;
 }
 
-static bool dce110_set_output_transfer_func(
-	struct pipe_ctx *pipe_ctx,
-	const struct dc_stream_state *stream)
+static bool
+dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+				const struct dc_stream_state *stream)
 {
 	struct transform *xfm = pipe_ctx->plane_res.xfm;
 
@@ -2754,8 +2748,7 @@ static void dce110_program_front_end_for_pipe(
 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	struct xfm_grph_csc_adjustment adjust;
 	struct out_csc_color_matrix tbl_entry;
-	struct pipe_ctx *cur_pipe_ctx =
-					&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
+	struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 	unsigned int i;
 
 	memset(&tbl_entry, 0, sizeof(tbl_entry));
@@ -2848,10 +2841,8 @@ static void dce110_program_front_end_for_pipe(
 
 	/* Moved programming gamma from dc to hwss */
 	if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
-		dc->hwss.set_input_transfer_func(
-				pipe_ctx, pipe_ctx->plane_state);
-		dc->hwss.set_output_transfer_func(
-				pipe_ctx, pipe_ctx->stream);
+		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
+		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
 	}
 
 	dm_logger_write(dc->ctx->logger, LOG_SURFACE,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9def1038ddce..5cac22519c37 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -874,8 +874,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c
 		pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 }
 
-static bool dcn10_set_input_transfer_func(
-	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
+static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+					  const struct dc_plane_state *plane_state)
 {
 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 	const struct dc_transfer_func *tf = NULL;
@@ -888,28 +888,22 @@ static bool dcn10_set_input_transfer_func(
 		tf = plane_state->in_transfer_func;
 
 	if (plane_state->gamma_correction && dce_use_lut(plane_state))
-		dpp_base->funcs->dpp_program_input_lut(dpp_base,
-				plane_state->gamma_correction);
+		dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 
 	if (tf == NULL)
 		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 	else if (tf->type == TF_TYPE_PREDEFINED) {
 		switch (tf->tf) {
 		case TRANSFER_FUNCTION_SRGB:
-			dpp_base->funcs->dpp_set_degamma(dpp_base,
-					IPP_DEGAMMA_MODE_HW_sRGB);
+			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 			break;
 		case TRANSFER_FUNCTION_BT709:
-			dpp_base->funcs->dpp_set_degamma(dpp_base,
-					IPP_DEGAMMA_MODE_HW_xvYCC);
+			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 			break;
 		case TRANSFER_FUNCTION_LINEAR:
-			dpp_base->funcs->dpp_set_degamma(dpp_base,
-					IPP_DEGAMMA_MODE_BYPASS);
+			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 			break;
 		case TRANSFER_FUNCTION_PQ:
-			result = false;
-			break;
 		default:
 			result = false;
 			break;
@@ -1238,9 +1232,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 	return true;
 }
 
-static bool dcn10_set_output_transfer_func(
-	struct pipe_ctx *pipe_ctx,
-	const struct dc_stream_state *stream)
+static bool
+dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+			       const struct dc_stream_state *stream)
 {
 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
 
@@ -1250,17 +1244,13 @@ static bool dcn10_set_output_transfer_func(
 	dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 
 	if (stream->out_transfer_func &&
-		stream->out_transfer_func->type ==
-			TF_TYPE_PREDEFINED &&
-		stream->out_transfer_func->tf ==
-			TRANSFER_FUNCTION_SRGB) {
+	    stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
+	    stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
 		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
-	} else if (dcn10_translate_regamma_to_hw_format(
-				stream->out_transfer_func, &dpp->regamma_params)) {
-			dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
-	} else {
+	else if (dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, &dpp->regamma_params))
+		dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
+	else
 		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
-	}
 
 	return true;
 }
@@ -2047,10 +2037,8 @@ static void program_all_pipe_in_tree(
 		}
 
 		if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
-			dc->hwss.set_input_transfer_func(
-					pipe_ctx, pipe_ctx->plane_state);
-			dc->hwss.set_output_transfer_func(
-					pipe_ctx, pipe_ctx->stream);
+			dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
+			dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
 		}
 	}
 
-- 
2.14.1

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[PATCH 27/73] drm/amd/display: use num_timing_generator instead of pipe_count

[Harry Wentland]

From: Ken Chalmers <ken.chalmers@amd.com>

The two are not necessarily the same.

Change-Id: I585542651c2a57502d4c37e0f9393ece4426e455
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5cac22519c37..99f478c52421 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -154,7 +154,7 @@ void dcn10_log_hw_state(struct dc *dc)
 	DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 			"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 
-	for (i = 0; i < pool->pipe_count; i++) {
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
 		struct timing_generator *tg = pool->timing_generators[i];
 		struct dcn_otg_state s = {0};
 
-- 
2.14.1

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[PATCH 28/73] drm/amd/display: fix regamma programming

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

When new coefficients match cached we would skip setting regamma mode
Also, when doing a stream update we would program regamma for all pipes,
even thos that are not yet powered on. This resulted in never setting
regamma since we would cache before the pipe is powered.

Change-Id: I83bde3ebffc7a1ca114012af81ee237ba3087e2c
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                  | 14 +++-----------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c          | 10 +++-------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h          |  6 ------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |  1 -
 4 files changed, 6 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7fe62beb2d7e..d969bf116645 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1343,27 +1343,19 @@ static void commit_planes_for_stream(struct dc *dc,
 		}
 	}
 
-	if (update_type > UPDATE_TYPE_FAST) {
+	if (stream && stream_update && update_type > UPDATE_TYPE_FAST)
 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx =
 					&context->res_ctx.pipe_ctx[j];
 
-			if (!pipe_ctx->stream)
+			if (pipe_ctx->stream != stream)
 				continue;
 
-			if (stream_update != NULL &&
-				stream_update->out_transfer_func != NULL) {
-				dc->hwss.set_output_transfer_func(
-						pipe_ctx, pipe_ctx->stream);
-			}
-
-			if (stream_update != NULL &&
-				stream_update->hdr_static_metadata) {
+			if (stream_update->hdr_static_metadata) {
 				resource_build_info_frame(pipe_ctx);
 				dc->hwss.update_info_frame(pipe_ctx);
 			}
 		}
-	}
 }
 
 void dc_commit_updates_for_stream(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 21eba82aba97..bbf93c94a977 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -188,9 +188,7 @@ static void dpp1_cm_set_regamma_pwl(
 	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
 {
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-	uint32_t re_mode = 0;
-	uint32_t obuf_bypass = 0; /* need for pipe split */
-	uint32_t obuf_hupscale = 0;
+	uint32_t re_mode;
 
 	switch (mode) {
 	case OPP_REGAMMA_BYPASS:
@@ -203,8 +201,9 @@ static void dpp1_cm_set_regamma_pwl(
 		re_mode = 2;
 		break;
 	case OPP_REGAMMA_USER:
+		re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
 		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
-			return;
+			break;
 
 		dpp1_cm_power_on_regamma_lut(dpp_base, true);
 		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
@@ -225,9 +224,6 @@ static void dpp1_cm_set_regamma_pwl(
 		break;
 	}
 	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
-	REG_UPDATE_2(OBUF_CONTROL,
-			OBUF_BYPASS, obuf_bypass,
-			OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
 }
 
 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 4355cc21b111..ad71fb50f8a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -71,7 +71,6 @@
 	SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
 	SRI(RECOUT_START, DSCL, id), \
 	SRI(RECOUT_SIZE, DSCL, id), \
-	SRI(OBUF_CONTROL, DSCL, id), \
 	SRI(CM_ICSC_CONTROL, CM, id), \
 	SRI(CM_ICSC_C11_C12, CM, id), \
 	SRI(CM_ICSC_C33_C34, CM, id), \
@@ -236,7 +235,6 @@
 	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
 	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
 	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
-	TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
 	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
 	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
 	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
@@ -394,7 +392,6 @@
 	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
 	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
 	TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
-	TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
 	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
 	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
 	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
@@ -558,8 +555,6 @@
 	type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
 	type CM_RGAM_LUT_MODE; \
 	type CM_CMOUT_ROUND_TRUNC_MODE; \
-	type OBUF_BYPASS; \
-	type OBUF_H_2X_UPSCALE_EN; \
 	type CM_BLNDGAM_LUT_MODE; \
 	type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
 	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
@@ -1096,7 +1091,6 @@ struct dcn_dpp_registers {
 	uint32_t CM_RGAM_RAMA_REGION_32_33;
 	uint32_t CM_RGAM_CONTROL;
 	uint32_t CM_CMOUT_CONTROL;
-	uint32_t OBUF_CONTROL;
 	uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK;
 	uint32_t CM_BLNDGAM_CONTROL;
 	uint32_t CM_BLNDGAM_RAMB_START_CNTL_B;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 99f478c52421..26452b6b38dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -820,7 +820,6 @@ static void reset_hw_ctx_wrap(
 			struct clock_source *old_clk = pipe_ctx_old->clock_source;
 
 			reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
-
 			if (old_clk)
 				old_clk->funcs->cs_power_down(old_clk);
 		}
-- 
2.14.1

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[PATCH 29/73] drm/amd/display: fix uninitialized variable warning

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ida9244b5d9c44b8fc12c18a1bfb460e18778e04f
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index bbf93c94a977..d8929b31e5ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -188,7 +188,7 @@ static void dpp1_cm_set_regamma_pwl(
 	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
 {
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-	uint32_t re_mode;
+	uint32_t re_mode = 0;
 
 	switch (mode) {
 	case OPP_REGAMMA_BYPASS:
-- 
2.14.1

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[PATCH 30/73] drm/amd/display: remove unnecessary waits in dcn10

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I4c883547441b8db282efc6ced0930fca1cc1f043
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h              |  9 ---------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   | 13 +------------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c   | 13 ++-----------
 3 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 52506155e361..3b0db253ac22 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -140,10 +140,6 @@
 	BL_REG_LIST()
 
 #define HWSEQ_DCN_REG_LIST()\
-	SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
-	SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
-	SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
-	SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
 	SRII(DCHUBP_CNTL, HUBP, 0), \
 	SRII(DCHUBP_CNTL, HUBP, 1), \
 	SRII(DCHUBP_CNTL, HUBP, 2), \
@@ -264,7 +260,6 @@ struct dce_hwseq_registers {
 	uint32_t DCHUB_AGP_BOT;
 	uint32_t DCHUB_AGP_TOP;
 
-	uint32_t OTG_GLOBAL_SYNC_STATUS[4];
 	uint32_t DCHUBP_CNTL[4];
 	uint32_t HUBP_CLK_CNTL[4];
 	uint32_t DPP_CONTROL[4];
@@ -438,8 +433,6 @@ struct dce_hwseq_registers {
 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
 	HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
-	HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
-	HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
 	HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
 	HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
 	HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
@@ -536,8 +529,6 @@ struct dce_hwseq_registers {
 	type LVTMA_PWRSEQ_TARGET_STATE_R;
 
 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
-	type VUPDATE_NO_LOCK_EVENT_CLEAR; \
-	type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
 	type HUBP_VTG_SEL; \
 	type HUBP_CLOCK_ENABLE; \
 	type DPP_CLOCK_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 26452b6b38dd..bd30d49e574a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -565,8 +565,6 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	struct mpc *mpc = dc->res_pool->mpc;
 	int opp_id, z_idx;
 	int mpcc_id = -1;
-	struct timing_generator *tg = pipe_ctx->stream_res.tg;
-	struct dce_hwseq *hws = dc->hwseq;
 
 	/* look at tree rather than mi here to know if we already reset */
 	for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
@@ -586,7 +584,7 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 		return;
 
 	mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
-					   dc->res_pool->opps[opp_id]->inst, fe_idx);
+					dc->res_pool->opps[opp_id]->inst, fe_idx);
 
 	if (hubp->funcs->hubp_disconnect)
 		hubp->funcs->hubp_disconnect(hubp);
@@ -607,10 +605,6 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 		pipe_ctx->bottom_pipe = NULL;
 	}
 	pipe_ctx->plane_state = NULL;
-
-	/* TODO: Move to tg. */
-	REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst],
-			VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
 }
 
 /* disable HW used by plane.
@@ -630,11 +624,6 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	if (opp_id == 0xf)
 		return;
 
-	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-		REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
-				VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
-				1, 100000);
-
 	mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
 	dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
 	/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 819c4edd77a7..90e94a3c11a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -393,19 +393,9 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
 				OTG_CLOCK_GATE_DIS, 0,
 				OTG_CLOCK_EN, 0);
 
-		if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-			REG_WAIT(OTG_CLOCK_CONTROL,
-					OTG_CLOCK_ON, 0,
-					1, 1000);
-
 		REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 				OPTC_INPUT_CLK_GATE_DIS, 0,
 				OPTC_INPUT_CLK_EN, 0);
-
-		if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-			REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
-					OPTC_INPUT_CLK_ON, 0,
-					1, 1000);
 	}
 }
 
@@ -568,10 +558,11 @@ static void tgn10_lock(struct timing_generator *tg)
 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 			OTG_MASTER_UPDATE_LOCK, 1);
 
+	/* Should be fast, status does not update on maximus */
 	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
 		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 				UPDATE_LOCK_STATUS, 1,
-				1, 100);
+				1, 10);
 }
 
 static void tgn10_unlock(struct timing_generator *tg)
-- 
2.14.1

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[PATCH 31/73] drm/amd/display: add warning on long reg_wait

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I237ee9baaeb91434d94abe0b2ce052f9f4f67799
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 0d84b2a1ccfd..c584252669fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -156,8 +156,13 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
 
 		field_value = get_reg_field_value_ex(reg_val, mask, shift);
 
-		if (field_value == condition_value)
+		if (field_value == condition_value) {
+			if (i * delay_between_poll_us > 1000)
+				dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n",
+						delay_between_poll_us * i / 1000,
+						func_name, line);
 			return reg_val;
+		}
 	}
 
 	dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
-- 
2.14.1

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[PATCH 32/73] drm/amd/display: Modified front end initiail in init_hw

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Optimized front end initial sequence, reset MPC module
properly.

Change-Id: Id223308988505a15a9e0fc26f908beb1e42ed4a4
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 66 ++++++++++++++++------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 11 ++++
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 11 ++++
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |  2 +
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  1 +
 5 files changed, 74 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bd30d49e574a..5d1fb1c297a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -616,10 +616,6 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 	struct mpc *mpc = dc->res_pool->mpc;
 	int opp_id = hubp->opp_id;
-	struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
-	if (tg == NULL)
-		return;
 
 	if (opp_id == 0xf)
 		return;
@@ -700,6 +696,8 @@ static void dcn10_init_hw(struct dc *dc)
 	struct abm *abm = dc->res_pool->abm;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dce_hwseq *hws = dc->hwseq;
+	struct dc_bios *dcb = dc->ctx->dc_bios;
+	struct dc_state  *context = dc->current_state;
 
 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 		REG_WRITE(REFCLK_CNTL, 0);
@@ -720,9 +718,10 @@ static void dcn10_init_hw(struct dc *dc)
 	}
 	/* end of FPGA. Below if real ASIC */
 
-	bios_golden_init(dc);
-
-	disable_vga(dc->hwseq);
+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+		bios_golden_init(dc);
+		disable_vga(dc->hwseq);
+	}
 
 	for (i = 0; i < dc->link_count; i++) {
 		/* Power up AND update implementation according to the
@@ -738,22 +737,55 @@ static void dcn10_init_hw(struct dc *dc)
 	}
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct dpp *dpp = dc->res_pool->dpps[i];
 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
 
-		dpp->funcs->dpp_reset(dpp);
-		dc->res_pool->mpc->funcs->remove(
-				dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree),
-				dc->res_pool->opps[i]->inst, i);
+		if (tg->funcs->is_tg_enabled(tg))
+			tg->funcs->lock(tg);
+	}
 
-		/* Blank controller using driver code instead of
-		 * command table.
-		 */
-		tg->funcs->set_blank(tg, true);
-		hwss_wait_for_blank_complete(tg);
+	/* Blank controller using driver code instead of
+	 * command table.
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+
+		if (tg->funcs->is_tg_enabled(tg)) {
+			tg->funcs->set_blank(tg, true);
+			hwss_wait_for_blank_complete(tg);
+		}
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		pipe_ctx->stream_res.tg = tg;
+		pipe_ctx->pipe_idx = i;
+		pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i];
+		pipe_ctx->plane_res.hubp->mpcc_id = i;
+		pipe_ctx->plane_res.hubp->opp_id =
+				dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+
+		plane_atomic_disconnect(dc, pipe_ctx);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
 
+		if (tg->funcs->is_tg_enabled(tg))
+			tg->funcs->unlock(tg);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		plane_atomic_disable(dc, pipe_ctx);
 		plane_atomic_power_down(dc, i);
 
+		pipe_ctx->stream_res.tg = NULL;
+		pipe_ctx->plane_res.hubp = NULL;
+
 		tg->funcs->tg_init(tg);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 76573e1f5b01..5028619d4fb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -335,11 +335,22 @@ void mpc10_update_blend_mode(
 			MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha);
 }
 
+static int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
+{
+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+	int opp_id = 0xF;
+
+	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
+
+	return opp_id;
+}
+
 const struct mpc_funcs dcn10_mpc_funcs = {
 		.add = mpc10_mpcc_add,
 		.remove = mpc10_mpcc_remove,
 		.wait_for_idle = mpc10_assert_idle_mpcc,
 		.update_blend_mode = mpc10_update_blend_mode,
+		.get_opp_id = mpc10_get_opp_id,
 };
 
 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 90e94a3c11a6..d248067810c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1212,6 +1212,16 @@ static void tgn10_tg_init(struct timing_generator *tg)
 	REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
 }
 
+static bool tgn10_is_tg_enabled(struct timing_generator *tg)
+{
+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+	uint32_t otg_enabled = 0;
+
+	REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
+
+	return (otg_enabled != 0);
+
+}
 static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.validate_timing = tgn10_validate_timing,
 		.program_timing = tgn10_program_timing,
@@ -1243,6 +1253,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.is_stereo_left_eye = tgn10_is_stereo_left_eye,
 		.set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer,
 		.tg_init = tgn10_tg_init,
+		.is_tg_enabled = tgn10_is_tg_enabled,
 };
 
 void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index d4188b2c0626..a786d4c3935c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -56,6 +56,8 @@ struct mpc_funcs {
 
 	void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg);
 
+	int (*get_opp_id)(struct mpc *mpc, int mpcc_id);
+
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index f77dca87cbbc..860259913d78 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -186,6 +186,7 @@ struct timing_generator_funcs {
 	void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
 
 	void (*tg_init)(struct timing_generator *tg);
+	bool (*is_tg_enabled)(struct timing_generator *tg);
 };
 
 #endif
-- 
2.14.1

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[PATCH 33/73] drm/amd/display: send display_count msg so SMU can enter S0i2

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

SMU can future lower voltages in long idle case when all display is off.

If all display output is turned off via DPMS, send display_count = 0
after all output are turned off.

otherwise send display_count msg before turning on display to make sure
SMU exit S0i2 state.  before is not neccessary as we are out of S0i2
when driver execute code, but send message before anyways for correctness.

Change-Id: Ic2a3c808eab514c42e0691e694767b0139579b78
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                    | 12 ++++++++++--
 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c |  2 ++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |  5 +++++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   |  2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h           |  4 ++++
 5 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d969bf116645..d6938bf19c8f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -383,11 +383,19 @@ void set_dpms(
 
 	if (stream->dpms_off != dpms_off) {
 		stream->dpms_off = dpms_off;
-		if (dpms_off)
+
+		if (dpms_off) {
 			core_link_disable_stream(pipe_ctx,
 					KEEP_ACQUIRED_RESOURCE);
-		else
+
+			dc->hwss.pplib_apply_display_requirements(
+					dc, dc->current_state);
+		} else {
+			dc->hwss.pplib_apply_display_requirements(
+					dc, dc->current_state);
+
 			core_link_enable_stream(dc->current_state, pipe_ctx);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index e7a694835e3e..469af0587604 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -148,5 +148,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
 
 	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
 	dc->hwss.set_bandwidth = dce100_set_bandwidth;
+	dc->hwss.pplib_apply_display_requirements =
+			dce100_pplib_apply_display_requirements;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8d9a6b504046..bf76698b30c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2593,6 +2593,10 @@ void dce110_fill_display_configs(
 
 		ASSERT(pipe_ctx != NULL);
 
+		/* only notify active stream */
+		if (stream->dpms_off)
+			continue;
+
 		num_cfgs++;
 		cfg->signal = pipe_ctx->stream->signal;
 		cfg->pipe_idx = pipe_ctx->pipe_idx;
@@ -3022,6 +3026,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
 	.ready_shared_resources = ready_shared_resources,
 	.optimize_shared_resources = optimize_shared_resources,
+	.pplib_apply_display_requirements = pplib_apply_display_requirements,
 	.edp_backlight_control = hwss_edp_backlight_control,
 	.edp_power_control = hwss_edp_power_control,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5d1fb1c297a3..73e7afb360b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2567,6 +2567,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
 	.ready_shared_resources = ready_shared_resources,
 	.optimize_shared_resources = optimize_shared_resources,
+	.pplib_apply_display_requirements =
+			dcn10_pplib_apply_display_requirements,
 	.edp_backlight_control = hwss_edp_backlight_control,
 	.edp_power_control = hwss_edp_power_control
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 19cfca91bb4e..1d8852683f1f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -183,12 +183,16 @@ struct hw_sequencer_funcs {
 
 	void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
 	void (*optimize_shared_resources)(struct dc *dc);
+	void (*pplib_apply_display_requirements)(
+			struct dc *dc,
+			struct dc_state *context);
 	void (*edp_power_control)(
 			struct dc_link *link,
 			bool enable);
 	void (*edp_backlight_control)(
 			struct dc_link *link,
 			bool enable);
+
 };
 
 void color_space_to_black_color(
-- 
2.14.1

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[PATCH 34/73] drm/amd/display: Add transfer function to dc_surface_update

[Harry Wentland]

From: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>

Change-Id: Ic42be4e0033db8d402f5688aef7c3cea6f7e0119
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 86a9c927a312..acb36594acc2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -475,6 +475,8 @@ struct dc_surface_update {
 	 */
 	/* gamma TO BE REMOVED */
 	struct dc_gamma *gamma;
+	enum color_transfer_func color_input_tf;
+	enum color_transfer_func color_output_tf;
 	struct dc_transfer_func *in_transfer_func;
 
 	struct csc_transform *input_csc_color_matrix;
-- 
2.14.1

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[PATCH 35/73] drm/amd/display: fix dcn10_hubbub_wm_read_state

[Harry Wentland]

From: Ken Chalmers <ken.chalmers@amd.com>

The ALLOW_SR registers might not always be available.

Change-Id: I715cffd3e56caee38ceed7af112182a7a51ce39a
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c    | 26 +++++++++++++++-------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 23c4573f7a34..eb8317187f30 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -42,36 +42,46 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 {
 	struct dcn_hubbub_wm_set *s;
 
+	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
+
 	s = &wm->sets[0];
 	s->wm_set = 0;
 	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
 	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
-	s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
-	s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+	}
 	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
 
 	s = &wm->sets[1];
 	s->wm_set = 1;
 	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
 	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
-	s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
-	s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
+	}
 	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
 
 	s = &wm->sets[2];
 	s->wm_set = 2;
 	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
 	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
-	s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
-	s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
+	}
 	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
 
 	s = &wm->sets[3];
 	s->wm_set = 3;
 	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
 	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
-	s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
-	s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
+	}
 	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
-- 
2.14.1

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[PATCH 36/73] drm/amd/display: Remove unused OPP functions from interface

[Harry Wentland]

From: Eric Bernstein <eric.bernstein@amd.com>

Change-Id: Ib79e69b0178219e02819a7b92cc1cb1bea9b5a68
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 8141b677fda9..cd6b0d4cd457 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -281,15 +281,6 @@ struct opp_funcs {
 			bool enable,
 			bool rightEyePolarity);
 
-	void (*opp_set_test_pattern)(
-			struct output_pixel_processor *opp,
-			bool enable);
-
-	void (*opp_dpg_blank_enable)(
-			struct output_pixel_processor *opp,
-			bool enable,
-			int width,
-			int height);
 };
 
 #endif
-- 
2.14.1

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[PATCH 37/73] drm/amd/display: dal 3.1.15

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: I58812cc60def70f03da97e90eff052c461db4dbb
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index acb36594acc2..8cdc63f273ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.14"
+#define DC_VER "3.1.15"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 38/73] drm/amd/display: Fix warnings on S3 resume

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

This is a followup to the following revert:

Rex Zhu    Revert "drm/amd/display: Match actual state during S3
           resume."

Three things needed to be addressed:

1. Potential memory leak on dc_state creation in atomic_check during
   s3 resume
2. Warnings are now seen in dmesg during S3 resume
3. Since dc_state is now created in atomic_check, what the reverted
   patch was addressing needs to be reevaluated.

This change addresses the above:

1. Since the suspend procedure calls drm_atomic_state_clear, our hook
   for releasing the dc_state is called. This frees it before
   atomic_check creates it during resume. The leak does not occur.

2. The dc_crtc/plane_state references kept by the atomic states need to
   be released before calling atomic_check, which warns if they are
   non-null. This is because atomic_check is responsible for creating
   the dc_*_states. This is a special case for S3 resume, since the
   atomic state duplication that occurs during suspend also copies a
   reference to the dc_*_states.

3. See 2. comments are also updated to reflect this.

Change-Id: I6e342bf8134f0e5dc32888a8d894c2cd20d28296
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1c7f22146bc9..bdef1ed0dfac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 	struct drm_connector *connector;
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *new_crtc_state;
+	struct dm_crtc_state *dm_new_crtc_state;
+	struct drm_plane *plane;
+	struct drm_plane_state *new_plane_state;
+	struct dm_plane_state *dm_new_plane_state;
+
 	int ret = 0;
 	int i;
 
@@ -685,6 +690,29 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
 		new_crtc_state->active_changed = true;
 
+	/*
+	 * atomic_check is expected to create the dc states. We need to release
+	 * them here, since they were duplicated as part of the suspend
+	 * procedure.
+	 */
+	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+		if (dm_new_crtc_state->stream) {
+			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
+			dc_stream_release(dm_new_crtc_state->stream);
+			dm_new_crtc_state->stream = NULL;
+		}
+	}
+
+	for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
+		dm_new_plane_state = to_dm_plane_state(new_plane_state);
+		if (dm_new_plane_state->dc_state) {
+			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
+			dc_plane_state_release(dm_new_plane_state->dc_state);
+			dm_new_plane_state->dc_state = NULL;
+		}
+	}
+
 	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
 	drm_atomic_state_put(adev->dm.cached_state);
-- 
2.14.1

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[PATCH 39/73] drm/amd/display: Miss register MST encoder cbs

[Harry Wentland]

From: "Jerry (Fangzhi) Zuo" <Jerry.Zuo@amd.com>

It is to fix: MST display failed to resume from S3

Need to properly setup MST encoder cbs. Otherwise drm_device
encoder doesn't register its own cbs, leading to NULL
encoder->funcs in drm_atomic_helper_resume().

Change-Id: I2b2d1673d30e9a1765ad5bef97c98545b658b912
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 3b05da7a90e8..f8efb98b1fa7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -245,6 +245,16 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs
 	.best_encoder = dm_mst_best_encoder,
 };
 
+static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+	kfree(encoder);
+}
+
+static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
+	.destroy = amdgpu_dm_encoder_destroy,
+};
+
 static struct amdgpu_encoder *
 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 {
@@ -268,7 +278,7 @@ dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 	drm_encoder_init(
 		dev,
 		&amdgpu_encoder->base,
-		NULL,
+		&amdgpu_dm_encoder_funcs,
 		DRM_MODE_ENCODER_DPMST,
 		NULL);
 
-- 
2.14.1

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[PATCH 40/73] drm/amd/display: Fixed not set scaler bug.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

New scaler parameter assign to dpp is after early return,
cause next flip scaler not program.

Change-Id: I4af97d37de194429116378ce7bbb820b21b7a6af
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 242a568294e2..4b5b70907202 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -650,6 +650,9 @@ void dpp1_dscl_set_scaler_manual_scale(
 
 	if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
 		return;
+
+	dpp->scl_data = *scl_data;
+
 	/* Recout */
 	dpp1_dscl_set_recout(dpp, &scl_data->recout);
 
@@ -701,5 +704,4 @@ void dpp1_dscl_set_scaler_manual_scale(
 		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
 
 	dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
-	dpp->scl_data = *scl_data;
 }
-- 
2.14.1

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[PATCH 41/73] drm/amd/display: Check aux channel before MST resume

[Harry Wentland]

From: "Jerry (Fangzhi) Zuo" <Jerry.Zuo@amd.com>

It is to fix: MST display failed to resume from S3

At the beginning of resume from S3, need to check if mgr->aux is
NULL. Fake MST encoder doesn't have real aux channel.

Change-Id: I15de6ab99da01841d62912dd98e6cc74d9100801
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bdef1ed0dfac..b88a7cca61a8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -520,7 +520,8 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		aconnector = to_amdgpu_dm_connector(connector);
-		if (aconnector->dc_link->type == dc_connection_mst_branch) {
+		if (aconnector->dc_link->type == dc_connection_mst_branch &&
+		    aconnector->mst_mgr.aux) {
 			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 					aconnector, aconnector->base.base.id);
 
-- 
2.14.1

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[PATCH 42/73] drm/amd/display: always call set output tf

[Harry Wentland]

From: Eric Yang <Eric.Yang2@amd.com>

Temporary solution to fix gamma adjustment not
working.

Change-Id: I1884bcee28f7d71cbd5f6edd56423f01c32107b1
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 73e7afb360b1..666c6c0f882a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2058,8 +2058,14 @@ static void program_all_pipe_in_tree(
 
 		if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
 			dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
-			dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
 		}
+
+		/*
+		 * TODO: This can be further optimized/cleaned up
+		 * Always call this for now since it does memcmp inside before
+		 * doing heavy calculation and programming
+		 */
+		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
 	}
 
 	if (dc->debug.sanity_checks) {
-- 
2.14.1

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[PATCH 43/73] drm/amd/display: dal 3.1.16

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: If2b7804a5074077c3581f53db337768877fffc98
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cdc63f273ca..74955f458fbb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.15"
+#define DC_VER "3.1.16"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 44/73] drm/amd/display: add flip_immediate to commit update for stream

[Harry Wentland]

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

This struct is not updated on page flip and causes vblank_mode
to not work as expected

Change-Id: I0e8684c5b67ec5670054f4bb849fa26bc60ed4b1
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d6938bf19c8f..802aebaa2e11 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1409,8 +1409,11 @@ void dc_commit_updates_for_stream(struct dc *dc,
 		/* TODO: On flip we don't build the state, so it still has the
 		 * old address. Which is why we are updating the address here
 		 */
-		if (srf_updates[i].flip_addr)
+		if (srf_updates[i].flip_addr) {
 			surface->address = srf_updates[i].flip_addr->address;
+			surface->flip_immediate = srf_updates[i].flip_addr->flip_immediate;
+
+		}
 
 		if (update_type >= UPDATE_TYPE_MED) {
 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
-- 
2.14.1

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[PATCH 45/73] drm/amd/display: Remove extra arr_points element

[Harry Wentland]

arr_points[1] and [2] were duplicated. Remove the extra
one. If we ever need more points we can add them but the
current state of affairs is confusing.

Change-Id: Ib72a1cb90940e9d52f241432c160f14393992523
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c           | 2 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 7 -------
 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 7 -------
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h            | 2 +-
 5 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 4ff874a43f7a..543b4901e987 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1277,7 +1277,7 @@ static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
 
 	REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
 		  REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
-		  REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope);
+		  REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope);
 
 	curve = params->arr_curve_points;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index bf76698b30c1..d411d0a8b9d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -539,8 +539,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 			dal_fixed31_32_from_int(segment_start));
 	arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 			dal_fixed31_32_from_int(segment_end));
-	arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-			dal_fixed31_32_from_int(segment_end));
 
 	y_r = rgb_resulted[0].red;
 	y_g = rgb_resulted[0].green;
@@ -563,10 +561,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
 
 	arr_points[1].y = y3_max;
-	arr_points[2].y = y3_max;
 
 	arr_points[1].slope = dal_fixed31_32_zero;
-	arr_points[2].slope = dal_fixed31_32_zero;
 
 	if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 		/* for PQ, we want to have a straight line from last HW X point,
@@ -578,9 +574,6 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 		arr_points[1].slope = dal_fixed31_32_div(
 			dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
 			dal_fixed31_32_sub(end_value, arr_points[1].x));
-		arr_points[2].slope = dal_fixed31_32_div(
-			dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-			dal_fixed31_32_sub(end_value, arr_points[1].x));
 	}
 
 	regamma_params->hw_points_num = hw_points;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
index e98ed3058ea2..9b65b77e8823 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
@@ -175,7 +175,7 @@ static void regamma_config_regions_and_segments(
 		value = 0;
 		set_reg_field_value(
 			value,
-			params->arr_points[2].custom_float_slope,
+			params->arr_points[1].custom_float_slope,
 			GAMMA_CORR_CNTLA_END_CNTL2,
 			GAMMA_CORR_CNTLA_EXP_REGION_END_BASE);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 666c6c0f882a..c4a6ad3f7e25 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1158,8 +1158,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 			dal_fixed31_32_from_int(segment_start));
 	arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 			dal_fixed31_32_from_int(segment_end));
-	arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-			dal_fixed31_32_from_int(segment_end));
 
 	y_r = rgb_resulted[0].red;
 	y_g = rgb_resulted[0].green;
@@ -1181,10 +1179,8 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
 
 	arr_points[1].y = y3_max;
-	arr_points[2].y = y3_max;
 
 	arr_points[1].slope = dal_fixed31_32_zero;
-	arr_points[2].slope = dal_fixed31_32_zero;
 
 	if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 		/* for PQ, we want to have a straight line from last HW X point,
@@ -1196,9 +1192,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 		arr_points[1].slope = dal_fixed31_32_div(
 			dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
 			dal_fixed31_32_sub(end_value, arr_points[1].x));
-		arr_points[2].slope = dal_fixed31_32_div(
-			dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-			dal_fixed31_32_sub(end_value, arr_points[1].x));
 	}
 
 	regamma_params->hw_points_num = hw_points;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index fa3d100de264..a650ede413d1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -73,7 +73,7 @@ struct pwl_result_data {
 
 struct pwl_params {
 	struct gamma_curve arr_curve_points[34];
-	struct curve_points arr_points[3];
+	struct curve_points arr_points[2];
 	struct pwl_result_data rgb_resulted[256 + 3];
 	uint32_t hw_points_num;
 };
-- 
2.14.1

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[PATCH 46/73] drm/amd/display: Bunch more color indentation cleanups

[Harry Wentland]

Change-Id: Ibcc4e730884cc16688873115eac44d76957978f0
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 104 ++++++++++-----------
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  54 ++++-------
 2 files changed, 69 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 543b4901e987..97414abbc69d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1183,81 +1183,75 @@ static void program_pwl(
 {
 	uint32_t value;
 	int retval;
+	uint8_t max_tries = 10;
+	uint8_t counter = 0;
+	uint32_t i = 0;
+	const struct pwl_result_data *rgb = params->rgb_resulted;
 
-	{
-		uint8_t max_tries = 10;
-		uint8_t counter = 0;
+	/* Power on LUT memory */
+	if (REG(DCFE_MEM_PWR_CTRL))
+		REG_UPDATE(DCFE_MEM_PWR_CTRL,
+			   DCP_REGAMMA_MEM_PWR_DIS, 1);
+	else
+		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
+			   REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
 
-		/* Power on LUT memory */
-		if (REG(DCFE_MEM_PWR_CTRL))
-			REG_UPDATE(DCFE_MEM_PWR_CTRL,
-				DCP_REGAMMA_MEM_PWR_DIS, 1);
-		else
-			REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
-				REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
-
-		while (counter < max_tries) {
-			if (REG(DCFE_MEM_PWR_STATUS)) {
-				value = REG_READ(DCFE_MEM_PWR_STATUS);
-				REG_GET(DCFE_MEM_PWR_STATUS,
-						DCP_REGAMMA_MEM_PWR_STATE,
-						&retval);
-
-				if (retval == 0)
-						break;
-				++counter;
-			} else {
-				value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
-				REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
-						REGAMMA_LUT_MEM_PWR_STATE,
-						&retval);
-
-				if (retval == 0)
-						break;
-				++counter;
-			}
+	while (counter < max_tries) {
+		if (REG(DCFE_MEM_PWR_STATUS)) {
+			value = REG_READ(DCFE_MEM_PWR_STATUS);
+			REG_GET(DCFE_MEM_PWR_STATUS,
+				DCP_REGAMMA_MEM_PWR_STATE,
+				&retval);
+
+			if (retval == 0)
+				break;
+			++counter;
+		} else {
+			value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
+			REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
+				REGAMMA_LUT_MEM_PWR_STATE,
+				&retval);
+
+			if (retval == 0)
+				break;
+			++counter;
 		}
+	}
 
-		if (counter == max_tries) {
-			dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
+	if (counter == max_tries) {
+		dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
 				"%s: regamma lut was not powered on "
 				"in a timely manner,"
 				" programming still proceeds\n",
 				__func__);
-		}
 	}
 
 	REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
-			REGAMMA_LUT_WRITE_EN_MASK, 7);
+		   REGAMMA_LUT_WRITE_EN_MASK, 7);
 
 	REG_WRITE(REGAMMA_LUT_INDEX, 0);
 
 	/* Program REGAMMA_LUT_DATA */
-	{
-		uint32_t i = 0;
-		const struct pwl_result_data *rgb = params->rgb_resulted;
+	while (i != params->hw_points_num) {
 
-		while (i != params->hw_points_num) {
+		REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
+		REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
+		REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
+		REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
+		REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
+		REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
 
-			REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
-			REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
-			REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
-			REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
-			REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
-			REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
-
-			++rgb;
-			++i;
-		}
+		++rgb;
+		++i;
 	}
 
 	/*  we are done with DCP LUT memory; re-enable low power mode */
 	if (REG(DCFE_MEM_PWR_CTRL))
 		REG_UPDATE(DCFE_MEM_PWR_CTRL,
-			DCP_REGAMMA_MEM_PWR_DIS, 0);
+			   DCP_REGAMMA_MEM_PWR_DIS, 0);
 	else
 		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
-			REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
+			   REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
 }
 
 static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
@@ -1358,12 +1352,12 @@ void dce110_opp_power_on_regamma_lut(struct transform *xfm,
 
 	if (REG(DCFE_MEM_PWR_CTRL))
 		REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
-			DCP_REGAMMA_MEM_PWR_DIS, power_on,
-			DCP_LUT_MEM_PWR_DIS, power_on);
+			     DCP_REGAMMA_MEM_PWR_DIS, power_on,
+			     DCP_LUT_MEM_PWR_DIS, power_on);
 	else
 		REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
-			REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
-			DCP_LUT_LIGHT_SLEEP_DIS, power_on);
+			    REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
+			    DCP_LUT_LIGHT_SLEEP_DIS, power_on);
 
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d411d0a8b9d7..59259ccd1be1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -432,8 +432,9 @@ static bool convert_to_custom_float(
 	return true;
 }
 
-static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
-		*output_tf, struct pwl_params *regamma_params)
+static bool
+dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
+				      struct pwl_params *regamma_params)
 {
 	struct curve_points *arr_points;
 	struct pwl_result_data *rgb_resulted;
@@ -448,8 +449,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 	int32_t segment_start, segment_end;
 	uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
 
-	if (output_tf == NULL || regamma_params == NULL ||
-			output_tf->type == TF_TYPE_BYPASS)
+	if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 		return false;
 
 	arr_points = regamma_params->arr_points;
@@ -528,17 +528,14 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 
 	/* last point */
 	start_index = (segment_end + 25) * 32;
-	rgb_resulted[hw_points - 1].red =
-			output_tf->tf_pts.red[start_index];
-	rgb_resulted[hw_points - 1].green =
-			output_tf->tf_pts.green[start_index];
-	rgb_resulted[hw_points - 1].blue =
-			output_tf->tf_pts.blue[start_index];
+	rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
+	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
 	arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-			dal_fixed31_32_from_int(segment_start));
+					     dal_fixed31_32_from_int(segment_start));
 	arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-			dal_fixed31_32_from_int(segment_end));
+					     dal_fixed31_32_from_int(segment_end));
 
 	y_r = rgb_resulted[0].red;
 	y_g = rgb_resulted[0].green;
@@ -547,9 +544,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
 
 	arr_points[0].y = y1_min;
-	arr_points[0].slope = dal_fixed31_32_div(
-					arr_points[0].y,
-					arr_points[0].x);
+	arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y,
+						 arr_points[0].x);
 
 	y_r = rgb_resulted[hw_points - 1].red;
 	y_g = rgb_resulted[hw_points - 1].green;
@@ -568,12 +564,11 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 		/* for PQ, we want to have a straight line from last HW X point,
 		 * and the slope to be such that we hit 1.0 at 10000 nits.
 		 */
-		const struct fixed31_32 end_value =
-				dal_fixed31_32_from_int(125);
+		const struct fixed31_32 end_value = dal_fixed31_32_from_int(125);
 
 		arr_points[1].slope = dal_fixed31_32_div(
-			dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-			dal_fixed31_32_sub(end_value, arr_points[1].x));
+				dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+				dal_fixed31_32_sub(end_value, arr_points[1].x));
 	}
 
 	regamma_params->hw_points_num = hw_points;
@@ -581,18 +576,15 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 	i = 1;
 	for (k = 0; k < 16 && i < 16; k++) {
 		if (seg_distr[k] != -1) {
-			regamma_params->arr_curve_points[k].segments_num =
-					seg_distr[k];
+			regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 			regamma_params->arr_curve_points[i].offset =
-					regamma_params->arr_curve_points[k].
-					offset + (1 << seg_distr[k]);
+					regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 		}
 		i++;
 	}
 
 	if (seg_distr[k] != -1)
-		regamma_params->arr_curve_points[k].segments_num =
-				seg_distr[k];
+		regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 
 	rgb = rgb_resulted;
 	rgb_plus_1 = rgb_resulted + 1;
@@ -607,15 +599,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
 		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
 			rgb_plus_1->blue = rgb->blue;
 
-		rgb->delta_red = dal_fixed31_32_sub(
-			rgb_plus_1->red,
-			rgb->red);
-		rgb->delta_green = dal_fixed31_32_sub(
-			rgb_plus_1->green,
-			rgb->green);
-		rgb->delta_blue = dal_fixed31_32_sub(
-			rgb_plus_1->blue,
-			rgb->blue);
+		rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
+		rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
+		rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
 
 		++rgb_plus_1;
 		++rgb;
-- 
2.14.1

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[PATCH 47/73] drm/amd/display: Remove unused register read in program_pwl

[Harry Wentland]

Change-Id: I28eb763419eec834c591c03281abd22ad446b2e7
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 97414abbc69d..330dbe9989d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1181,7 +1181,6 @@ static void program_pwl(
 	struct dce_transform *xfm_dce,
 	const struct pwl_params *params)
 {
-	uint32_t value;
 	int retval;
 	uint8_t max_tries = 10;
 	uint8_t counter = 0;
@@ -1198,7 +1197,6 @@ static void program_pwl(
 
 	while (counter < max_tries) {
 		if (REG(DCFE_MEM_PWR_STATUS)) {
-			value = REG_READ(DCFE_MEM_PWR_STATUS);
 			REG_GET(DCFE_MEM_PWR_STATUS,
 				DCP_REGAMMA_MEM_PWR_STATE,
 				&retval);
@@ -1207,7 +1205,6 @@ static void program_pwl(
 				break;
 			++counter;
 		} else {
-			value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
 			REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
 				REGAMMA_LUT_MEM_PWR_STATE,
 				&retval);
-- 
2.14.1

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[PATCH 48/73] drm/amd/display: A few more color indentation changes

[Harry Wentland]

Change-Id: Iff1b55b300bd6d874bd0dcbfe9fcf5d1ec43a7c9
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c       |  33 +++---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c |   5 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  79 +++++---------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    |  25 ++---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 115 +++++++--------------
 6 files changed, 96 insertions(+), 165 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
index d618fdd0cc82..d737e911971b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
@@ -135,36 +135,34 @@ static void dce_ipp_cursor_set_attributes(
 }
 
 
-static void dce_ipp_program_prescale(
-	struct input_pixel_processor *ipp,
-	struct ipp_prescale_params *params)
+static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
+				     struct ipp_prescale_params *params)
 {
 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
 
 	/* set to bypass mode first before change */
 	REG_UPDATE(PRESCALE_GRPH_CONTROL,
-		GRPH_PRESCALE_BYPASS,
-		1);
+		   GRPH_PRESCALE_BYPASS, 1);
 
 	REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
-		GRPH_PRESCALE_SCALE_R, params->scale,
-		GRPH_PRESCALE_BIAS_R, params->bias);
+		  GRPH_PRESCALE_SCALE_R, params->scale,
+		  GRPH_PRESCALE_BIAS_R, params->bias);
 
 	REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
-		GRPH_PRESCALE_SCALE_G, params->scale,
-		GRPH_PRESCALE_BIAS_G, params->bias);
+		  GRPH_PRESCALE_SCALE_G, params->scale,
+		  GRPH_PRESCALE_BIAS_G, params->bias);
 
 	REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
-		GRPH_PRESCALE_SCALE_B, params->scale,
-		GRPH_PRESCALE_BIAS_B, params->bias);
+		  GRPH_PRESCALE_SCALE_B, params->scale,
+		  GRPH_PRESCALE_BIAS_B, params->bias);
 
 	if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
 		REG_UPDATE(PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_BYPASS, 0);
+			   GRPH_PRESCALE_BYPASS, 0);
 
 		/* If prescale is in use, then legacy lut should be bypassed */
 		REG_UPDATE(INPUT_GAMMA_CONTROL,
-				GRPH_INPUT_GAMMA_MODE, 1);
+			   GRPH_INPUT_GAMMA_MODE, 1);
 	}
 }
 
@@ -223,13 +221,12 @@ static void dce_ipp_set_degamma(
 	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
 	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
 
-	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||
-			mode == IPP_DEGAMMA_MODE_HW_sRGB);
+	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
 
 	REG_SET_3(DEGAMMA_CONTROL, 0,
-		GRPH_DEGAMMA_MODE, degamma_type,
-		CURSOR_DEGAMMA_MODE, degamma_type,
-		CURSOR2_DEGAMMA_MODE, degamma_type);
+		  GRPH_DEGAMMA_MODE, degamma_type,
+		  CURSOR_DEGAMMA_MODE, degamma_type,
+		  CURSOR2_DEGAMMA_MODE, degamma_type);
 }
 
 static const struct ipp_funcs dce_ipp_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 330dbe9989d4..0f662e6ee9bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1177,9 +1177,8 @@ void dce110_opp_set_csc_default(
 		default_adjust->out_color_space);
 }
 
-static void program_pwl(
-	struct dce_transform *xfm_dce,
-	const struct pwl_params *params)
+static void program_pwl(struct dce_transform *xfm_dce,
+			const struct pwl_params *params)
 {
 	int retval;
 	uint8_t max_tries = 10;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 59259ccd1be1..f6f06bcaac01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -307,10 +307,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 	return result;
 }
 
-static bool convert_to_custom_float(
-		struct pwl_result_data *rgb_resulted,
-		struct curve_points *arr_points,
-		uint32_t hw_points_num)
+static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
+				    struct curve_points *arr_points,
+				    uint32_t hw_points_num)
 {
 	struct custom_float_format fmt;
 
@@ -322,26 +321,20 @@ static bool convert_to_custom_float(
 	fmt.mantissa_bits = 12;
 	fmt.sign = true;
 
-	if (!convert_to_custom_float_format(
-		arr_points[0].x,
-		&fmt,
-		&arr_points[0].custom_float_x)) {
+	if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
+					    &arr_points[0].custom_float_x)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[0].offset,
-		&fmt,
-		&arr_points[0].custom_float_offset)) {
+	if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
+					    &arr_points[0].custom_float_offset)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[0].slope,
-		&fmt,
-		&arr_points[0].custom_float_slope)) {
+	if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
+					    &arr_points[0].custom_float_slope)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
@@ -349,26 +342,20 @@ static bool convert_to_custom_float(
 	fmt.mantissa_bits = 10;
 	fmt.sign = false;
 
-	if (!convert_to_custom_float_format(
-		arr_points[1].x,
-		&fmt,
-		&arr_points[1].custom_float_x)) {
+	if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
+					    &arr_points[1].custom_float_x)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[1].y,
-		&fmt,
-		&arr_points[1].custom_float_y)) {
+	if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
+					    &arr_points[1].custom_float_y)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[2].slope,
-		&fmt,
-		&arr_points[2].custom_float_slope)) {
+	if (!convert_to_custom_float_format(arr_points[2].slope, &fmt,
+					    &arr_points[2].custom_float_slope)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
@@ -377,50 +364,38 @@ static bool convert_to_custom_float(
 	fmt.sign = true;
 
 	while (i != hw_points_num) {
-		if (!convert_to_custom_float_format(
-			rgb->red,
-			&fmt,
-			&rgb->red_reg)) {
+		if (!convert_to_custom_float_format(rgb->red, &fmt,
+						    &rgb->red_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->green,
-			&fmt,
-			&rgb->green_reg)) {
+		if (!convert_to_custom_float_format(rgb->green, &fmt,
+						    &rgb->green_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->blue,
-			&fmt,
-			&rgb->blue_reg)) {
+		if (!convert_to_custom_float_format(rgb->blue, &fmt,
+						    &rgb->blue_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->delta_red,
-			&fmt,
-			&rgb->delta_red_reg)) {
+		if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
+						    &rgb->delta_red_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->delta_green,
-			&fmt,
-			&rgb->delta_green_reg)) {
+		if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
+						    &rgb->delta_green_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->delta_blue,
-			&fmt,
-			&rgb->delta_blue_reg)) {
+		if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
+						    &rgb->delta_blue_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index d8929b31e5ba..8df3945370cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -213,8 +213,8 @@ static void dpp1_cm_set_regamma_pwl(
 		else
 			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
 
-		dpp1_cm_program_regamma_lut(
-				dpp_base, params->rgb_resulted, params->hw_points_num);
+		dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
+					    params->hw_points_num);
 		dpp->pwl_data = *params;
 
 		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index bb430c0ec1b6..b4892f43cd77 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -365,34 +365,31 @@ void dpp1_cm_set_output_csc_adjustment(
 	dpp1_cm_program_color_matrix(dpp, tbl_entry);
 }
 
-void dpp1_cm_power_on_regamma_lut(
-	struct dpp *dpp_base,
-	bool power_on)
+void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
+				  bool power_on)
 {
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
 	REG_SET(CM_MEM_PWR_CTRL, 0,
-			RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+		RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
 
 }
 
-void dpp1_cm_program_regamma_lut(
-		struct dpp *dpp_base,
-		const struct pwl_result_data *rgb,
-		uint32_t num)
+void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
+				 const struct pwl_result_data *rgb,
+				 uint32_t num)
 {
 	uint32_t i;
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
 	for (i = 0 ; i < num; i++) {
 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
 
-		REG_SET(CM_RGAM_LUT_DATA, 0,
-				CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
-		REG_SET(CM_RGAM_LUT_DATA, 0,
-				CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
-		REG_SET(CM_RGAM_LUT_DATA, 0,
-				CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
 
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c4a6ad3f7e25..cb73d25aca4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -953,26 +953,20 @@ static bool convert_to_custom_float(
 	fmt.mantissa_bits = 12;
 	fmt.sign = false;
 
-	if (!convert_to_custom_float_format(
-		arr_points[0].x,
-		&fmt,
-		&arr_points[0].custom_float_x)) {
+	if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
+					    &arr_points[0].custom_float_x)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[0].offset,
-		&fmt,
-		&arr_points[0].custom_float_offset)) {
+	if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
+					    &arr_points[0].custom_float_offset)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[0].slope,
-		&fmt,
-		&arr_points[0].custom_float_slope)) {
+	if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
+					    &arr_points[0].custom_float_slope)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
@@ -980,26 +974,20 @@ static bool convert_to_custom_float(
 	fmt.mantissa_bits = 10;
 	fmt.sign = false;
 
-	if (!convert_to_custom_float_format(
-		arr_points[1].x,
-		&fmt,
-		&arr_points[1].custom_float_x)) {
+	if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
+					    &arr_points[1].custom_float_x)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[1].y,
-		&fmt,
-		&arr_points[1].custom_float_y)) {
+	if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
+					    &arr_points[1].custom_float_y)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
 
-	if (!convert_to_custom_float_format(
-		arr_points[1].slope,
-		&fmt,
-		&arr_points[1].custom_float_slope)) {
+	if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
+					    &arr_points[1].custom_float_slope)) {
 		BREAK_TO_DEBUGGER();
 		return false;
 	}
@@ -1008,50 +996,38 @@ static bool convert_to_custom_float(
 	fmt.sign = true;
 
 	while (i != hw_points_num) {
-		if (!convert_to_custom_float_format(
-			rgb->red,
-			&fmt,
-			&rgb->red_reg)) {
+		if (!convert_to_custom_float_format(rgb->red, &fmt,
+						    &rgb->red_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->green,
-			&fmt,
-			&rgb->green_reg)) {
+		if (!convert_to_custom_float_format(rgb->green, &fmt,
+						    &rgb->green_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->blue,
-			&fmt,
-			&rgb->blue_reg)) {
+		if (!convert_to_custom_float_format(rgb->blue, &fmt,
+						    &rgb->blue_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->delta_red,
-			&fmt,
-			&rgb->delta_red_reg)) {
+		if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
+						    &rgb->delta_red_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->delta_green,
-			&fmt,
-			&rgb->delta_green_reg)) {
+		if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
+						    &rgb->delta_green_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(
-			rgb->delta_blue,
-			&fmt,
-			&rgb->delta_blue_reg)) {
+		if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
+						    &rgb->delta_blue_reg)) {
 			BREAK_TO_DEBUGGER();
 			return false;
 		}
@@ -1066,8 +1042,9 @@ static bool convert_to_custom_float(
 #define MAX_LOW_POINT      25
 #define NUMBER_SEGMENTS    32
 
-static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
-		*output_tf, struct pwl_params *regamma_params)
+static bool
+dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
+				     struct pwl_params *regamma_params)
 {
 	struct curve_points *arr_points;
 	struct pwl_result_data *rgb_resulted;
@@ -1083,8 +1060,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 	int32_t i;
 	uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
 
-	if (output_tf == NULL || regamma_params == NULL ||
-			output_tf->type == TF_TYPE_BYPASS)
+	if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 		return false;
 
 	arr_points = regamma_params->arr_points;
@@ -1147,17 +1123,14 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 
 	/* last point */
 	start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
-	rgb_resulted[hw_points - 1].red =
-			output_tf->tf_pts.red[start_index];
-	rgb_resulted[hw_points - 1].green =
-			output_tf->tf_pts.green[start_index];
-	rgb_resulted[hw_points - 1].blue =
-			output_tf->tf_pts.blue[start_index];
+	rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
+	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
 	arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-			dal_fixed31_32_from_int(segment_start));
+					     dal_fixed31_32_from_int(segment_start));
 	arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-			dal_fixed31_32_from_int(segment_end));
+					     dal_fixed31_32_from_int(segment_end));
 
 	y_r = rgb_resulted[0].red;
 	y_g = rgb_resulted[0].green;
@@ -1166,9 +1139,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
 
 	arr_points[0].y = y1_min;
-	arr_points[0].slope = dal_fixed31_32_div(
-					arr_points[0].y,
-					arr_points[0].x);
+	arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x);
 	y_r = rgb_resulted[hw_points - 1].red;
 	y_g = rgb_resulted[hw_points - 1].green;
 	y_b = rgb_resulted[hw_points - 1].blue;
@@ -1202,15 +1173,13 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 			regamma_params->arr_curve_points[k].segments_num =
 					seg_distr[k];
 			regamma_params->arr_curve_points[i].offset =
-					regamma_params->arr_curve_points[k].
-					offset + (1 << seg_distr[k]);
+					regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 		}
 		i++;
 	}
 
 	if (seg_distr[k] != -1)
-		regamma_params->arr_curve_points[k].segments_num =
-				seg_distr[k];
+		regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 
 	rgb = rgb_resulted;
 	rgb_plus_1 = rgb_resulted + 1;
@@ -1225,15 +1194,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
 			rgb_plus_1->blue = rgb->blue;
 
-		rgb->delta_red = dal_fixed31_32_sub(
-			rgb_plus_1->red,
-			rgb->red);
-		rgb->delta_green = dal_fixed31_32_sub(
-			rgb_plus_1->green,
-			rgb->green);
-		rgb->delta_blue = dal_fixed31_32_sub(
-			rgb_plus_1->blue,
-			rgb->blue);
+		rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
+		rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
+		rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
 
 		++rgb_plus_1;
 		++rgb;
-- 
2.14.1

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[PATCH 49/73] drm/amd/display: combine output signal and signal

[Harry Wentland]

From: Eric Yang <Eric.Yang2@amd.com>

output signal used to be a public member to be used by DM to override
the stream signal. Now since there is no longer separation between
public and private part of stream, they are combined. The overriding
was not working properly as well, which is addressed by this change

Change-Id: Icd7487eb3e29078ee940a85bc916f7b6f9685a8e
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++++++---------
 drivers/gpu/drm/amd/display/dc/dc.h             |  2 --
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index de04b95e103a..f561232e8867 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -36,16 +36,13 @@
 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
 static void update_stream_signal(struct dc_stream_state *stream)
 {
-	if (stream->output_signal == SIGNAL_TYPE_NONE) {
-		struct dc_sink *dc_sink = stream->sink;
 
-		if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
-			stream->signal = stream->sink->link->connector_signal;
-		else
-			stream->signal = dc_sink->sink_signal;
-	} else {
-		stream->signal = stream->output_signal;
-	}
+	struct dc_sink *dc_sink = stream->sink;
+
+	if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
+		stream->signal = stream->sink->link->connector_signal;
+	else
+		stream->signal = dc_sink->sink_signal;
 
 	if (dc_is_dvi_signal(stream->signal)) {
 		if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 74955f458fbb..f2647b40f3cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -579,8 +579,6 @@ struct dc_stream_state {
 	struct colorspace_transform gamut_remap_matrix;
 	struct csc_transform csc_color_matrix;
 
-	enum signal_type output_signal;
-
 	enum dc_color_space output_color_space;
 	enum dc_dither_option dither_option;
 
-- 
2.14.1

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[PATCH 50/73] drm/amd/display: Report pitch_alignment for DCN

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

Change-Id: I2825b787ae02b7317bf1602eb2d45aeca8ba1041
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h                   | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f2647b40f3cb..459a1c55b5cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -58,6 +58,7 @@ struct dc_caps {
 	uint32_t i2c_speed_in_khz;
 	unsigned int max_cursor_size;
 	unsigned int max_video_width;
+	int pitch_alignment;
 	bool dcc_const_color;
 	bool dynamic_audio;
 	bool is_apu;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 2e6122c4670a..c350fe2fec20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1267,7 +1267,7 @@ static bool construct(
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
 	dc->caps.max_cursor_size = 256;
-
+	dc->caps.pitch_alignment = 64; /* Alignment is 64 on DCN1 */
 	dc->caps.max_slave_planes = 1;
 	dc->caps.is_apu = true;
 
-- 
2.14.1

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[PATCH 51/73] drm/amd/display: Loosen plane_info and scaling_info checks

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

Make it so that differing dcc and plane size fields don't necessarily
result in a full update, along with upscaling modes. This allows us to
save some unnecessary full updates.

Change-Id: I5ea98fa690e8ed136d39e2de0af8cbe10806c4b4
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 802aebaa2e11..de7332cffaa2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1130,9 +1130,7 @@ static enum surface_update_type get_plane_info_update_type(
 	/* Full update parameters */
 	temp_plane_info.color_space = u->surface->color_space;
 	temp_plane_info.input_tf = u->surface->input_tf;
-	temp_plane_info.dcc = u->surface->dcc;
 	temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
-	temp_plane_info.plane_size = u->surface->plane_size;
 	temp_plane_info.rotation = u->surface->rotation;
 	temp_plane_info.stereo_format = u->surface->stereo_format;
 
@@ -1175,14 +1173,23 @@ static enum surface_update_type  get_scaling_info_update_type(
 	if (!u->scaling_info)
 		return UPDATE_TYPE_FAST;
 
-	if (u->scaling_info->src_rect.width != u->surface->src_rect.width
-			|| u->scaling_info->src_rect.height != u->surface->src_rect.height
-			|| u->scaling_info->clip_rect.width != u->surface->clip_rect.width
+	if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
 			|| u->scaling_info->clip_rect.height != u->surface->clip_rect.height
 			|| u->scaling_info->dst_rect.width != u->surface->dst_rect.width
 			|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
 		return UPDATE_TYPE_FULL;
 
+	if (u->scaling_info->src_rect.width != u->surface->src_rect.width
+		|| u->scaling_info->src_rect.height != u->surface->src_rect.height) {
+
+		if (u->scaling_info->src_rect.width > u->surface->src_rect.width
+				&& u->scaling_info->src_rect.height > u->surface->src_rect.height)
+			return UPDATE_TYPE_FULL;
+
+		/* Upscaling does not require a full update */
+		return UPDATE_TYPE_MED;
+	}
+
 	if (u->scaling_info->src_rect.x != u->surface->src_rect.x
 			|| u->scaling_info->src_rect.y != u->surface->src_rect.y
 			|| u->scaling_info->clip_rect.x != u->surface->clip_rect.x
-- 
2.14.1

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[PATCH 52/73] drm/amd/display: remove dcn10 wait on tg unlock

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ifde23126bc8528f42ad73fa19e6bf48d17a2233b
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index d248067810c8..73ff78f9cae1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -571,11 +571,6 @@ static void tgn10_unlock(struct timing_generator *tg)
 
 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 			OTG_MASTER_UPDATE_LOCK, 0);
-
-	/* why are we waiting here? */
-	REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL,
-			OTG_UPDATE_PENDING, 0,
-			1, 100000);
 }
 
 static void tgn10_get_position(struct timing_generator *tg,
-- 
2.14.1

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[PATCH 53/73] drm/amd/display: Apply work around for stutter.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Power on one plane after disable all the planes, for
a hw bug work around to resolve stutter efficiency issue.

Change-Id: Ifc696c800f9402afb9615a974657c8b06a94b334
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           |   2 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |  10 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 153 +++++++++------------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h       |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  10 +-
 6 files changed, 84 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index de7332cffaa2..615541d8eb21 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -935,7 +935,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 		if (context->res_ctx.pipe_ctx[i].stream == NULL ||
 		    context->res_ctx.pipe_ctx[i].plane_state == NULL) {
 			context->res_ctx.pipe_ctx[i].pipe_idx = i;
-			dc->hwss.power_down_front_end(dc, &context->res_ctx.pipe_ctx[i]);
+			dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
 		}
 
 	/* 3rd param should be true, temp w/a for RV*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index f6f06bcaac01..28c977f49773 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1413,7 +1413,7 @@ static void disable_vga_and_power_gate_all_controllers(
 				true);
 
 		dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
-		dc->hwss.power_down_front_end(dc,
+		dc->hwss.disable_plane(dc,
 			&dc->current_state->res_ctx.pipe_ctx[i]);
 	}
 }
@@ -1836,7 +1836,7 @@ static void dce110_reset_hw_ctx_wrap(
 			if (old_clk)
 				old_clk->funcs->cs_power_down(old_clk);
 
-			dc->hwss.power_down_front_end(dc, pipe_ctx_old);
+			dc->hwss.disable_plane(dc, pipe_ctx_old);
 
 			pipe_ctx_old->stream = NULL;
 		}
@@ -2061,8 +2061,8 @@ enum dc_status dce110_apply_ctx_to_hw(
 				context,
 				dc);
 
-		if (dc->hwss.power_on_front_end)
-			dc->hwss.power_on_front_end(dc, pipe_ctx, context);
+		if (dc->hwss.enable_plane)
+			dc->hwss.enable_plane(dc, pipe_ctx, context);
 
 		if (DC_OK != status)
 			return status;
@@ -2967,7 +2967,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.unblank_stream = dce110_unblank_stream,
 	.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
 	.enable_display_power_gating = dce110_enable_display_power_gating,
-	.power_down_front_end = dce110_power_down_fe,
+	.disable_plane = dce110_power_down_fe,
 	.pipe_control_lock = dce_pipe_control_lock,
 	.set_bandwidth = dce110_set_bandwidth,
 	.set_drr = set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cb73d25aca4c..7d1821fb3607 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -363,11 +363,8 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 {
 	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = dc->res_pool->hubps[0];
-	int pwr_status = 0;
 
-	REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status);
-	/* Don't need to blank if hubp is power gated*/
-	if (pwr_status == 2)
+	if (!hws->wa_state.DEGVIDCN10_253_applied)
 		return;
 
 	hubp->funcs->set_blank(hubp, true);
@@ -378,16 +375,29 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 	hubp_pg_control(hws, 0, false);
 	REG_SET(DC_IP_REQUEST_CNTL, 0,
 			IP_REQUEST_EN, 0);
+
+	hws->wa_state.DEGVIDCN10_253_applied = false;
 }
 
 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 {
 	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = dc->res_pool->hubps[0];
+	int i;
 
 	if (dc->debug.disable_stutter)
 		return;
 
+	if (!hws->wa.DEGVIDCN10_253)
+		return;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!dc->res_pool->hubps[i]->power_gated)
+			return;
+	}
+
+	/* all pipe power gated, apply work around to enable stutter. */
+
 	REG_SET(DC_IP_REQUEST_CNTL, 0,
 			IP_REQUEST_EN, 1);
 
@@ -396,6 +406,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 			IP_REQUEST_EN, 0);
 
 	hubp->funcs->set_hubp_blank_en(hubp, false);
+	hws->wa_state.DEGVIDCN10_253_applied = true;
 }
 
 static void bios_golden_init(struct dc *dc)
@@ -592,61 +603,14 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	if (dc->debug.sanity_checks)
 		dcn10_verify_allow_pstate_change_high(dc);
 
-	if (pipe_ctx->top_pipe) {
-		pipe_ctx->top_pipe->bottom_pipe = NULL;
-		pipe_ctx->top_pipe = NULL;
-		pipe_ctx->stream = NULL;
-		memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
-		memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
-	}
-
-	if (pipe_ctx->bottom_pipe) {
-		pipe_ctx->bottom_pipe->top_pipe = NULL;
-		pipe_ctx->bottom_pipe = NULL;
-	}
+	pipe_ctx->stream = NULL;
+	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
+	memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
+	pipe_ctx->top_pipe = NULL;
+	pipe_ctx->bottom_pipe = NULL;
 	pipe_ctx->plane_state = NULL;
 }
 
-/* disable HW used by plane.
- * note:  cannot disable until disconnect is complete */
-static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
-{
-	int fe_idx = pipe_ctx->pipe_idx;
-	struct dce_hwseq *hws = dc->hwseq;
-	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
-	struct mpc *mpc = dc->res_pool->mpc;
-	int opp_id = hubp->opp_id;
-
-	if (opp_id == 0xf)
-		return;
-
-	mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
-	dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
-	/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
-			"[debug_mpo: atomic disable finished on mpcc %d]\n",
-			fe_idx);*/
-
-	hubp->funcs->set_blank(hubp, true);
-
-	if (dc->debug.sanity_checks)
-		dcn10_verify_allow_pstate_change_high(dc);
-
-	REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
-			HUBP_CLOCK_ENABLE, 0);
-	REG_UPDATE(DPP_CONTROL[fe_idx],
-			DPP_CLOCK_ENABLE, 0);
-
-	if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
-		REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
-				OPP_PIPE_CLOCK_EN, 0);
-
-	if (dc->debug.sanity_checks)
-		dcn10_verify_allow_pstate_change_high(dc);
-}
-
-/* kill power to plane hw
- * note: cannot power down until plane is disable
- */
 static void plane_atomic_power_down(struct dc *dc, int fe_idx)
 {
 	struct dce_hwseq *hws = dc->hwseq;
@@ -665,29 +629,51 @@ static void plane_atomic_power_down(struct dc *dc, int fe_idx)
 	}
 }
 
-static void dcn10_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
+/* disable HW used by plane.
+ * note:  cannot disable until disconnect is complete
+ */
+static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
 	int fe_idx = pipe_ctx->pipe_idx;
-	struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
-	if (tg != NULL) {
-		tg->funcs->lock(tg);
+	struct dce_hwseq *hws = dc->hwseq;
+	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
+	struct mpc *mpc = dc->res_pool->mpc;
+	int opp_id = hubp->opp_id;
+	struct output_pixel_processor *opp;
 
-		plane_atomic_disconnect(dc, pipe_ctx);
+	if (opp_id != 0xf) {
+		mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
+		opp = dc->res_pool->opps[hubp->opp_id];
+		opp->mpcc_disconnect_pending[hubp->mpcc_id] = false;
+		hubp->funcs->set_blank(hubp, true);
+	}
 
-		tg->funcs->unlock(tg);
+	REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
+			HUBP_CLOCK_ENABLE, 0);
+	REG_UPDATE(DPP_CONTROL[fe_idx],
+			DPP_CLOCK_ENABLE, 0);
 
-		if (dc->debug.sanity_checks)
-			dcn10_verify_allow_pstate_change_high(dc);
+	if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
+		REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
+				OPP_PIPE_CLOCK_EN, 0);
 
-		plane_atomic_disable(dc, pipe_ctx);
-	}
+	hubp->power_gated = true;
 
 	plane_atomic_power_down(dc, fe_idx);
+}
+
+static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+	if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
+		return;
+
+	plane_atomic_disable(dc, pipe_ctx);
+
+	apply_DEGVIDCN10_253_wa(dc);
 
 	dm_logger_write(dc->ctx->logger, LOG_DC,
-					"Reset front end %d\n",
-					fe_idx);
+					"Power down front end %d\n",
+					pipe_ctx->pipe_idx);
 }
 
 static void dcn10_init_hw(struct dc *dc)
@@ -780,8 +766,7 @@ static void dcn10_init_hw(struct dc *dc)
 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
-		plane_atomic_disable(dc, pipe_ctx);
-		plane_atomic_power_down(dc, i);
+		dcn10_disable_plane(dc, pipe_ctx);
 
 		pipe_ctx->stream_res.tg = NULL;
 		pipe_ctx->plane_res.hubp = NULL;
@@ -1468,7 +1453,7 @@ static void print_rq_dlg_ttu(
 			);
 }
 
-static void dcn10_power_on_fe(
+static void dcn10_enable_plane(
 	struct dc *dc,
 	struct pipe_ctx *pipe_ctx,
 	struct dc_state *context)
@@ -1480,6 +1465,8 @@ static void dcn10_power_on_fe(
 		dcn10_verify_allow_pstate_change_high(dc);
 	}
 
+	undo_DEGVIDCN10_253_wa(dc);
+
 	power_on_plane(dc->hwseq,
 		pipe_ctx->pipe_idx);
 
@@ -1946,6 +1933,8 @@ static void update_dchubp_dpp(
 		&plane_state->dcc,
 		plane_state->horizontal_mirror);
 
+	hubp->power_gated = false;
+
 	dc->hwss.update_plane_addr(dc, pipe_ctx);
 
 	if (is_pipe_tree_visible(pipe_ctx))
@@ -1988,7 +1977,7 @@ static void program_all_pipe_in_tree(
 		struct pipe_ctx *cur_pipe_ctx =
 				&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 
-		dcn10_power_on_fe(dc, pipe_ctx, context);
+		dcn10_enable_plane(dc, pipe_ctx, context);
 
 		/* temporary dcn1 wa:
 		 *   watermark update requires toggle after a/b/c/d sets are programmed
@@ -2063,7 +2052,6 @@ static void dcn10_pplib_apply_display_requirements(
 static void optimize_shared_resources(struct dc *dc)
 {
 	if (dc->current_state->stream_count == 0) {
-		apply_DEGVIDCN10_253_wa(dc);
 		/* S0i2 message */
 		dcn10_pplib_apply_display_requirements(dc, dc->current_state);
 	}
@@ -2074,10 +2062,6 @@ static void optimize_shared_resources(struct dc *dc)
 
 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
 {
-	if (dc->current_state->stream_count == 0 &&
-			!dc->debug.disable_stutter)
-		undo_DEGVIDCN10_253_wa(dc);
-
 	/* S0i2 message */
 	if (dc->current_state->stream_count == 0 &&
 			context->stream_count != 0)
@@ -2152,7 +2136,7 @@ static void dcn10_apply_ctx_for_surface(
 			if (old_pipe_ctx->stream_res.tg == tg &&
 				old_pipe_ctx->plane_res.hubp &&
 				old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
-				dcn10_power_down_fe(dc, pipe_ctx);
+				dcn10_disable_plane(dc, pipe_ctx);
 				/*
 				 * power down fe will unlock when calling reset, need
 				 * to lock it back here. Messy, need rework.
@@ -2184,14 +2168,10 @@ static void dcn10_apply_ctx_for_surface(
 		struct pipe_ctx *old_pipe_ctx =
 				&dc->current_state->res_ctx.pipe_ctx[i];
 
-		if (removed_pipe[i]) {
-			plane_atomic_disable(dc, old_pipe_ctx);
-			if (num_planes == 0)
-				plane_atomic_power_down(dc, i);
-		}
+		if (removed_pipe[i] && num_planes == 0)
+			dcn10_disable_plane(dc, old_pipe_ctx);
 	}
 
-
 	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
 			"\n============== Watermark parameters ==============\n"
 			"a.urgent_ns: %d \n"
@@ -2514,8 +2494,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.disable_stream = dce110_disable_stream,
 	.unblank_stream = dce110_unblank_stream,
 	.enable_display_power_gating = dcn10_dummy_display_power_gating,
-	.power_down_front_end = dcn10_power_down_fe,
-	.power_on_front_end = dcn10_power_on_fe,
+	.disable_plane = dcn10_disable_plane,
 	.pipe_control_lock = dcn10_pipe_control_lock,
 	.set_bandwidth = dcn10_set_bandwidth,
 	.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index c350fe2fec20..7eb11c61c44e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -677,6 +677,7 @@ static struct dce_hwseq *dcn10_hwseq_create(
 		hws->regs = &hwseq_reg;
 		hws->shifts = &hwseq_shift;
 		hws->masks = &hwseq_mask;
+		hws->wa.DEGVIDCN10_253 = true;
 	}
 	return hws;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 3286585bd6cd..49b12f602e79 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -34,9 +34,12 @@ struct hubp {
 	struct dc_plane_address request_address;
 	struct dc_plane_address current_address;
 	int inst;
+
+	/* run time states */
 	int opp_id;
 	int mpcc_id;
 	struct dc_cursor_attributes curs_attr;
+	bool power_gated;
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 1d8852683f1f..5dc4ecf618ff 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -39,6 +39,11 @@ enum pipe_gating_control {
 
 struct dce_hwseq_wa {
 	bool blnd_crtc_trigger;
+	bool DEGVIDCN10_253;
+};
+
+struct hwseq_wa_state {
+	bool DEGVIDCN10_253_applied;
 };
 
 struct dce_hwseq {
@@ -47,6 +52,7 @@ struct dce_hwseq {
 	const struct dce_hwseq_shift *shifts;
 	const struct dce_hwseq_mask *masks;
 	struct dce_hwseq_wa wa;
+	struct hwseq_wa_state wa_state;
 };
 
 struct pipe_ctx;
@@ -129,9 +135,9 @@ struct hw_sequencer_funcs {
 					struct dc_bios *dcb,
 					enum pipe_gating_control power_gating);
 
-	void (*power_down_front_end)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 
-	void (*power_on_front_end)(struct dc *dc,
+	void (*enable_plane)(struct dc *dc,
 			struct pipe_ctx *pipe,
 			struct dc_state *context);
 
-- 
2.14.1

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[PATCH 54/73] drm/amd/display: Fix unbalanced locking in surface apply

[Harry Wentland]

From: Roman Li <Roman.Li@amd.com>

also simplifying syntax and removing unused variable in
dce110_apply_ctx_for_surface()

Change-Id: I15c39de23afa05635d537ab2c5f8385342f75a64
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 28c977f49773..ee3b9441e460 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2847,22 +2847,19 @@ static void dce110_apply_ctx_for_surface(
 		int num_planes,
 		struct dc_state *context)
 {
-	int i, be_idx;
+	int i;
 
 	if (num_planes == 0)
 		return;
 
-	be_idx = -1;
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 
-		if (stream == context->res_ctx.pipe_ctx[i].stream) {
-			be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst;
+		if (stream == pipe_ctx->stream) {
 			if (!pipe_ctx->top_pipe &&
 				(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
-			break;
 		}
 	}
 
-- 
2.14.1

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[PATCH 55/73] drm/amd/display: Optimize programming front end

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

In case of update type is medium, optimize squence,
reduce programing time.

Change-Id: Ib1793408897b0c4d4a64434c239c3703d43e83d9
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 22 +++++-------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 42 ++++++++++------------
 2 files changed, 27 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 615541d8eb21..56df1304e49c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1314,7 +1314,7 @@ static void commit_planes_for_stream(struct dc *dc,
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 
-		if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state)
+		if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state)
 			continue;
 
 		if (!pipe_ctx->top_pipe &&
@@ -1335,26 +1335,20 @@ static void commit_planes_for_stream(struct dc *dc,
 	for (i = 0; i < surface_count; i++) {
 		struct dc_plane_state *plane_state = srf_updates[i].surface;
 
-		if (update_type == UPDATE_TYPE_MED)
-			dc->hwss.apply_ctx_for_surface(
-					dc, stream, surface_count, context);
-
 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 
-			if (pipe_ctx->plane_state != plane_state)
+			if (pipe_ctx->stream != stream)
 				continue;
 
-			if (srf_updates[i].flip_addr)
-				dc->hwss.update_plane_addr(dc, pipe_ctx);
-
-			if (update_type == UPDATE_TYPE_FAST)
+			if (pipe_ctx->plane_state != plane_state)
 				continue;
 
-			/* work around to program degamma regs for split pipe after set mode. */
-			if (srf_updates[i].in_transfer_func ||
-			    (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state))
-				dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
+			if (update_type == UPDATE_TYPE_FAST) {
+				if (srf_updates[i].flip_addr)
+					dc->hwss.update_plane_addr(dc, pipe_ctx);
+				continue;
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7d1821fb3607..ffce33fb5540 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -555,7 +555,7 @@ static void reset_back_end_for_pipe(
 					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 }
 
-void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 {
 	static bool should_log_hw_state; /* prevent hw state log by default */
 
@@ -1331,7 +1331,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
 	DC_SYNC_INFO("Multi-display sync is complete\n");
 }
 
-static void print_rq_dlg_ttu(
+/*static void print_rq_dlg_ttu(
 		struct dc *core_dc,
 		struct pipe_ctx *pipe_ctx)
 {
@@ -1452,13 +1452,13 @@ static void print_rq_dlg_ttu(
 			pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
 			);
 }
+*/
 
 static void dcn10_enable_plane(
 	struct dc *dc,
 	struct pipe_ctx *pipe_ctx,
 	struct dc_state *context)
 {
-	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	struct dce_hwseq *hws = dc->hwseq;
 
 	if (dc->debug.sanity_checks) {
@@ -1479,6 +1479,7 @@ static void dcn10_enable_plane(
 			OPP_PIPE_CLOCK_EN, 1);
 	/*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
 
+/* TODO: enable/disable in dm as per update type.
 	if (plane_state) {
 		dm_logger_write(dc->ctx->logger, LOG_DC,
 				"Pipe:%d 0x%x: addr hi:0x%x, "
@@ -1514,6 +1515,7 @@ static void dcn10_enable_plane(
 				pipe_ctx->plane_res.scl_data.recout.y);
 		print_rq_dlg_ttu(dc, pipe_ctx);
 	}
+*/
 
 	if (dc->debug.sanity_checks) {
 		dcn10_verify_allow_pstate_change_high(dc);
@@ -1947,16 +1949,8 @@ static void program_all_pipe_in_tree(
 		struct pipe_ctx *pipe_ctx,
 		struct dc_state *context)
 {
-	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
-
 	if (pipe_ctx->top_pipe == NULL) {
 
-		/* lock otg_master_update to process all pipes associated with
-		 * this OTG. this is done only one time.
-		 */
-		/* watermark is for all pipes */
-		hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz);
-
 		if (dc->debug.sanity_checks) {
 			/* pstate stuck check after watermark update */
 			dcn10_verify_allow_pstate_change_high(dc);
@@ -1979,17 +1973,6 @@ static void program_all_pipe_in_tree(
 
 		dcn10_enable_plane(dc, pipe_ctx, context);
 
-		/* temporary dcn1 wa:
-		 *   watermark update requires toggle after a/b/c/d sets are programmed
-		 *   if hubp is pg then wm value doesn't get properaged to hubp
-		 *   need to toggle after ungate to ensure wm gets to hubp.
-		 *
-		 * final solution:  we need to get SMU to do the toggle as
-		 * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
-		 * both driver and fw accessing same register
-		 */
-		hubbub1_toggle_watermark_change_req(dc->res_pool->hubbub);
-
 		update_dchubp_dpp(dc, pipe_ctx, context);
 
 		/* TODO: this is a hack w/a for switching from mpo to pipe split */
@@ -2101,6 +2084,7 @@ static void dcn10_apply_ctx_for_surface(
 	int i;
 	struct timing_generator *tg;
 	bool removed_pipe[4] = { false };
+	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
 
 	struct pipe_ctx *top_pipe_to_program =
 			find_top_pipe_for_stream(dc, context, stream);
@@ -2163,7 +2147,6 @@ static void dcn10_apply_ctx_for_surface(
 
 	tg->funcs->unlock(tg);
 
-
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *old_pipe_ctx =
 				&dc->current_state->res_ctx.pipe_ctx[i];
@@ -2172,6 +2155,19 @@ static void dcn10_apply_ctx_for_surface(
 			dcn10_disable_plane(dc, old_pipe_ctx);
 	}
 
+	if (dc->debug.sanity_checks) {
+		/* pstate stuck check after watermark update */
+		dcn10_verify_allow_pstate_change_high(dc);
+	}
+	/* watermark is for all pipes */
+	hubbub1_program_watermarks(dc->res_pool->hubbub,
+			&context->bw.dcn.watermarks, ref_clk_mhz);
+
+	if (dc->debug.sanity_checks) {
+		/* pstate stuck check after watermark update */
+		dcn10_verify_allow_pstate_change_high(dc);
+	}
+
 	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
 			"\n============== Watermark parameters ==============\n"
 			"a.urgent_ns: %d \n"
-- 
2.14.1

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[PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

When disabling pipe splitting, we need to make sure we disable both
planes used.

This should be done for Linux as well.

Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 56df1304e49c..d70dbc102123 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
 	return false;
 }
 
+static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+{
+	int i, j;
+	struct dc_state *dangling_context = dc_create_state();
+	struct dc_state *current_ctx;
+
+	if (dangling_context == NULL)
+		return;
+
+	dc_resource_state_copy_construct(dc->current_state, dangling_context);
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_stream_state *old_stream =
+				dc->current_state->res_ctx.pipe_ctx[i].stream;
+		bool should_disable = true;
+
+		for (j = 0; j < context->stream_count; j++) {
+			if (old_stream == context->streams[j]) {
+				should_disable = false;
+				break;
+			}
+		}
+		if (should_disable && old_stream) {
+			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
+			dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+		}
+	}
+
+	current_ctx = dc->current_state;
+	dc->current_state = dangling_context;
+	dc_release_state(current_ctx);
+}
+
 /*******************************************************************************
  * Public functions
  ******************************************************************************/
@@ -833,14 +866,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	int i, k, l;
 	struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
+	disable_dangling_plane(dc, context);
+
 	for (i = 0; i < context->stream_count; i++)
 		dc_streams[i] =  context->streams[i];
 
 	if (!dcb->funcs->is_accelerated_mode(dcb))
 		dc->hwss.enable_accelerated_mode(dc);
 
-
-
 	for (i = 0; i < context->stream_count; i++) {
 		const struct dc_sink *sink = context->streams[i]->sink;
 
@@ -864,8 +897,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 			}
 		}
 
-
-
 		CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
 				context->streams[i]->timing.h_addressable,
 				context->streams[i]->timing.v_addressable,
-- 
2.14.1

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[PATCH 57/73] drm/amd/display: Change frontend/backend programming sequence

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

This is a follow-up to the following change:

Yongqiang Sun: Program front end first when set mode.

Due to pipe-splitting features, how we handle stream enabling and
disabling needs to change.

In the case of pipe split disable, two planes need to be combined back
into the same stream. This needs to be done before any stream
programming happens.

The previous patch addresses this, but breaks cross-platform
compatibility. It's not guaranteed that a dc commit will be called
separately to program planes and streams.

Therefore, we handle the combined commit case by doing plane programming
both before and after stream programming, to handle pipe split disable
and plane enable respectively.

Change-Id: Ia8120f1f9d9e322556577b3054e3b19a1d860de3
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 41 ++++++++++++++++++++++----------
 1 file changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d70dbc102123..c1ae293b41b3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -874,6 +874,33 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	if (!dcb->funcs->is_accelerated_mode(dcb))
 		dc->hwss.enable_accelerated_mode(dc);
 
+	/* Combine planes if required, in case of pipe split disable */
+	for (i = 0; i < dc->current_state->stream_count; i++) {
+		dc->hwss.apply_ctx_for_surface(
+			dc, dc->current_state->streams[i],
+			dc->current_state->stream_status[i].plane_count,
+			dc->current_state);
+	}
+
+	/* Program hardware */
+	dc->hwss.ready_shared_resources(dc, context);
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
+	}
+
+	result = dc->hwss.apply_ctx_to_hw(dc, context);
+
+	if (result != DC_OK)
+		goto fail;
+
+	if (context->stream_count > 1) {
+		enable_timing_multisync(dc, context);
+		program_timing_sync(dc, context);
+	}
+
+	/* Program all planes within new context*/
 	for (i = 0; i < context->stream_count; i++) {
 		const struct dc_sink *sink = context->streams[i]->sink;
 
@@ -905,19 +932,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 				context->streams[i]->timing.pix_clk_khz);
 	}
 
-	dc->hwss.ready_shared_resources(dc, context);
-
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		pipe = &context->res_ctx.pipe_ctx[i];
-		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
-	}
-	result = dc->hwss.apply_ctx_to_hw(dc, context);
-
-	if (context->stream_count > 1) {
-		enable_timing_multisync(dc, context);
-		program_timing_sync(dc, context);
-	}
-
+fail:
 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
 	dc_release_state(dc->current_state);
-- 
2.14.1

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[PATCH 58/73] drm/amd/display: Early return on stream programming failure

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

The fail goto is incorrect. It will incorrectly release the dc_states on
stream programming failure.

Change-Id: Ifefa4561266aaef10235e02dc687f5c0f637e6c1
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c1ae293b41b3..1ccc0c018b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -893,7 +893,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	result = dc->hwss.apply_ctx_to_hw(dc, context);
 
 	if (result != DC_OK)
-		goto fail;
+		return result;
 
 	if (context->stream_count > 1) {
 		enable_timing_multisync(dc, context);
@@ -932,7 +932,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 				context->streams[i]->timing.pix_clk_khz);
 	}
 
-fail:
 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
 	dc_release_state(dc->current_state);
-- 
2.14.1

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[PATCH 59/73] drm/amd/display: Remove legacy unused workaround

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

We shouldn't be able to get a non-visible plane into DC anymore.

Change-Id: I152ff6dabe8e022fd200d0aab42e64e0444b70f9
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1ccc0c018b0e..95a6795af6d9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1153,9 +1153,7 @@ static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
 	}
 }
 
-static enum surface_update_type get_plane_info_update_type(
-		const struct dc_surface_update *u,
-		int surface_index)
+static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
 {
 	struct dc_plane_info temp_plane_info;
 	memset(&temp_plane_info, 0, sizeof(temp_plane_info));
@@ -1179,11 +1177,6 @@ static enum surface_update_type get_plane_info_update_type(
 	temp_plane_info.rotation = u->surface->rotation;
 	temp_plane_info.stereo_format = u->surface->stereo_format;
 
-	if (surface_index == 0)
-		temp_plane_info.visible = u->plane_info->visible;
-	else
-		temp_plane_info.visible = u->surface->visible;
-
 	if (memcmp(u->plane_info, &temp_plane_info,
 			sizeof(struct dc_plane_info)) != 0)
 		return UPDATE_TYPE_FULL;
@@ -1246,10 +1239,8 @@ static enum surface_update_type  get_scaling_info_update_type(
 	return UPDATE_TYPE_FAST;
 }
 
-static enum surface_update_type det_surface_update(
-		const struct dc *dc,
-		const struct dc_surface_update *u,
-		int surface_index)
+static enum surface_update_type det_surface_update(const struct dc *dc,
+												   const struct dc_surface_update *u)
 {
 	const struct dc_state *context = dc->current_state;
 	enum surface_update_type type = UPDATE_TYPE_FAST;
@@ -1258,7 +1249,7 @@ static enum surface_update_type det_surface_update(
 	if (!is_surface_in_context(context, u->surface))
 		return UPDATE_TYPE_FULL;
 
-	type = get_plane_info_update_type(u, surface_index);
+	type = get_plane_info_update_type(u);
 	if (overall_type < type)
 		overall_type = type;
 
@@ -1293,7 +1284,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
 
 	for (i = 0 ; i < surface_count; i++) {
 		enum surface_update_type type =
-				det_surface_update(dc, &updates[i], i);
+				det_surface_update(dc, &updates[i]);
 
 		if (type == UPDATE_TYPE_FULL)
 			return type;
-- 
2.14.1

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[PATCH 60/73] drm/amd/display: Add update flags in to determine surface update type

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

This way, we can know exactly what triggered the update type we're
looking at, and we can simplify the logic for determining what exactly
needs to be updated in the future.

Also allow a dst rect size increase to go through a medium update,
since that does not require us to increase clock or bandwidth.

Change-Id: I06ac694e33c33d4c8bfc31a34b664060b04116a8
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 123 ++++++++++++++++++++-----------
 drivers/gpu/drm/amd/display/dc/dc.h      |  93 +++++++++++++++--------
 2 files changed, 140 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 95a6795af6d9..82e6d33133ab 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -54,6 +54,13 @@
 /*******************************************************************************
  * Private functions
  ******************************************************************************/
+
+static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
+{
+	if (new > *original)
+		*original = new;
+}
+
 static void destroy_links(struct dc *dc)
 {
 	uint32_t i;
@@ -1155,77 +1162,88 @@ static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
 
 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
 {
-	struct dc_plane_info temp_plane_info;
-	memset(&temp_plane_info, 0, sizeof(temp_plane_info));
+	union surface_update_flags *update_flags = &u->surface->update_flags;
 
 	if (!u->plane_info)
 		return UPDATE_TYPE_FAST;
 
-	temp_plane_info = *u->plane_info;
+	if (u->plane_info->color_space != u->surface->color_space)
+		update_flags->bits.color_space_change = 1;
 
-	/* Copy all parameters that will cause a full update
-	 * from current surface, the rest of the parameters
-	 * from provided plane configuration.
-	 * Perform memory compare and special validation
-	 * for those that can cause fast/medium updates
-	 */
+	if (u->plane_info->input_tf != u->surface->input_tf)
+		update_flags->bits.input_tf_change = 1;
 
-	/* Full update parameters */
-	temp_plane_info.color_space = u->surface->color_space;
-	temp_plane_info.input_tf = u->surface->input_tf;
-	temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
-	temp_plane_info.rotation = u->surface->rotation;
-	temp_plane_info.stereo_format = u->surface->stereo_format;
+	if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
+		update_flags->bits.horizontal_mirror_change = 1;
 
-	if (memcmp(u->plane_info, &temp_plane_info,
-			sizeof(struct dc_plane_info)) != 0)
-		return UPDATE_TYPE_FULL;
+	if (u->plane_info->rotation != u->surface->rotation)
+		update_flags->bits.rotation_change = 1;
+
+	if (u->plane_info->stereo_format != u->surface->stereo_format)
+		update_flags->bits.stereo_format_change = 1;
+
+	if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
+		update_flags->bits.per_pixel_alpha_change = 1;
 
 	if (pixel_format_to_bpp(u->plane_info->format) !=
-			pixel_format_to_bpp(u->surface->format)) {
+			pixel_format_to_bpp(u->surface->format))
 		/* different bytes per element will require full bandwidth
 		 * and DML calculation
 		 */
-		return UPDATE_TYPE_FULL;
-	}
+		update_flags->bits.bpp_change = 1;
 
 	if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
 			sizeof(union dc_tiling_info)) != 0) {
+		update_flags->bits.swizzle_change = 1;
 		/* todo: below are HW dependent, we should add a hook to
 		 * DCE/N resource and validated there.
 		 */
-		if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
+		if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
 			/* swizzled mode requires RQ to be setup properly,
 			 * thus need to run DML to calculate RQ settings
 			 */
-			return UPDATE_TYPE_FULL;
-		}
+			update_flags->bits.bandwidth_change = 1;
 	}
 
+	if (update_flags->bits.rotation_change
+			|| update_flags->bits.stereo_format_change
+			|| update_flags->bits.bpp_change
+			|| update_flags->bits.bandwidth_change)
+		return UPDATE_TYPE_FULL;
+
 	return UPDATE_TYPE_MED;
 }
 
-static enum surface_update_type  get_scaling_info_update_type(
+static enum surface_update_type get_scaling_info_update_type(
 		const struct dc_surface_update *u)
 {
+	union surface_update_flags *update_flags = &u->surface->update_flags;
+
 	if (!u->scaling_info)
 		return UPDATE_TYPE_FAST;
 
 	if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
 			|| u->scaling_info->clip_rect.height != u->surface->clip_rect.height
 			|| u->scaling_info->dst_rect.width != u->surface->dst_rect.width
-			|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
-		return UPDATE_TYPE_FULL;
+			|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
+		update_flags->bits.scaling_change = 1;
+
+		if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
+			|| u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
+				&& (u->scaling_info->dst_rect.width < u->surface->src_rect.width
+					|| u->scaling_info->dst_rect.height < u->surface->src_rect.height))
+			/* Making dst rect smaller requires a bandwidth change */
+			update_flags->bits.bandwidth_change = 1;
+	}
 
 	if (u->scaling_info->src_rect.width != u->surface->src_rect.width
 		|| u->scaling_info->src_rect.height != u->surface->src_rect.height) {
 
+		update_flags->bits.scaling_change = 1;
 		if (u->scaling_info->src_rect.width > u->surface->src_rect.width
 				&& u->scaling_info->src_rect.height > u->surface->src_rect.height)
-			return UPDATE_TYPE_FULL;
-
-		/* Upscaling does not require a full update */
-		return UPDATE_TYPE_MED;
+			/* Making src rect bigger requires a bandwidth change */
+			update_flags->bits.clock_change = 1;
 	}
 
 	if (u->scaling_info->src_rect.x != u->surface->src_rect.x
@@ -1234,33 +1252,50 @@ static enum surface_update_type  get_scaling_info_update_type(
 			|| u->scaling_info->clip_rect.y != u->surface->clip_rect.y
 			|| u->scaling_info->dst_rect.x != u->surface->dst_rect.x
 			|| u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
+		update_flags->bits.position_change = 1;
+
+	if (update_flags->bits.clock_change
+			|| update_flags->bits.bandwidth_change)
+		return UPDATE_TYPE_FULL;
+
+	if (update_flags->bits.scaling_change
+			|| update_flags->bits.position_change)
 		return UPDATE_TYPE_MED;
 
 	return UPDATE_TYPE_FAST;
 }
 
 static enum surface_update_type det_surface_update(const struct dc *dc,
-												   const struct dc_surface_update *u)
+		const struct dc_surface_update *u)
 {
 	const struct dc_state *context = dc->current_state;
-	enum surface_update_type type = UPDATE_TYPE_FAST;
+	enum surface_update_type type;
 	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
+	union surface_update_flags *update_flags = &u->surface->update_flags;
+
+	update_flags->raw = 0; // Reset all flags
 
-	if (!is_surface_in_context(context, u->surface))
+	if (!is_surface_in_context(context, u->surface)) {
+		update_flags->bits.new_plane = 1;
 		return UPDATE_TYPE_FULL;
+	}
 
 	type = get_plane_info_update_type(u);
-	if (overall_type < type)
-		overall_type = type;
+	elevate_update_type(&overall_type, type);
 
 	type = get_scaling_info_update_type(u);
-	if (overall_type < type)
-		overall_type = type;
+	elevate_update_type(&overall_type, type);
+
+	if (u->in_transfer_func)
+		update_flags->bits.in_transfer_func = 1;
+
+	if (u->input_csc_color_matrix)
+		update_flags->bits.input_csc_change = 1;
 
-	if (u->in_transfer_func ||
-		u->input_csc_color_matrix) {
-		if (overall_type < UPDATE_TYPE_MED)
-			overall_type = UPDATE_TYPE_MED;
+	if (update_flags->bits.in_transfer_func
+			|| update_flags->bits.input_csc_change) {
+		type = UPDATE_TYPE_MED;
+		elevate_update_type(&overall_type, type);
 	}
 
 	return overall_type;
@@ -1286,11 +1321,11 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
 		enum surface_update_type type =
 				det_surface_update(dc, &updates[i]);
 
+		updates[i].surface->update_type = type;
 		if (type == UPDATE_TYPE_FULL)
 			return type;
 
-		if (overall_type < type)
-			overall_type = type;
+		elevate_update_type(&overall_type, type);
 	}
 
 	return overall_type;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 459a1c55b5cf..f6d431a942a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -99,6 +99,39 @@ struct dc_static_screen_events {
 	bool overlay_update;
 };
 
+
+/* Surface update type is used by dc_update_surfaces_and_stream
+ * The update type is determined at the very beginning of the function based
+ * on parameters passed in and decides how much programming (or updating) is
+ * going to be done during the call.
+ *
+ * UPDATE_TYPE_FAST is used for really fast updates that do not require much
+ * logical calculations or hardware register programming. This update MUST be
+ * ISR safe on windows. Currently fast update will only be used to flip surface
+ * address.
+ *
+ * UPDATE_TYPE_MED is used for slower updates which require significant hw
+ * re-programming however do not affect bandwidth consumption or clock
+ * requirements. At present, this is the level at which front end updates
+ * that do not require us to run bw_calcs happen. These are in/out transfer func
+ * updates, viewport offset changes, recout size changes and pixel depth changes.
+ * This update can be done at ISR, but we want to minimize how often this happens.
+ *
+ * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
+ * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
+ * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
+ * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
+ * a full update. This cannot be done at ISR level and should be a rare event.
+ * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
+ * underscan we don't expect to see this call at all.
+ */
+
+enum surface_update_type {
+	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
+	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
+	UPDATE_TYPE_FULL, /* may need to shuffle resources */
+};
+
 /* Forward declaration*/
 struct dc;
 struct dc_plane_state;
@@ -399,6 +432,32 @@ struct dc_plane_status {
 	bool is_right_eye;
 };
 
+union surface_update_flags {
+
+	struct {
+		/* Medium updates */
+		uint32_t color_space_change:1;
+		uint32_t input_tf_change:1;
+		uint32_t horizontal_mirror_change:1;
+		uint32_t per_pixel_alpha_change:1;
+		uint32_t rotation_change:1;
+		uint32_t swizzle_change:1;
+		uint32_t scaling_change:1;
+		uint32_t position_change:1;
+		uint32_t in_transfer_func:1;
+		uint32_t input_csc_change:1;
+
+		/* Full updates */
+		uint32_t new_plane:1;
+		uint32_t bpp_change:1;
+		uint32_t bandwidth_change:1;
+		uint32_t clock_change:1;
+		uint32_t stereo_format_change:1;
+	} bits;
+
+	uint32_t raw;
+};
+
 struct dc_plane_state {
 	struct dc_plane_address address;
 	struct scaling_taps scaling_quality;
@@ -432,6 +491,8 @@ struct dc_plane_state {
 	bool flip_immediate;
 	bool horizontal_mirror;
 
+	union surface_update_flags update_flags;
+	enum surface_update_type update_type;
 	/* private to DC core */
 	struct dc_plane_status status;
 	struct dc_context *ctx;
@@ -516,38 +577,6 @@ struct dc_flip_addrs {
 bool dc_post_update_surfaces_to_stream(
 		struct dc *dc);
 
-/* Surface update type is used by dc_update_surfaces_and_stream
- * The update type is determined at the very beginning of the function based
- * on parameters passed in and decides how much programming (or updating) is
- * going to be done during the call.
- *
- * UPDATE_TYPE_FAST is used for really fast updates that do not require much
- * logical calculations or hardware register programming. This update MUST be
- * ISR safe on windows. Currently fast update will only be used to flip surface
- * address.
- *
- * UPDATE_TYPE_MED is used for slower updates which require significant hw
- * re-programming however do not affect bandwidth consumption or clock
- * requirements. At present, this is the level at which front end updates
- * that do not require us to run bw_calcs happen. These are in/out transfer func
- * updates, viewport offset changes, recout size changes and pixel depth changes.
- * This update can be done at ISR, but we want to minimize how often this happens.
- *
- * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
- * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
- * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
- * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
- * a full update. This cannot be done at ISR level and should be a rare event.
- * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
- * underscan we don't expect to see this call at all.
- */
-
-enum surface_update_type {
-	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
-	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
-	UPDATE_TYPE_FULL, /* may need to shuffle resources */
-};
-
 /*******************************************************************************
  * Stream Interfaces
  ******************************************************************************/
-- 
2.14.1

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[PATCH 61/73] drm/amd/display: fix plane update prior to stream enablement

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

plane update prior to stream enablement is there to recombine pipe
in case we need free pipe for new display.  need to pass in new state
or we will just re-applyingwhat we already have

Change-Id: I688eced64db9ac785cd36a40603d158088f174f0
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 82e6d33133ab..bb053cbd4db1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -881,12 +881,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	if (!dcb->funcs->is_accelerated_mode(dcb))
 		dc->hwss.enable_accelerated_mode(dc);
 
-	/* Combine planes if required, in case of pipe split disable */
+	/* re-program planes for existing stream, in case we need to
+	 * free up plane resource for later use
+	 */
 	for (i = 0; i < dc->current_state->stream_count; i++) {
 		dc->hwss.apply_ctx_for_surface(
 			dc, dc->current_state->streams[i],
 			dc->current_state->stream_status[i].plane_count,
-			dc->current_state);
+			context); /* use new pipe config in new context */
 	}
 
 	/* Program hardware */
-- 
2.14.1

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[PATCH 62/73] drm/amd/display: Added Opp and Diags Interface for P to I

[Harry Wentland]

From: Arun Pandey <Arun.Pandey@amd.com>

Change-Id: I47b7c9a88eebe84c238f20cd1c9206d06eace7e7
Signed-off-by: Arun Pandey <Arun.Pandey@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   | 29 +++--------------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   | 38 ++++++++++++----------
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h        | 15 +++++++++
 6 files changed, 44 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ffce33fb5540..0bc1cb889992 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -431,13 +431,13 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
 		struct dc *dc)
 {
 	struct dc_stream_state *stream = pipe_ctx->stream;
+	struct mpc *mpc = dc->res_pool->mpc;
 	enum dc_color_space color_space;
 	struct tg_color black_color = {0};
 	bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
 			false:true;
 	bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
 
-
 	/* by upper caller loop, pipe0 is parent pipe and be called first.
 	 * back end is set up by for pipe0. Other children pipe share back end
 	 * with pipe 0. No program is needed.
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 5028619d4fb4..b016f4cbd45c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -335,7 +335,7 @@ void mpc10_update_blend_mode(
 			MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha);
 }
 
-static int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
 {
 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
 	int opp_id = 0xF;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 683ce4aaa76e..e85e1f342266 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -134,5 +134,6 @@ void mpc10_assert_idle_mpcc(
 void mpc10_update_blend_mode(
 		struct mpc *mpc,
 		struct mpcc_cfg *cfg);
+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 71385a004f52..341210060cf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -38,25 +38,6 @@
 	oppn10->base.ctx
 
 
-enum dpg_mode {
-	/* RGB colour block mode */
-	DPG_MODE_RGB_COLOUR_BLOCK,
-	/* YCbCr-601 colour block mode */
-	DPG_MODE_YCBCR_601_COLOUR_BLOCK,
-	/* YCbCr-709 colour block mode */
-	DPG_MODE_YCBCR_709_COLOUR_BLOCK,
-	/* Vertical bar mode */
-	DPG_MODE_VERTICAL_BAR,
-	/* Horizontal bar mode */
-	DPG_MODE_HORIZONTAL_BAR,
-	/* Single ramp mode */
-	DPG_MODE_RGB_SINGLE_RAMP,
-	/* Dual ramp mode */
-	DPG_MODE_RGB_DUAL_RAMP,
-	/* RGB XR BIAS mode */
-	DPG_MODE_RGB_XR_BIAS
-};
-
 /************* FORMATTER ************/
 
 /**
@@ -154,7 +135,7 @@ static void opp1_set_spatial_dither(
 			FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 }
 
-static void opp1_program_bit_depth_reduction(
+void opp1_program_bit_depth_reduction(
 	struct output_pixel_processor *opp,
 	const struct bit_depth_reduction_params *params)
 {
@@ -242,7 +223,7 @@ static void opp1_set_clamping(
 
 }
 
-static void opp1_set_dyn_expansion(
+void opp1_set_dyn_expansion(
 	struct output_pixel_processor *opp,
 	enum dc_color_space color_sp,
 	enum dc_color_depth color_dpth,
@@ -292,7 +273,7 @@ static void opp1_program_clamping_and_pixel_encoding(
 	opp1_set_pixel_encoding(oppn10, params);
 }
 
-static void opp1_program_fmt(
+void opp1_program_fmt(
 	struct output_pixel_processor *opp,
 	struct bit_depth_reduction_params *fmt_bit_depth,
 	struct clamping_and_pixel_encoding_params *clamping)
@@ -315,7 +296,7 @@ static void opp1_program_fmt(
 	return;
 }
 
-static void opp1_set_stereo_polarity(
+void opp1_set_stereo_polarity(
 		struct output_pixel_processor *opp,
 		bool enable, bool rightEyePolarity)
 {
@@ -328,7 +309,7 @@ static void opp1_set_stereo_polarity(
 /* Constructor, Destructor               */
 /*****************************************/
 
-static void opp1_destroy(struct output_pixel_processor **opp)
+void opp1_destroy(struct output_pixel_processor **opp)
 {
 	kfree(TO_DCN10_OPP(*opp));
 	*opp = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index cdb220ed858e..4b1e51050d33 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -74,18 +74,6 @@
 	OPP_MASK_SH_LIST_DCN(mask_sh)
 
 #define OPP_DCN10_REG_FIELD_LIST(type) \
-	type DPG_EN; \
-	type DPG_MODE; \
-	type DPG_VRES; \
-	type DPG_HRES; \
-	type DPG_ACTIVE_WIDTH; \
-	type DPG_ACTIVE_HEIGHT; \
-	type DPG_COLOUR0_R_CR; \
-	type DPG_COLOUR1_R_CR; \
-	type DPG_COLOUR0_B_CB; \
-	type DPG_COLOUR1_B_CB; \
-	type DPG_COLOUR0_G_Y; \
-	type DPG_COLOUR1_G_Y; \
 	type FMT_TRUNCATE_EN; \
 	type FMT_TRUNCATE_DEPTH; \
 	type FMT_TRUNCATE_MODE; \
@@ -118,11 +106,6 @@ struct dcn10_opp_mask {
 };
 
 struct dcn10_opp_registers {
-	uint32_t DPG_CONTROL;
-	uint32_t DPG_DIMENSIONS;
-	uint32_t DPG_COLOUR_B_CB;
-	uint32_t DPG_COLOUR_G_Y;
-	uint32_t DPG_COLOUR_R_CR;
 	uint32_t FMT_BIT_DEPTH_CONTROL;
 	uint32_t FMT_CONTROL;
 	uint32_t FMT_DITHER_RAND_R_SEED;
@@ -150,4 +133,25 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
 	const struct dcn10_opp_shift *opp_shift,
 	const struct dcn10_opp_mask *opp_mask);
 
+void opp1_set_dyn_expansion(
+	struct output_pixel_processor *opp,
+	enum dc_color_space color_sp,
+	enum dc_color_depth color_dpth,
+	enum signal_type signal);
+
+void opp1_program_fmt(
+	struct output_pixel_processor *opp,
+	struct bit_depth_reduction_params *fmt_bit_depth,
+	struct clamping_and_pixel_encoding_params *clamping);
+
+void opp1_program_bit_depth_reduction(
+	struct output_pixel_processor *opp,
+	const struct bit_depth_reduction_params *params);
+
+void opp1_set_stereo_polarity(
+		struct output_pixel_processor *opp,
+		bool enable, bool rightEyePolarity);
+
+void opp1_destroy(struct output_pixel_processor **opp);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index cd6b0d4cd457..579d1059a3d4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -281,6 +281,21 @@ struct opp_funcs {
 			bool enable,
 			bool rightEyePolarity);
 
+	void (*opp_set_test_pattern)(
+			struct output_pixel_processor *opp,
+			bool enable);
+
+	void (*opp_dpg_blank_enable)(
+			struct output_pixel_processor *opp,
+			bool enable,
+			const struct tg_color *color,
+			int width,
+			int height);
+
+	void (*opp_convert_pti)(
+		struct output_pixel_processor *opp,
+		bool enable,
+		bool polarity);
 };
 
 #endif
-- 
2.14.1

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[PATCH 63/73] drm/amd/display: Rename pitch_alignment to linear_pitch_alignment

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

Also initialize this to 64 for all ASICs.

Change-Id: Ia745d8d17e176ac2f65c6ac398d93bdc77fe75d6
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c              | 1 +
 drivers/gpu/drm/amd/display/dc/dc.h                   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 -
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index bb053cbd4db1..0294ff865406 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -696,6 +696,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
 
 	dc->caps.max_links = dc->link_count;
 	dc->caps.max_audios = dc->res_pool->audio_count;
+	dc->caps.linear_pitch_alignment = 64;
 
 	dc->config = init_params->flags;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f6d431a942a1..fb45e1170f42 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -58,7 +58,7 @@ struct dc_caps {
 	uint32_t i2c_speed_in_khz;
 	unsigned int max_cursor_size;
 	unsigned int max_video_width;
-	int pitch_alignment;
+	int linear_pitch_alignment;
 	bool dcc_const_color;
 	bool dynamic_audio;
 	bool is_apu;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 7eb11c61c44e..d818a71b82c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1268,7 +1268,6 @@ static bool construct(
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
 	dc->caps.max_cursor_size = 256;
-	dc->caps.pitch_alignment = 64; /* Alignment is 64 on DCN1 */
 	dc->caps.max_slave_planes = 1;
 	dc->caps.is_apu = true;
 
-- 
2.14.1

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[PATCH 64/73] drm/amd/display: Add check update surfaces for stream wrapper

[Harry Wentland]

From: Andrew Jiang <Andrew.Jiang@amd.com>

This allows us to properly clear and set the update flags for all cases.

Change-Id: I9d4f8295db086f4401284098420af8a37c6bea44
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 24 ++++++++++++++++++++++--
 drivers/gpu/drm/amd/display/dc/dc.h      |  2 +-
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0294ff865406..c2931989eefa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1304,7 +1304,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
 	return overall_type;
 }
 
-enum surface_update_type dc_check_update_surfaces_for_stream(
+static enum surface_update_type check_update_surfaces_for_stream(
 		struct dc *dc,
 		struct dc_surface_update *updates,
 		int surface_count,
@@ -1324,7 +1324,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
 		enum surface_update_type type =
 				det_surface_update(dc, &updates[i]);
 
-		updates[i].surface->update_type = type;
 		if (type == UPDATE_TYPE_FULL)
 			return type;
 
@@ -1334,6 +1333,27 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
 	return overall_type;
 }
 
+enum surface_update_type dc_check_update_surfaces_for_stream(
+		struct dc *dc,
+		struct dc_surface_update *updates,
+		int surface_count,
+		struct dc_stream_update *stream_update,
+		const struct dc_stream_status *stream_status)
+{
+	int i;
+	enum surface_update_type type;
+
+	for (i = 0; i < surface_count; i++)
+		updates[i].surface->update_flags.raw = 0;
+
+	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
+	if (type == UPDATE_TYPE_FULL)
+		for (i = 0; i < surface_count; i++)
+			updates[i].surface->update_flags.bits.full_update = 1;
+
+	return type;
+}
+
 static struct dc_stream_status *stream_get_status(
 	struct dc_state *ctx,
 	struct dc_stream_state *stream)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index fb45e1170f42..5fe86fab6995 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -453,6 +453,7 @@ union surface_update_flags {
 		uint32_t bandwidth_change:1;
 		uint32_t clock_change:1;
 		uint32_t stereo_format_change:1;
+		uint32_t full_update:1;
 	} bits;
 
 	uint32_t raw;
@@ -492,7 +493,6 @@ struct dc_plane_state {
 	bool horizontal_mirror;
 
 	union surface_update_flags update_flags;
-	enum surface_update_type update_type;
 	/* private to DC core */
 	struct dc_plane_status status;
 	struct dc_context *ctx;
-- 
2.14.1

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[PATCH 65/73] drm/amd/display: Fix unused variable warning

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

'struct mpc *mpc' is not used.

Change-Id: Icc20385798c76e41e29f44ccb26d32b044829821
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0bc1cb889992..d0f46e13efca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -431,7 +431,6 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
 		struct dc *dc)
 {
 	struct dc_stream_state *stream = pipe_ctx->stream;
-	struct mpc *mpc = dc->res_pool->mpc;
 	enum dc_color_space color_space;
 	struct tg_color black_color = {0};
 	bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
-- 
2.14.1

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[PATCH 66/73] drm/amd/display: Optimize front end programming.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

for video scaling changes,
Reduce reg access count from 1044 to 447, duration time
from 4.6ms to 3ms.

Change-Id: I92c5f7a30044b977dea5d4334ac12876b8ae5ae5
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 219 +++++++++++----------
 1 file changed, 111 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f46e13efca..30f458701f9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1453,6 +1453,89 @@ static void dcn10_enable_per_frame_crtc_position_reset(
 }
 */
 
+static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
+		struct vm_system_aperture_param *apt,
+		struct dce_hwseq *hws)
+{
+	PHYSICAL_ADDRESS_LOC physical_page_number;
+	uint32_t logical_addr_low;
+	uint32_t logical_addr_high;
+
+	REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+			PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
+	REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+			PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
+
+	REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+			LOGICAL_ADDR, &logical_addr_low);
+
+	REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+			LOGICAL_ADDR, &logical_addr_high);
+
+	apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
+	apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
+	apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
+}
+
+/* Temporary read settings, future will get values from kmd directly */
+static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
+		struct vm_context0_param *vm0,
+		struct dce_hwseq *hws)
+{
+	PHYSICAL_ADDRESS_LOC fb_base;
+	PHYSICAL_ADDRESS_LOC fb_offset;
+	uint32_t fb_base_value;
+	uint32_t fb_offset_value;
+
+	REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
+	REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
+
+	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+			PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
+	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+			PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
+
+	REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
+	REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
+
+	REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
+	REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
+
+	REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+			PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
+	REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+			PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
+
+	/*
+	 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
+	 * Therefore we need to do
+	 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+	 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
+	 */
+	fb_base.quad_part = (uint64_t)fb_base_value << 24;
+	fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
+	vm0->pte_base.quad_part += fb_base.quad_part;
+	vm0->pte_base.quad_part -= fb_offset.quad_part;
+}
+
+
+static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
+{
+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+	struct vm_system_aperture_param apt = { {{ 0 } } };
+	struct vm_context0_param vm0 = { { { 0 } } };
+
+	mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
+	mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
+
+	hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
+	hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
+}
+
 static void dcn10_enable_plane(
 	struct dc *dc,
 	struct pipe_ctx *pipe_ctx,
@@ -1515,6 +1598,8 @@ static void dcn10_enable_plane(
 		print_rq_dlg_ttu(dc, pipe_ctx);
 	}
 */
+	if (dc->config.gpu_vm_support)
+		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
 
 	if (dc->debug.sanity_checks) {
 		dcn10_verify_allow_pstate_change_high(dc);
@@ -1737,93 +1822,6 @@ void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
 	}
 }
 
-static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
-		struct vm_system_aperture_param *apt,
-		struct dce_hwseq *hws)
-{
-	PHYSICAL_ADDRESS_LOC physical_page_number;
-	uint32_t logical_addr_low;
-	uint32_t logical_addr_high;
-
-	REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
-			PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
-	REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
-			PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
-
-	REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
-			LOGICAL_ADDR, &logical_addr_low);
-
-	REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-			LOGICAL_ADDR, &logical_addr_high);
-
-	apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
-	apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
-	apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
-}
-
-/* Temporary read settings, future will get values from kmd directly */
-static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
-		struct vm_context0_param *vm0,
-		struct dce_hwseq *hws)
-{
-	PHYSICAL_ADDRESS_LOC fb_base;
-	PHYSICAL_ADDRESS_LOC fb_offset;
-	uint32_t fb_base_value;
-	uint32_t fb_offset_value;
-
-	REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
-	REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
-
-	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
-			PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
-	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
-			PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
-
-	REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
-			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
-	REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
-			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
-
-	REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
-			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
-	REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
-			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
-
-	REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
-			PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
-	REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
-			PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
-
-	/*
-	 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
-	 * Therefore we need to do
-	 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
-	 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
-	 */
-	fb_base.quad_part = (uint64_t)fb_base_value << 24;
-	fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
-	vm0->pte_base.quad_part += fb_base.quad_part;
-	vm0->pte_base.quad_part -= fb_offset.quad_part;
-}
-
-static void dcn10_program_pte_vm(struct hubp *hubp,
-		enum surface_pixel_format format,
-		union dc_tiling_info *tiling_info,
-		enum dc_rotation_angle rotation,
-		struct dce_hwseq *hws)
-{
-	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-	struct vm_system_aperture_param apt = { {{ 0 } } };
-	struct vm_context0_param vm0 = { { { 0 } } };
-
-
-	mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
-	mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
-
-	hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
-	hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
-}
-
 static void update_dchubp_dpp(
 	struct dc *dc,
 	struct pipe_ctx *pipe_ctx,
@@ -1865,15 +1863,6 @@ static void update_dchubp_dpp(
 
 	size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
 
-	if (dc->config.gpu_vm_support)
-		dcn10_program_pte_vm(
-				pipe_ctx->plane_res.hubp,
-				plane_state->format,
-				&plane_state->tiling_info,
-				plane_state->rotation,
-				hws
-				);
-
 	// program the input csc
 	dpp->funcs->dpp_setup(dpp,
 			plane_state->format,
@@ -1970,18 +1959,11 @@ static void program_all_pipe_in_tree(
 		struct pipe_ctx *cur_pipe_ctx =
 				&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 
-		dcn10_enable_plane(dc, pipe_ctx, context);
+		if (pipe_ctx->plane_state->update_flags.bits.full_update)
+			dcn10_enable_plane(dc, pipe_ctx, context);
 
-		update_dchubp_dpp(dc, pipe_ctx, context);
-
-		/* TODO: this is a hack w/a for switching from mpo to pipe split */
-		if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
-			struct dc_cursor_position position = { 0 };
-
-			dc_stream_set_cursor_position(pipe_ctx->stream, &position);
-			dc_stream_set_cursor_attributes(pipe_ctx->stream,
-				&pipe_ctx->stream->cursor_attributes);
-		}
+		if (pipe_ctx->plane_state->update_flags.raw != 0)
+			update_dchubp_dpp(dc, pipe_ctx, context);
 
 		if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
 			dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
@@ -2141,9 +2123,30 @@ static void dcn10_apply_ctx_for_surface(
 		}
 	}
 
-	if (num_planes > 0)
+	if (num_planes > 0) {
+		struct dc_stream_state *stream_for_cursor;
+
 		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
 
+		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+			if (stream == pipe_ctx->stream) {
+				stream_for_cursor = pipe_ctx->stream;
+				break;
+			}
+		}
+
+		/* TODO: this is a hack w/a for switching from mpo to pipe split */
+		if (stream_for_cursor->cursor_attributes.address.quad_part != 0) {
+			struct dc_cursor_position position = { 0 };
+
+			dc_stream_set_cursor_position(stream_for_cursor, &position);
+			dc_stream_set_cursor_attributes(stream_for_cursor,
+				&stream_for_cursor->cursor_attributes);
+		}
+	}
+
 	tg->funcs->unlock(tg);
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-- 
2.14.1

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[PATCH 67/73] drm/amd/display: Fix formatting for null pointer dereference fix

[Harry Wentland]

Change-Id: I277078c8d6c547fb5a685845f6617bf9886c6fe4
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index f561232e8867..1efa5b62e257 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -285,7 +285,7 @@ bool dc_stream_set_cursor_position(
 			pos_cpy.enable = false;
 
 
-		if (ipp !=NULL && ipp->funcs->ipp_cursor_set_position != NULL)
+		if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
 			ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
 
 		if (mi != NULL && mi->funcs->set_cursor_position != NULL)
-- 
2.14.1

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[PATCH 68/73] drm/amd/display: Move dc_stream interface to separate header

[Harry Wentland]

Change-Id: I390b96c79693dc7d00e39f8dfb8700cf20b7c3f3
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h        | 223 +-----------------------
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 271 +++++++++++++++++++++++++++++
 2 files changed, 273 insertions(+), 221 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dc_stream.h

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5fe86fab6995..170cdcb5a027 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -137,6 +137,7 @@ struct dc;
 struct dc_plane_state;
 struct dc_state;
 
+
 struct dc_cap_funcs {
 	bool (*get_dcc_compression_cap)(const struct dc *dc,
 			const struct dc_dcc_surface_param *input,
@@ -577,168 +578,7 @@ struct dc_flip_addrs {
 bool dc_post_update_surfaces_to_stream(
 		struct dc *dc);
 
-/*******************************************************************************
- * Stream Interfaces
- ******************************************************************************/
-
-struct dc_stream_status {
-	int primary_otg_inst;
-	int stream_enc_inst;
-	int plane_count;
-	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
-
-	/*
-	 * link this stream passes through
-	 */
-	struct dc_link *link;
-};
-
-struct dc_stream_state {
-	struct dc_sink *sink;
-	struct dc_crtc_timing timing;
-
-	struct rect src; /* composition area */
-	struct rect dst; /* stream addressable area */
-
-	struct audio_info audio_info;
-
-	struct freesync_context freesync_ctx;
-
-	struct dc_hdr_static_metadata hdr_static_metadata;
-	struct dc_transfer_func *out_transfer_func;
-	struct colorspace_transform gamut_remap_matrix;
-	struct csc_transform csc_color_matrix;
-
-	enum dc_color_space output_color_space;
-	enum dc_dither_option dither_option;
-
-	enum view_3d_format view_format;
-
-	bool ignore_msa_timing_param;
-	/* TODO: custom INFO packets */
-	/* TODO: ABM info (DMCU) */
-	/* TODO: PSR info */
-	/* TODO: CEA VIC */
-
-	/* from core_stream struct */
-	struct dc_context *ctx;
-
-	/* used by DCP and FMT */
-	struct bit_depth_reduction_params bit_depth_params;
-	struct clamping_and_pixel_encoding_params clamping;
-
-	int phy_pix_clk;
-	enum signal_type signal;
-	bool dpms_off;
-
-	struct dc_stream_status status;
-
-	struct dc_cursor_attributes cursor_attributes;
-
-	/* from stream struct */
-	struct kref refcount;
-
-	struct crtc_trigger_info triggered_crtc_reset;
-
-};
-
-struct dc_stream_update {
-	struct rect src;
-	struct rect dst;
-	struct dc_transfer_func *out_transfer_func;
-	struct dc_hdr_static_metadata *hdr_static_metadata;
-};
-
-bool dc_is_stream_unchanged(
-	struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-bool dc_is_stream_scaling_unchanged(
-	struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-
-/*
- * Set up surface attributes and associate to a stream
- * The surfaces parameter is an absolute set of all surface active for the stream.
- * If no surfaces are provided, the stream will be blanked; no memory read.
- * Any flip related attribute changes must be done through this interface.
- *
- * After this call:
- *   Surfaces attributes are programmed and configured to be composed into stream.
- *   This does not trigger a flip.  No surface address is programmed.
- */
-
-bool dc_commit_planes_to_stream(
-		struct dc *dc,
-		struct dc_plane_state **plane_states,
-		uint8_t new_plane_count,
-		struct dc_stream_state *dc_stream,
-		struct dc_state *state);
-
-void dc_commit_updates_for_stream(struct dc *dc,
-		struct dc_surface_update *srf_updates,
-		int surface_count,
-		struct dc_stream_state *stream,
-		struct dc_stream_update *stream_update,
-		struct dc_plane_state **plane_states,
-		struct dc_state *state);
-/*
- * Log the current stream state.
- */
-void dc_stream_log(
-	const struct dc_stream_state *stream,
-	struct dal_logger *dc_logger,
-	enum dc_log_type log_type);
-
-uint8_t dc_get_current_stream_count(struct dc *dc);
-struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
-
-/*
- * Return the current frame counter.
- */
-uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
-
-/* TODO: Return parsed values rather than direct register read
- * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
- * being refactored properly to be dce-specific
- */
-bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
-				  uint32_t *v_blank_start,
-				  uint32_t *v_blank_end,
-				  uint32_t *h_position,
-				  uint32_t *v_position);
-
-enum dc_status dc_add_stream_to_ctx(
-			struct dc *dc,
-		struct dc_state *new_ctx,
-		struct dc_stream_state *stream);
-
-enum dc_status dc_remove_stream_from_ctx(
-		struct dc *dc,
-			struct dc_state *new_ctx,
-			struct dc_stream_state *stream);
-
-
-bool dc_add_plane_to_context(
-		const struct dc *dc,
-		struct dc_stream_state *stream,
-		struct dc_plane_state *plane_state,
-		struct dc_state *context);
-
-bool dc_remove_plane_from_context(
-		const struct dc *dc,
-		struct dc_stream_state *stream,
-		struct dc_plane_state *plane_state,
-		struct dc_state *context);
-
-bool dc_rem_all_planes_for_stream(
-		const struct dc *dc,
-		struct dc_stream_state *stream,
-		struct dc_state *context);
-
-bool dc_add_all_planes_for_stream(
-		const struct dc *dc,
-		struct dc_stream_state *stream,
-		struct dc_plane_state * const *plane_states,
-		int plane_count,
-		struct dc_state *context);
+#include "dc_stream.h"
 
 /*
  * Structure to store surface/stream associations for validation
@@ -749,22 +589,12 @@ struct dc_validation_set {
 	uint8_t plane_count;
 };
 
-enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
-
 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
 
 enum dc_status dc_validate_global_state(
 		struct dc *dc,
 		struct dc_state *new_ctx);
 
-/*
- * This function takes a stream and checks if it is guaranteed to be supported.
- * Guaranteed means that MAX_COFUNC similar streams are supported.
- *
- * After this call:
- *   No hardware is programmed for call.  Only validation is done.
- */
-
 
 void dc_resource_state_construct(
 		const struct dc *dc,
@@ -791,42 +621,6 @@ void dc_resource_state_destruct(struct dc_state *context);
  */
 bool dc_commit_state(struct dc *dc, struct dc_state *context);
 
-/*
- * Set up streams and links associated to drive sinks
- * The streams parameter is an absolute set of all active streams.
- *
- * After this call:
- *   Phy, Encoder, Timing Generator are programmed and enabled.
- *   New streams are enabled with blank stream; no memory read.
- */
-/*
- * Enable stereo when commit_streams is not required,
- * for example, frame alternate.
- */
-bool dc_enable_stereo(
-	struct dc *dc,
-	struct dc_state *context,
-	struct dc_stream_state *streams[],
-	uint8_t stream_count);
-
-/**
- * Create a new default stream for the requested sink
- */
-struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
-
-void dc_stream_retain(struct dc_stream_state *dc_stream);
-void dc_stream_release(struct dc_stream_state *dc_stream);
-
-struct dc_stream_status *dc_stream_get_status(
-	struct dc_stream_state *dc_stream);
-
-enum surface_update_type dc_check_update_surfaces_for_stream(
-		struct dc *dc,
-		struct dc_surface_update *updates,
-		int surface_count,
-		struct dc_stream_update *stream_update,
-		const struct dc_stream_status *stream_status);
-
 
 struct dc_state *dc_create_state(void);
 void dc_retain_state(struct dc_state *context);
@@ -1076,18 +870,6 @@ struct dc_sink_init_data {
 
 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
 
-/*******************************************************************************
- * Cursor interfaces - To manages the cursor within a stream
- ******************************************************************************/
-/* TODO: Deprecated once we switch to dc_set_cursor_position */
-bool dc_stream_set_cursor_attributes(
-	struct dc_stream_state *stream,
-	const struct dc_cursor_attributes *attributes);
-
-bool dc_stream_set_cursor_position(
-	struct dc_stream_state *stream,
-	const struct dc_cursor_position *position);
-
 /* Newer interfaces  */
 struct dc_cursor {
 	struct dc_plane_address address;
@@ -1124,5 +906,4 @@ bool dc_submit_i2c(
 		uint32_t link_index,
 		struct i2c_command *cmd);
 
-
 #endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
new file mode 100644
index 000000000000..bed2a937de71
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2012-14 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DC_STREAM_H_
+#define DC_STREAM_H_
+
+#include "dc_types.h"
+#include "grph_object_defs.h"
+
+/*******************************************************************************
+ * Stream Interfaces
+ ******************************************************************************/
+
+struct dc_stream_status {
+	int primary_otg_inst;
+	int stream_enc_inst;
+	int plane_count;
+	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
+
+	/*
+	 * link this stream passes through
+	 */
+	struct dc_link *link;
+};
+
+struct dc_stream_state {
+	struct dc_sink *sink;
+	struct dc_crtc_timing timing;
+
+	struct rect src; /* composition area */
+	struct rect dst; /* stream addressable area */
+
+	struct audio_info audio_info;
+
+	struct freesync_context freesync_ctx;
+
+	struct dc_hdr_static_metadata hdr_static_metadata;
+	struct dc_transfer_func *out_transfer_func;
+	struct colorspace_transform gamut_remap_matrix;
+	struct csc_transform csc_color_matrix;
+
+	enum dc_color_space output_color_space;
+	enum dc_dither_option dither_option;
+
+	enum view_3d_format view_format;
+
+	bool ignore_msa_timing_param;
+	/* TODO: custom INFO packets */
+	/* TODO: ABM info (DMCU) */
+	/* TODO: PSR info */
+	/* TODO: CEA VIC */
+
+	/* from core_stream struct */
+	struct dc_context *ctx;
+
+	/* used by DCP and FMT */
+	struct bit_depth_reduction_params bit_depth_params;
+	struct clamping_and_pixel_encoding_params clamping;
+
+	int phy_pix_clk;
+	enum signal_type signal;
+	bool dpms_off;
+
+	struct dc_stream_status status;
+
+	struct dc_cursor_attributes cursor_attributes;
+
+	/* from stream struct */
+	struct kref refcount;
+
+	struct crtc_trigger_info triggered_crtc_reset;
+
+};
+
+struct dc_stream_update {
+	struct rect src;
+	struct rect dst;
+	struct dc_transfer_func *out_transfer_func;
+	struct dc_hdr_static_metadata *hdr_static_metadata;
+};
+
+bool dc_is_stream_unchanged(
+	struct dc_stream_state *old_stream, struct dc_stream_state *stream);
+bool dc_is_stream_scaling_unchanged(
+	struct dc_stream_state *old_stream, struct dc_stream_state *stream);
+
+/*
+ * Set up surface attributes and associate to a stream
+ * The surfaces parameter is an absolute set of all surface active for the stream.
+ * If no surfaces are provided, the stream will be blanked; no memory read.
+ * Any flip related attribute changes must be done through this interface.
+ *
+ * After this call:
+ *   Surfaces attributes are programmed and configured to be composed into stream.
+ *   This does not trigger a flip.  No surface address is programmed.
+ */
+
+bool dc_commit_planes_to_stream(
+		struct dc *dc,
+		struct dc_plane_state **plane_states,
+		uint8_t new_plane_count,
+		struct dc_stream_state *dc_stream,
+		struct dc_state *state);
+
+void dc_commit_updates_for_stream(struct dc *dc,
+		struct dc_surface_update *srf_updates,
+		int surface_count,
+		struct dc_stream_state *stream,
+		struct dc_stream_update *stream_update,
+		struct dc_plane_state **plane_states,
+		struct dc_state *state);
+/*
+ * Log the current stream state.
+ */
+void dc_stream_log(
+	const struct dc_stream_state *stream,
+	struct dal_logger *dc_logger,
+	enum dc_log_type log_type);
+
+uint8_t dc_get_current_stream_count(struct dc *dc);
+struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
+
+/*
+ * Return the current frame counter.
+ */
+uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
+
+/* TODO: Return parsed values rather than direct register read
+ * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
+ * being refactored properly to be dce-specific
+ */
+bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+				  uint32_t *v_blank_start,
+				  uint32_t *v_blank_end,
+				  uint32_t *h_position,
+				  uint32_t *v_position);
+
+enum dc_status dc_add_stream_to_ctx(
+			struct dc *dc,
+		struct dc_state *new_ctx,
+		struct dc_stream_state *stream);
+
+enum dc_status dc_remove_stream_from_ctx(
+		struct dc *dc,
+			struct dc_state *new_ctx,
+			struct dc_stream_state *stream);
+
+
+bool dc_add_plane_to_context(
+		const struct dc *dc,
+		struct dc_stream_state *stream,
+		struct dc_plane_state *plane_state,
+		struct dc_state *context);
+
+bool dc_remove_plane_from_context(
+		const struct dc *dc,
+		struct dc_stream_state *stream,
+		struct dc_plane_state *plane_state,
+		struct dc_state *context);
+
+bool dc_rem_all_planes_for_stream(
+		const struct dc *dc,
+		struct dc_stream_state *stream,
+		struct dc_state *context);
+
+bool dc_add_all_planes_for_stream(
+		const struct dc *dc,
+		struct dc_stream_state *stream,
+		struct dc_plane_state * const *plane_states,
+		int plane_count,
+		struct dc_state *context);
+
+enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
+
+/*
+ * This function takes a stream and checks if it is guaranteed to be supported.
+ * Guaranteed means that MAX_COFUNC similar streams are supported.
+ *
+ * After this call:
+ *   No hardware is programmed for call.  Only validation is done.
+ */
+
+/*
+ * Set up streams and links associated to drive sinks
+ * The streams parameter is an absolute set of all active streams.
+ *
+ * After this call:
+ *   Phy, Encoder, Timing Generator are programmed and enabled.
+ *   New streams are enabled with blank stream; no memory read.
+ */
+/*
+ * Enable stereo when commit_streams is not required,
+ * for example, frame alternate.
+ */
+bool dc_enable_stereo(
+	struct dc *dc,
+	struct dc_state *context,
+	struct dc_stream_state *streams[],
+	uint8_t stream_count);
+
+
+enum surface_update_type dc_check_update_surfaces_for_stream(
+		struct dc *dc,
+		struct dc_surface_update *updates,
+		int surface_count,
+		struct dc_stream_update *stream_update,
+		const struct dc_stream_status *stream_status);
+
+/**
+ * Create a new default stream for the requested sink
+ */
+struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
+
+void dc_stream_retain(struct dc_stream_state *dc_stream);
+void dc_stream_release(struct dc_stream_state *dc_stream);
+
+struct dc_stream_status *dc_stream_get_status(
+	struct dc_stream_state *dc_stream);
+
+/*******************************************************************************
+ * Cursor interfaces - To manages the cursor within a stream
+ ******************************************************************************/
+/* TODO: Deprecated once we switch to dc_set_cursor_position */
+bool dc_stream_set_cursor_attributes(
+	struct dc_stream_state *stream,
+	const struct dc_cursor_attributes *attributes);
+
+bool dc_stream_set_cursor_position(
+	struct dc_stream_state *stream,
+	const struct dc_cursor_position *position);
+
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
+				struct dc_stream_state **stream,
+				int num_streams,
+				int vmin,
+				int vmax);
+
+bool dc_stream_get_crtc_position(struct dc *dc,
+				 struct dc_stream_state **stream,
+				 int num_streams,
+				 unsigned int *v_pos,
+				 unsigned int *nom_v_pos);
+
+void dc_stream_set_static_screen_events(struct dc *dc,
+					struct dc_stream_state **stream,
+					int num_streams,
+					const struct dc_static_screen_events *events);
+
+#endif /* DC_STREAM_H_ */
-- 
2.14.1

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[PATCH 69/73] drm/amd/display: Move dc_link interface to separate header

[Harry Wentland]

Change-Id: Id35bc6b48dde03068ed554fe7dcf72bd40009769
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h      | 175 +-------------------------
 drivers/gpu/drm/amd/display/dc/dc_link.h | 207 +++++++++++++++++++++++++++++++
 2 files changed, 208 insertions(+), 174 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dc_link.h

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 170cdcb5a027..5c509707ccd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -653,171 +653,7 @@ struct dpcd_caps {
 	bool dpcd_display_control_capable;
 };
 
-struct dc_link_status {
-	struct dpcd_caps *dpcd_caps;
-};
-
-/* DP MST stream allocation (payload bandwidth number) */
-struct link_mst_stream_allocation {
-	/* DIG front */
-	const struct stream_encoder *stream_enc;
-	/* associate DRM payload table with DC stream encoder */
-	uint8_t vcp_id;
-	/* number of slots required for the DP stream in transport packet */
-	uint8_t slot_count;
-};
-
-/* DP MST stream allocation table */
-struct link_mst_stream_allocation_table {
-	/* number of DP video streams */
-	int stream_count;
-	/* array of stream allocations */
-	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
-};
-
-/*
- * A link contains one or more sinks and their connected status.
- * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
- */
-struct dc_link {
-	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
-	unsigned int sink_count;
-	struct dc_sink *local_sink;
-	unsigned int link_index;
-	enum dc_connection_type type;
-	enum signal_type connector_signal;
-	enum dc_irq_source irq_source_hpd;
-	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
-	/* caps is the same as reported_link_cap. link_traing use
-	 * reported_link_cap. Will clean up.  TODO
-	 */
-	struct dc_link_settings reported_link_cap;
-	struct dc_link_settings verified_link_cap;
-	struct dc_link_settings cur_link_settings;
-	struct dc_lane_settings cur_lane_setting;
-	struct dc_link_settings preferred_link_setting;
-
-	uint8_t ddc_hw_inst;
-
-	uint8_t hpd_src;
-
-	uint8_t link_enc_hw_inst;
-
-	bool test_pattern_enabled;
-	union compliance_test_state compliance_test_state;
-
-	void *priv;
-
-	struct ddc_service *ddc;
-
-	bool aux_mode;
-
-	/* Private to DC core */
-
-	const struct dc *dc;
-
-	struct dc_context *ctx;
-
-	struct link_encoder *link_enc;
-	struct graphics_object_id link_id;
-	union ddi_channel_mapping ddi_channel_mapping;
-	struct connector_device_tag_info device_tag;
-	struct dpcd_caps dpcd_caps;
-	unsigned short chip_caps;
-	unsigned int dpcd_sink_count;
-	enum edp_revision edp_revision;
-	bool psr_enabled;
-
-	/* MST record stream using this link */
-	struct link_flags {
-		bool dp_keep_receiver_powered;
-	} wa_flags;
-	struct link_mst_stream_allocation_table mst_stream_alloc_table;
-
-	struct dc_link_status link_status;
-
-};
-
-const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
-
-/*
- * Return an enumerated dc_link.  dc_link order is constant and determined at
- * boot time.  They cannot be created or destroyed.
- * Use dc_get_caps() to get number of links.
- */
-static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
-{
-	return dc->links[link_index];
-}
-
-/* Set backlight level of an embedded panel (eDP, LVDS). */
-bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
-		uint32_t frame_ramp, const struct dc_stream_state *stream);
-
-bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
-
-bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
-
-bool dc_link_setup_psr(struct dc_link *dc_link,
-		const struct dc_stream_state *stream, struct psr_config *psr_config,
-		struct psr_context *psr_context);
-
-/* Request DC to detect if there is a Panel connected.
- * boot - If this call is during initial boot.
- * Return false for any type of detection failure or MST detection
- * true otherwise. True meaning further action is required (status update
- * and OS notification).
- */
-enum dc_detect_reason {
-	DETECT_REASON_BOOT,
-	DETECT_REASON_HPD,
-	DETECT_REASON_HPDRX,
-};
-
-bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
-
-/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
- * Return:
- * true - Downstream port status changed. DM should call DC to do the
- * detection.
- * false - no change in Downstream port status. No further action required
- * from DM. */
-bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
-		union hpd_irq_data *hpd_irq_dpcd_data);
-
-struct dc_sink_init_data;
-
-struct dc_sink *dc_link_add_remote_sink(
-		struct dc_link *dc_link,
-		const uint8_t *edid,
-		int len,
-		struct dc_sink_init_data *init_data);
-
-void dc_link_remove_remote_sink(
-	struct dc_link *link,
-	struct dc_sink *sink);
-
-/* Used by diagnostics for virtual link at the moment */
-
-void dc_link_dp_set_drive_settings(
-	struct dc_link *link,
-	struct link_training_settings *lt_settings);
-
-enum link_training_result dc_link_dp_perform_link_training(
-	struct dc_link *link,
-	const struct dc_link_settings *link_setting,
-	bool skip_video_pattern);
-
-void dc_link_dp_enable_hpd(const struct dc_link *link);
-
-void dc_link_dp_disable_hpd(const struct dc_link *link);
-
-bool dc_link_dp_set_test_pattern(
-	struct dc_link *link,
-	enum dp_test_pattern test_pattern,
-	const struct link_training_settings *p_link_settings,
-	const unsigned char *p_custom_pattern,
-	unsigned int cust_pattern_size);
+#include "dc_link.h"
 
 /*******************************************************************************
  * Sink Interfaces - A sink corresponds to a display output device
@@ -897,13 +733,4 @@ void dc_set_power_state(
 		enum dc_acpi_cm_power_state power_state);
 void dc_resume(struct dc *dc);
 
-/*
- * DPCD access interfaces
- */
-
-bool dc_submit_i2c(
-		struct dc *dc,
-		uint32_t link_index,
-		struct i2c_command *cmd);
-
 #endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
new file mode 100644
index 000000000000..f11a734da1db
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2012-14 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DC_LINK_H_
+#define DC_LINK_H_
+
+#include "dc_types.h"
+#include "grph_object_defs.h"
+
+struct dc_link_status {
+	struct dpcd_caps *dpcd_caps;
+};
+
+/* DP MST stream allocation (payload bandwidth number) */
+struct link_mst_stream_allocation {
+	/* DIG front */
+	const struct stream_encoder *stream_enc;
+	/* associate DRM payload table with DC stream encoder */
+	uint8_t vcp_id;
+	/* number of slots required for the DP stream in transport packet */
+	uint8_t slot_count;
+};
+
+/* DP MST stream allocation table */
+struct link_mst_stream_allocation_table {
+	/* number of DP video streams */
+	int stream_count;
+	/* array of stream allocations */
+	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
+};
+
+/*
+ * A link contains one or more sinks and their connected status.
+ * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
+ */
+struct dc_link {
+	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
+	unsigned int sink_count;
+	struct dc_sink *local_sink;
+	unsigned int link_index;
+	enum dc_connection_type type;
+	enum signal_type connector_signal;
+	enum dc_irq_source irq_source_hpd;
+	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
+	/* caps is the same as reported_link_cap. link_traing use
+	 * reported_link_cap. Will clean up.  TODO
+	 */
+	struct dc_link_settings reported_link_cap;
+	struct dc_link_settings verified_link_cap;
+	struct dc_link_settings cur_link_settings;
+	struct dc_lane_settings cur_lane_setting;
+	struct dc_link_settings preferred_link_setting;
+
+	uint8_t ddc_hw_inst;
+
+	uint8_t hpd_src;
+
+	uint8_t link_enc_hw_inst;
+
+	bool test_pattern_enabled;
+	union compliance_test_state compliance_test_state;
+
+	void *priv;
+
+	struct ddc_service *ddc;
+
+	bool aux_mode;
+
+	/* Private to DC core */
+
+	const struct dc *dc;
+
+	struct dc_context *ctx;
+
+	struct link_encoder *link_enc;
+	struct graphics_object_id link_id;
+	union ddi_channel_mapping ddi_channel_mapping;
+	struct connector_device_tag_info device_tag;
+	struct dpcd_caps dpcd_caps;
+	unsigned short chip_caps;
+	unsigned int dpcd_sink_count;
+	enum edp_revision edp_revision;
+	bool psr_enabled;
+
+	/* MST record stream using this link */
+	struct link_flags {
+		bool dp_keep_receiver_powered;
+	} wa_flags;
+	struct link_mst_stream_allocation_table mst_stream_alloc_table;
+
+	struct dc_link_status link_status;
+
+};
+
+const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
+
+/*
+ * Return an enumerated dc_link.  dc_link order is constant and determined at
+ * boot time.  They cannot be created or destroyed.
+ * Use dc_get_caps() to get number of links.
+ */
+static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
+{
+	return dc->links[link_index];
+}
+
+/* Set backlight level of an embedded panel (eDP, LVDS). */
+bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
+		uint32_t frame_ramp, const struct dc_stream_state *stream);
+
+bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
+
+bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
+
+bool dc_link_setup_psr(struct dc_link *dc_link,
+		const struct dc_stream_state *stream, struct psr_config *psr_config,
+		struct psr_context *psr_context);
+
+/* Request DC to detect if there is a Panel connected.
+ * boot - If this call is during initial boot.
+ * Return false for any type of detection failure or MST detection
+ * true otherwise. True meaning further action is required (status update
+ * and OS notification).
+ */
+enum dc_detect_reason {
+	DETECT_REASON_BOOT,
+	DETECT_REASON_HPD,
+	DETECT_REASON_HPDRX,
+};
+
+bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
+
+/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
+ * Return:
+ * true - Downstream port status changed. DM should call DC to do the
+ * detection.
+ * false - no change in Downstream port status. No further action required
+ * from DM. */
+bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
+		union hpd_irq_data *hpd_irq_dpcd_data);
+
+struct dc_sink_init_data;
+
+struct dc_sink *dc_link_add_remote_sink(
+		struct dc_link *dc_link,
+		const uint8_t *edid,
+		int len,
+		struct dc_sink_init_data *init_data);
+
+void dc_link_remove_remote_sink(
+	struct dc_link *link,
+	struct dc_sink *sink);
+
+/* Used by diagnostics for virtual link at the moment */
+
+void dc_link_dp_set_drive_settings(
+	struct dc_link *link,
+	struct link_training_settings *lt_settings);
+
+enum link_training_result dc_link_dp_perform_link_training(
+	struct dc_link *link,
+	const struct dc_link_settings *link_setting,
+	bool skip_video_pattern);
+
+void dc_link_dp_enable_hpd(const struct dc_link *link);
+
+void dc_link_dp_disable_hpd(const struct dc_link *link);
+
+bool dc_link_dp_set_test_pattern(
+	struct dc_link *link,
+	enum dp_test_pattern test_pattern,
+	const struct link_training_settings *p_link_settings,
+	const unsigned char *p_custom_pattern,
+	unsigned int cust_pattern_size);
+
+/*
+ * DPCD access interfaces
+ */
+
+bool dc_submit_i2c(
+		struct dc *dc,
+		uint32_t link_index,
+		struct i2c_command *cmd);
+
+#endif /* DC_LINK_H_ */
-- 
2.14.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 70/73] drm/amd/display: Remove unnecessary dc_stream vtable

[Harry Wentland]

There's no need to have this as a vtable. The vtable was initially
used for stream_adjust_vmin_vmax but the condition checked here
(set_drr) is always true, hence we don't need to assign this
dynamically anymore.

Change-Id: I60e3c213b4566b3808b8feb001b93b74bcf7f17a
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 136 +--------------------
 drivers/gpu/drm/amd/display/dc/dc_stream.h         |  18 +++
 .../drm/amd/display/modules/freesync/freesync.c    |  84 +++++--------
 3 files changed, 51 insertions(+), 187 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c2931989eefa..ca9e6bc13352 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -158,7 +158,7 @@ static bool create_links(
 	return false;
 }
 
-static bool stream_adjust_vmin_vmax(struct dc *dc,
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 		struct dc_stream_state **streams, int num_streams,
 		int vmin, int vmax)
 {
@@ -183,7 +183,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc,
 	return ret;
 }
 
-static bool stream_get_crtc_position(struct dc *dc,
+bool dc_stream_get_crtc_position(struct dc *dc,
 		struct dc_stream_state **streams, int num_streams,
 		unsigned int *v_pos, unsigned int *nom_v_pos)
 {
@@ -208,45 +208,7 @@ static bool stream_get_crtc_position(struct dc *dc,
 	return ret;
 }
 
-static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
-{
-	int i = 0;
-	bool ret = false;
-	struct pipe_ctx *pipes;
-
-	for (i = 0; i < MAX_PIPES; i++) {
-		if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
-			pipes = &dc->current_state->res_ctx.pipe_ctx[i];
-			dc->hwss.program_gamut_remap(pipes);
-			ret = true;
-		}
-	}
-
-	return ret;
-}
-
-static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
-{
-	int i = 0;
-	bool ret = false;
-	struct pipe_ctx *pipes;
-
-	for (i = 0; i < MAX_PIPES; i++) {
-		if (dc->current_state->res_ctx.pipe_ctx[i].stream
-				== stream) {
-
-			pipes = &dc->current_state->res_ctx.pipe_ctx[i];
-			dc->hwss.program_csc_matrix(pipes,
-			stream->output_color_space,
-			stream->csc_color_matrix.matrix);
-			ret = true;
-		}
-	}
-
-	return ret;
-}
-
-static void set_static_screen_events(struct dc *dc,
+void dc_stream_set_static_screen_events(struct dc *dc,
 		struct dc_stream_state **streams,
 		int num_streams,
 		const struct dc_static_screen_events *events)
@@ -337,100 +299,8 @@ static void set_test_pattern(
 			cust_pattern_size);
 }
 
-static void set_dither_option(struct dc_stream_state *stream,
-		enum dc_dither_option option)
-{
-	struct bit_depth_reduction_params params;
-	struct dc_link *link = stream->status.link;
-	struct pipe_ctx *pipes = NULL;
-	int i;
-
-	for (i = 0; i < MAX_PIPES; i++) {
-		if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
-				stream) {
-			pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
-			break;
-		}
-	}
-
-	memset(&params, 0, sizeof(params));
-	if (!pipes)
-		return;
-	if (option > DITHER_OPTION_MAX)
-		return;
-
-	stream->dither_option = option;
-
-	resource_build_bit_depth_reduction_params(stream,
-				&params);
-	stream->bit_depth_params = params;
-	pipes->stream_res.opp->funcs->
-		opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
-}
-
-void set_dpms(
-	struct dc *dc,
-	struct dc_stream_state *stream,
-	bool dpms_off)
-{
-	struct pipe_ctx *pipe_ctx = NULL;
-	int i;
-
-	for (i = 0; i < MAX_PIPES; i++) {
-		if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
-			pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
-			break;
-		}
-	}
-
-	if (!pipe_ctx) {
-		ASSERT(0);
-		return;
-	}
-
-	if (stream->dpms_off != dpms_off) {
-		stream->dpms_off = dpms_off;
-
-		if (dpms_off) {
-			core_link_disable_stream(pipe_ctx,
-					KEEP_ACQUIRED_RESOURCE);
-
-			dc->hwss.pplib_apply_display_requirements(
-					dc, dc->current_state);
-		} else {
-			dc->hwss.pplib_apply_display_requirements(
-					dc, dc->current_state);
-
-			core_link_enable_stream(dc->current_state, pipe_ctx);
-		}
-	}
-}
-
 static void allocate_dc_stream_funcs(struct dc  *dc)
 {
-	if (dc->hwss.set_drr != NULL) {
-		dc->stream_funcs.adjust_vmin_vmax =
-				stream_adjust_vmin_vmax;
-	}
-
-	dc->stream_funcs.set_static_screen_events =
-			set_static_screen_events;
-
-	dc->stream_funcs.get_crtc_position =
-			stream_get_crtc_position;
-
-	dc->stream_funcs.set_gamut_remap =
-			set_gamut_remap;
-
-	dc->stream_funcs.program_csc_matrix =
-			program_csc_matrix;
-
-	dc->stream_funcs.set_dither_option =
-			set_dither_option;
-
-	dc->stream_funcs.set_dpms =
-			set_dpms;
-
 	dc->link_funcs.set_drive_settings =
 			set_drive_settings;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index bed2a937de71..9a64cf16c798 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -251,6 +251,24 @@ bool dc_stream_set_cursor_position(
 	struct dc_stream_state *stream,
 	const struct dc_cursor_position *position);
 
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
+				struct dc_stream_state **stream,
+				int num_streams,
+				int vmin,
+				int vmax);
+
+bool dc_stream_get_crtc_position(struct dc *dc,
+				 struct dc_stream_state **stream,
+				 int num_streams,
+				 unsigned int *v_pos,
+				 unsigned int *nom_v_pos);
+
+void dc_stream_set_static_screen_events(struct dc *dc,
+					struct dc_stream_state **stream,
+					int num_streams,
+					const struct dc_static_screen_events *events);
+
+
 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 				struct dc_stream_state **stream,
 				int num_streams,
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4d7db4aa28e0..b4723af368a5 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -132,14 +132,6 @@ struct core_freesync {
 #define MOD_FREESYNC_TO_CORE(mod_freesync)\
 		container_of(mod_freesync, struct core_freesync, public)
 
-static bool check_dc_support(const struct dc *dc)
-{
-	if (dc->stream_funcs.adjust_vmin_vmax == NULL)
-		return false;
-
-	return true;
-}
-
 struct mod_freesync *mod_freesync_create(struct dc *dc)
 {
 	struct core_freesync *core_freesync =
@@ -169,9 +161,6 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
 
 	core_freesync->dc = dc;
 
-	if (!check_dc_support(dc))
-		goto fail_construct;
-
 	/* Create initial module folder in registry for freesync enable data */
 	flag.save_per_edid = true;
 	flag.save_per_link = false;
@@ -599,10 +588,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync,
 				update_stream_freesync_context(core_freesync,
 						streams[stream_idx]);
 
-				core_freesync->dc->stream_funcs.
-				adjust_vmin_vmax(core_freesync->dc, streams,
-						num_streams, v_total_min,
-						v_total_max);
+				dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+							   num_streams, v_total_min,
+							   v_total_max);
 
 				return true;
 
@@ -625,8 +613,7 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync,
 						core_freesync,
 						streams[stream_idx]);
 
-					core_freesync->dc->stream_funcs.
-					adjust_vmin_vmax(
+					dc_stream_adjust_vmin_vmax(
 						core_freesync->dc, streams,
 						num_streams, v_total_nominal,
 						v_total_nominal);
@@ -645,11 +632,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync,
 					core_freesync,
 					streams[stream_idx]);
 
-				core_freesync->dc->stream_funcs.
-						adjust_vmin_vmax(
-						core_freesync->dc, streams,
-						num_streams, v_total_nominal,
-						v_total_nominal);
+				dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+							   num_streams, v_total_nominal,
+							   v_total_nominal);
 
 				/* Reset the cached variables */
 				reset_freesync_state_variables(state);
@@ -665,11 +650,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync,
 			 * not support freesync because a former stream has
 			 * be programmed
 			 */
-			core_freesync->dc->stream_funcs.
-					adjust_vmin_vmax(
-					core_freesync->dc, streams,
-					num_streams, v_total_nominal,
-					v_total_nominal);
+			dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+						   num_streams, v_total_nominal,
+						   v_total_nominal);
 			/* Reset the cached variables */
 			reset_freesync_state_variables(state);
 		}
@@ -786,9 +769,8 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 			vmin = inserted_frame_v_total;
 
 			/* Program V_TOTAL */
-			core_freesync->dc->stream_funcs.adjust_vmin_vmax(
-				core_freesync->dc, streams,
-				num_streams, vmin, vmax);
+			dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+						   num_streams, vmin, vmax);
 		}
 
 		if (state->btr.frame_counter > 0)
@@ -822,17 +804,15 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 		update_stream_freesync_context(core_freesync, streams[0]);
 
 		/* Program static screen ramp values */
-		core_freesync->dc->stream_funcs.adjust_vmin_vmax(
-					core_freesync->dc, streams,
-					num_streams, v_total,
-					v_total);
+		dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
+					   num_streams, v_total,
+					   v_total);
 
 		triggers.overlay_update = true;
 		triggers.surface_update = true;
 
-		core_freesync->dc->stream_funcs.set_static_screen_events(
-					core_freesync->dc, streams,	num_streams,
-					&triggers);
+		dc_stream_set_static_screen_events(core_freesync->dc, streams,
+						   num_streams, &triggers);
 	}
 }
 
@@ -916,9 +896,8 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync,
 	triggers.overlay_update = true;
 	triggers.surface_update = true;
 
-	core_freesync->dc->stream_funcs.set_static_screen_events(
-		core_freesync->dc, streams, num_streams,
-		&triggers);
+	dc_stream_set_static_screen_events(core_freesync->dc, streams,
+					   num_streams, &triggers);
 
 	if (freesync_program_required)
 		/* Program freesync according to current state*/
@@ -1084,10 +1063,9 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
 				max_refresh);
 
 		/* Program vtotal min/max */
-		core_freesync->dc->stream_funcs.adjust_vmin_vmax(
-			core_freesync->dc, &streams, 1,
-			state->freesync_range.vmin,
-			state->freesync_range.vmax);
+		dc_stream_adjust_vmin_vmax(core_freesync->dc, &streams, 1,
+					   state->freesync_range.vmin,
+					   state->freesync_range.vmax);
 	}
 
 	if (min_refresh != 0 &&
@@ -1163,9 +1141,9 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
 	index = map_index_from_stream(core_freesync, stream);
 
-	if (core_freesync->dc->stream_funcs.get_crtc_position(
-			core_freesync->dc, &stream, 1,
-			&position.vertical_count, &position.nominal_vcount)) {
+	if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
+					&position.vertical_count,
+					&position.nominal_vcount)) {
 
 		*nom_v_pos = position.nominal_vcount;
 		*v_pos = position.vertical_count;
@@ -1223,9 +1201,9 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
 			triggers.overlay_update = true;
 			triggers.surface_update = true;
 
-			core_freesync->dc->stream_funcs.set_static_screen_events(
-				core_freesync->dc, streams, num_streams,
-				&triggers);
+			dc_stream_set_static_screen_events(core_freesync->dc,
+							   streams, num_streams,
+							   &triggers);
 		}
 	}
 
@@ -1424,10 +1402,8 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync,
 
 		vmax = vmin;
 
-		core_freesync->dc->stream_funcs.adjust_vmin_vmax(
-				core_freesync->dc, &stream,
-				1, vmin,
-				vmax);
+		dc_stream_adjust_vmin_vmax(core_freesync->dc, &stream,
+					   1, vmin, vmax);
 	}
 }
 
-- 
2.14.1

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[PATCH 71/73] drm/amd/display: remove stream_func vtable

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: I5fd90f7b53efd60dc2a0559edfcc90e9ab1bf5ff
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 32 --------------------------------
 1 file changed, 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5c509707ccd6..dbb03b3e2c23 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -144,37 +144,6 @@ struct dc_cap_funcs {
 			struct dc_surface_dcc_cap *output);
 };
 
-struct dc_stream_state_funcs {
-	bool (*adjust_vmin_vmax)(struct dc *dc,
-			struct dc_stream_state **stream,
-			int num_streams,
-			int vmin,
-			int vmax);
-	bool (*get_crtc_position)(struct dc *dc,
-			struct dc_stream_state **stream,
-			int num_streams,
-			unsigned int *v_pos,
-			unsigned int *nom_v_pos);
-
-	bool (*set_gamut_remap)(struct dc *dc,
-			const struct dc_stream_state *stream);
-
-	bool (*program_csc_matrix)(struct dc *dc,
-			struct dc_stream_state *stream);
-
-	void (*set_static_screen_events)(struct dc *dc,
-			struct dc_stream_state **stream,
-			int num_streams,
-			const struct dc_static_screen_events *events);
-
-	void (*set_dither_option)(struct dc_stream_state *stream,
-			enum dc_dither_option option);
-
-	void (*set_dpms)(struct dc *dc,
-			struct dc_stream_state *stream,
-			bool dpms_off);
-};
-
 struct link_training_settings;
 
 struct dc_link_funcs {
@@ -268,7 +237,6 @@ struct dce_hwseq;
 struct dc {
 	struct dc_caps caps;
 	struct dc_cap_funcs cap_funcs;
-	struct dc_stream_state_funcs stream_funcs;
 	struct dc_link_funcs link_funcs;
 	struct dc_config config;
 	struct dc_debug debug;
-- 
2.14.1

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[PATCH 72/73] drm/amd/display: Fix Linux after optimize frontend programming

[Harry Wentland]

We still require the update_plane_addr call in commit_planes_for_stream.

Change-Id: I281c0106e02bf9828a750c28590f12726d16196d
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ca9e6bc13352..b71422d636ac 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1308,11 +1308,8 @@ static void commit_planes_for_stream(struct dc *dc,
 			if (pipe_ctx->plane_state != plane_state)
 				continue;
 
-			if (update_type == UPDATE_TYPE_FAST) {
-				if (srf_updates[i].flip_addr)
-					dc->hwss.update_plane_addr(dc, pipe_ctx);
-				continue;
-			}
+			if (srf_updates[i].flip_addr)
+				dc->hwss.update_plane_addr(dc, pipe_ctx);
 		}
 	}
 
-- 
2.14.1

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[PATCH 73/73] drm/amd/display: Fix use before initialize warning

[Harry Wentland]

From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>

on stream_for_cursor. Initialize to NULL.

Change-Id: Ic032bfe78b33e466e560d33488e0fd8df060f694
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 30f458701f9c..b5d048b364a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2124,7 +2124,7 @@ static void dcn10_apply_ctx_for_surface(
 	}
 
 	if (num_planes > 0) {
-		struct dc_stream_state *stream_for_cursor;
+		struct dc_stream_state *stream_for_cursor = NULL;
 
 		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
 
-- 
2.14.1

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Re: [PATCH 44/73] drm/amd/display: add flip_immediate to commit update for stream

[Michel Dänzer]

On 09/11/17 09:05 PM, Harry Wentland wrote:
> From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> 
> This struct is not updated on page flip and causes vblank_mode
> to not work as expected
> 
> Change-Id: I0e8684c5b67ec5670054f4bb849fa26bc60ed4b1
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> Acked-by: Harry Wentland <harry.wentland@amd.com>

I provided

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

for this patch in https://bugs.freedesktop.org/show_bug.cgi?id=103486#c9 .


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 15/73] drm/amd/display: Don't use dc_link in link_encoder

[Andrey Grodzovsky]

On 11/09/2017 03:05 PM, Harry Wentland wrote:
> From: Andrew Jiang <Andrew.Jiang@amd.com>
>
> dc_link is at a higher level than link_encoder, and we only want
> higher-level components to be able to access lower-level ones,
> not the other way around.
>
> Change-Id: I634b117b386938fb7ddba50c50484fadd54ad485
> Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> Acked-by: Harry Wentland <harry.wentland@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  2 +-
>   drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 +++---
>   .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 34 +++++++---------
>   .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  5 +--
>   .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 46 ++++++++++++----------
>   .../amd/display/dc/dce110/dce110_hw_sequencer.h    |  4 +-
>   .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 ++
>   .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |  2 +-
>   drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  2 +-
>   .../amd/display/dc/virtual/virtual_link_encoder.c  |  3 +-
>   10 files changed, 57 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index a6a762a26fd2..3b394a5f1c66 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1798,7 +1798,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
>   		else
>   			dp_disable_link_phy_mst(link, signal);
>   	} else
> -		link->link_enc->funcs->disable_output(link->link_enc, signal, link);
> +		link->link_enc->funcs->disable_output(link->link_enc, signal);
>   }
>   
>   bool dp_active_dongle_validate_timing(
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> index 9a33b471270a..f2902569be2e 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> @@ -89,7 +89,7 @@ void dp_enable_link_phy(
>   
>   	if (dc_is_dp_sst_signal(signal)) {
>   		if (signal == SIGNAL_TYPE_EDP) {
> -			link->dc->hwss.edp_power_control(link->link_enc, true);
> +			link->dc->hwss.edp_power_control(link, true);
>   			link_enc->funcs->enable_dp_output(
>   						link_enc,
>   						link_settings,
> @@ -140,10 +140,10 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
>   	if (signal == SIGNAL_TYPE_EDP) {
>   		link->dc->hwss.edp_backlight_control(link, false);
>   		edp_receiver_ready_T9(link);
> -		link->link_enc->funcs->disable_output(link->link_enc, signal, link);
> -		link->dc->hwss.edp_power_control(link->link_enc, false);
> +		link->link_enc->funcs->disable_output(link->link_enc, signal);
> +		link->dc->hwss.edp_power_control(link, false);
>   	} else
> -		link->link_enc->funcs->disable_output(link->link_enc, signal, link);
> +		link->link_enc->funcs->disable_output(link->link_enc, signal);
>   
>   	/* Clear current link setting.*/
>   	memset(&link->cur_link_settings, 0,
> @@ -286,8 +286,7 @@ void dp_retrain_link_dp_test(struct dc_link *link,
>   
>   			link->link_enc->funcs->disable_output(
>   					link->link_enc,
> -					SIGNAL_TYPE_DISPLAY_PORT,
> -					link);
> +					SIGNAL_TYPE_DISPLAY_PORT);
>   
>   			/* Clear current link setting. */
>   			memset(&link->cur_link_settings, 0,
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> index fe88852b4774..bad70c6b3aad 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
> @@ -845,8 +845,6 @@ void dce110_link_encoder_hw_init(
>   
>   		ASSERT(result == BP_RESULT_OK);
>   
> -	} else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
> -		ctx->dc->hwss.edp_power_control(enc, true);
>   	}
>   	aux_initialize(enc110);
>   
> @@ -1033,8 +1031,7 @@ void dce110_link_encoder_enable_dp_mst_output(
>    */
>   void dce110_link_encoder_disable_output(
>   	struct link_encoder *enc,
> -	enum signal_type signal,
> -	struct dc_link *link)
> +	enum signal_type signal)
>   {
>   	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
>   	struct dc_context *ctx = enc110->base.ctx;
> @@ -1045,8 +1042,6 @@ void dce110_link_encoder_disable_output(
>   		/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
>   		return;
>   	}
> -	if (enc110->base.connector.id == CONNECTOR_ID_EDP)
> -		ctx->dc->hwss.edp_backlight_control(link, false);
>   	/* Power-down RX and disable GPU PHY should be paired.
>   	 * Disabling PHY without powering down RX may cause
>   	 * symbol lock loss, on which we will get DP Sink interrupt. */
> @@ -1078,19 +1073,20 @@ void dce110_link_encoder_disable_output(
>   	if (dc_is_dp_signal(signal))
>   		link_encoder_disable(enc110);
>   
> -	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
> -		/* power down eDP panel */
> -		/* TODO: Power control cause regression, we should implement
> -		 * it properly, for now just comment it.
> -		 *
> -		 * link_encoder_edp_wait_for_hpd_ready(
> -			link_enc,
> -			link_enc->connector,
> -			false);
> -
> -		 * link_encoder_edp_power_control(
> -				link_enc, false); */
> -	}
> +	/*
> +	 * TODO: Power control cause regression, we should implement
> +	 * it properly, for now just comment it.
> +	 */
> +//	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
> +//		/* power down eDP panel */
> +//		link_encoder_edp_wait_for_hpd_ready(
> +//				enc,
> +//				enc->connector,
> +//				false);
> +//
> +//		link_encoder_edp_power_control(
> +//				enc, false);
> +//	}
>   }

This is wrong comment style, please check 
https://www.kernel.org/doc/html/v4.10/process/coding-style.html , section 8.

Thanks,
Andrey

>   
>   void dce110_link_encoder_dp_set_lane_settings(
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
> index 494067dedd03..8ca9afe47a2b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
> @@ -228,9 +228,8 @@ void dce110_link_encoder_enable_dp_mst_output(
>   
>   /* disable PHY output */
>   void dce110_link_encoder_disable_output(
> -	struct link_encoder *link_enc,
> -	enum signal_type signal,
> -	struct dc_link *link);
> +	struct link_encoder *enc,
> +	enum signal_type signal);
>   
>   /* set DP lane settings */
>   void dce110_link_encoder_dp_set_lane_settings(
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index b4504f1f49c0..4135de2d7203 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -814,11 +814,11 @@ static enum bp_result link_transmitter_control(
>    * eDP only.
>    */
>   void hwss_edp_wait_for_hpd_ready(
> -	struct link_encoder *enc,
> -	bool power_up)
> +		struct dc_link *link,
> +		bool power_up)
>   {
> -	struct dc_context *ctx = enc->ctx;
> -	struct graphics_object_id connector = enc->connector;
> +	struct dc_context *ctx = link->ctx;
> +	struct graphics_object_id connector = link->link_enc->connector;
>   	struct gpio *hpd;
>   	bool edp_hpd_high = false;
>   	uint32_t time_elapsed = 0;
> @@ -882,16 +882,16 @@ void hwss_edp_wait_for_hpd_ready(
>   }
>   
>   void hwss_edp_power_control(
> -	struct link_encoder *enc,
> -	bool power_up)
> +		struct dc_link *link,
> +		bool power_up)
>   {
> -	struct dc_context *ctx = enc->ctx;
> +	struct dc_context *ctx = link->ctx;
>   	struct dce_hwseq *hwseq = ctx->dc->hwseq;
>   	struct bp_transmitter_control cntl = { 0 };
>   	enum bp_result bp_result;
>   
>   
> -	if (dal_graphics_object_id_get_connector_id(enc->connector)
> +	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
>   			!= CONNECTOR_ID_EDP) {
>   		BREAK_TO_DEBUGGER();
>   		return;
> @@ -907,11 +907,11 @@ void hwss_edp_power_control(
>   		cntl.action = power_up ?
>   			TRANSMITTER_CONTROL_POWER_ON :
>   			TRANSMITTER_CONTROL_POWER_OFF;
> -		cntl.transmitter = enc->transmitter;
> -		cntl.connector_obj_id = enc->connector;
> +		cntl.transmitter = link->link_enc->transmitter;
> +		cntl.connector_obj_id = link->link_enc->connector;
>   		cntl.coherent = false;
>   		cntl.lanes_number = LANE_COUNT_FOUR;
> -		cntl.hpd_sel = enc->hpd_source;
> +		cntl.hpd_sel = link->link_enc->hpd_source;
>   
>   		bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
>   
> @@ -925,7 +925,7 @@ void hwss_edp_power_control(
>   				__func__, (power_up ? "On":"Off"));
>   	}
>   
> -	hwss_edp_wait_for_hpd_ready(enc, true);
> +	hwss_edp_wait_for_hpd_ready(link, true);
>   }
>   
>   /*todo: cloned in stream enc, fix*/
> @@ -934,14 +934,14 @@ void hwss_edp_power_control(
>    * eDP only. Control the backlight of the eDP panel
>    */
>   void hwss_edp_backlight_control(
> -	struct dc_link *link,
> -	bool enable)
> +		struct dc_link *link,
> +		bool enable)
>   {
> -	struct dce_hwseq *hws = link->dc->hwseq;
> -	struct dc_context *ctx = link->dc->ctx;
> +	struct dc_context *ctx = link->ctx;
> +	struct dce_hwseq *hws = ctx->dc->hwseq;
>   	struct bp_transmitter_control cntl = { 0 };
>   
> -	if (dal_graphics_object_id_get_connector_id(link->link_id)
> +	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
>   		!= CONNECTOR_ID_EDP) {
>   		BREAK_TO_DEBUGGER();
>   		return;
> @@ -982,7 +982,7 @@ void hwss_edp_backlight_control(
>   	 * Enable it in the future if necessary.
>   	 */
>   	/* dc_service_sleep_in_milliseconds(50); */
> -	link_transmitter_control(link->dc->ctx->dc_bios, &cntl);
> +	link_transmitter_control(ctx->dc_bios, &cntl);
>   }
>   
>   void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
> @@ -1398,12 +1398,14 @@ static void power_down_encoders(struct dc *dc)
>   
>   			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
>   				dp_receiver_power_ctrl(dc->links[i], false);
> -			if (connector_id == CONNECTOR_ID_EDP)
> +			if (connector_id == CONNECTOR_ID_EDP) {
>   				signal = SIGNAL_TYPE_EDP;
> +				hwss_edp_backlight_control(dc->links[i], false);
> +			}
>   		}
>   
>   		dc->links[i]->link_enc->funcs->disable_output(
> -				dc->links[i]->link_enc, signal, dc->links[i]);
> +				dc->links[i]->link_enc, signal);
>   	}
>   }
>   
> @@ -2539,6 +2541,10 @@ static void init_hw(struct dc *dc)
>   		 * required signal (which may be different from the
>   		 * default signal on connector). */
>   		struct dc_link *link = dc->links[i];
> +
> +		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
> +			dc->hwss.edp_power_control(link, true);
> +
>   		link->link_enc->funcs->hw_init(link->link_enc);
>   	}
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
> index 4d72bb99be93..2dd6ac637572 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
> @@ -70,8 +70,8 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
>   void dp_receiver_power_ctrl(struct dc_link *link, bool on);
>   
>   void hwss_edp_power_control(
> -	struct link_encoder *enc,
> -	bool power_up);
> +		struct dc_link *link,
> +		bool power_up);
>   
>   void hwss_edp_backlight_control(
>   	struct dc_link *link,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index dc37551399ba..51b7cfe9581f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -723,6 +723,9 @@ static void dcn10_init_hw(struct dc *dc)
>   		 */
>   		struct dc_link *link = dc->links[i];
>   
> +		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
> +			dc->hwss.edp_power_control(link, true);
> +
>   		link->link_enc->funcs->hw_init(link->link_enc);
>   	}
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> index 3d33bcda7059..8a08f0a97f94 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> @@ -111,7 +111,7 @@ struct link_encoder_funcs {
>   		const struct dc_link_settings *link_settings,
>   		enum clock_source_id clock_source);
>   	void (*disable_output)(struct link_encoder *link_enc,
> -		enum signal_type signal, struct dc_link *link);
> +		enum signal_type signal);
>   	void (*dp_set_lane_settings)(struct link_encoder *enc,
>   		const struct link_training_settings *link_settings);
>   	void (*dp_set_phy_pattern)(struct link_encoder *enc,
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
> index cebbba345889..f3c5468854bd 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
> @@ -184,7 +184,7 @@ struct hw_sequencer_funcs {
>   	void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
>   	void (*optimize_shared_resources)(struct dc *dc);
>   	void (*edp_power_control)(
> -			struct link_encoder *enc,
> +			struct dc_link *link,
>   			bool enable);
>   	void (*edp_backlight_control)(
>   			struct dc_link *link,
> diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
> index 88c2bde3f039..57a54a7b89e5 100644
> --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
> @@ -58,8 +58,7 @@ static void virtual_link_encoder_enable_dp_mst_output(
>   
>   static void virtual_link_encoder_disable_output(
>   	struct link_encoder *link_enc,
> -	enum signal_type signal,
> -	struct dc_link *link) {}
> +	enum signal_type signal) {}
>   
>   static void virtual_link_encoder_dp_set_lane_settings(
>   	struct link_encoder *enc,

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Re: [PATCH 38/73] drm/amd/display: Fix warnings on S3 resume

[Andrey Grodzovsky]

On 11/09/2017 03:05 PM, Harry Wentland wrote:
> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>
> This is a followup to the following revert:
>
> Rex Zhu    Revert "drm/amd/display: Match actual state during S3
>             resume."
>
> Three things needed to be addressed:
>
> 1. Potential memory leak on dc_state creation in atomic_check during
>     s3 resume
> 2. Warnings are now seen in dmesg during S3 resume
> 3. Since dc_state is now created in atomic_check, what the reverted
>     patch was addressing needs to be reevaluated.
>
> This change addresses the above:
>
> 1. Since the suspend procedure calls drm_atomic_state_clear, our hook
>     for releasing the dc_state is called. This frees it before
>     atomic_check creates it during resume. The leak does not occur.
>
> 2. The dc_crtc/plane_state references kept by the atomic states need to
>     be released before calling atomic_check, which warns if they are
>     non-null. This is because atomic_check is responsible for creating
>     the dc_*_states. This is a special case for S3 resume, since the
>     atomic state duplication that occurs during suspend also copies a
>     reference to the dc_*_states.
>
> 3. See 2. comments are also updated to reflect this.
>
> Change-Id: I6e342bf8134f0e5dc32888a8d894c2cd20d28296
> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
> ---
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++++++++++++++++++++++
>   1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 1c7f22146bc9..bdef1ed0dfac 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
>   	struct drm_connector *connector;
>   	struct drm_crtc *crtc;
>   	struct drm_crtc_state *new_crtc_state;
> +	struct dm_crtc_state *dm_new_crtc_state;
> +	struct drm_plane *plane;
> +	struct drm_plane_state *new_plane_state;
> +	struct dm_plane_state *dm_new_plane_state;
> +
>   	int ret = 0;
>   	int i;
>   
> @@ -685,6 +690,29 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
>   	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
>   		new_crtc_state->active_changed = true;
>   
> +	/*
> +	 * atomic_check is expected to create the dc states. We need to release
> +	 * them here, since they were duplicated as part of the suspend
> +	 * procedure.
> +	 */
> +	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
> +		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
> +		if (dm_new_crtc_state->stream) {
> +			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
> +			dc_stream_release(dm_new_crtc_state->stream);
> +			dm_new_crtc_state->stream = NULL;
> +		}
> +	}
> +
> +	for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
> +		dm_new_plane_state = to_dm_plane_state(new_plane_state);
> +		if (dm_new_plane_state->dc_state) {
> +			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
> +			dc_plane_state_release(dm_new_plane_state->dc_state);
> +			dm_new_plane_state->dc_state = NULL;
> +		}
> +	}

I guess the warnings you are referring to are in dm_update_crtcs_state 
and dm_update_planes_state,
but I don't understand why you need to explicitly release them in 
amdgpu_dm_resume, any changed
plane/crtc states will be removed during atomic check anyway and only 
after that new one will be added,
I find strange that this doesn't work.

P.S I tried to reproduce this to see the warnings with latest 
amd-staging-drm-next (776fb8c)on CZ but the system becomes
unimpressive after going to suspend, might wanna check this on your side.

Thanks,
Andrey

> +
>   	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
>   
>   	drm_atomic_state_put(adev->dm.cached_state);

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Re: [PATCH 38/73] drm/amd/display: Fix warnings on S3 resume

[Andrey Grodzovsky]

On 11/10/2017 01:38 PM, Andrey Grodzovsky wrote:
>
>
> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>
>> This is a followup to the following revert:
>>
>> Rex Zhu    Revert "drm/amd/display: Match actual state during S3
>>             resume."
>>
>> Three things needed to be addressed:
>>
>> 1. Potential memory leak on dc_state creation in atomic_check during
>>     s3 resume
>> 2. Warnings are now seen in dmesg during S3 resume
>> 3. Since dc_state is now created in atomic_check, what the reverted
>>     patch was addressing needs to be reevaluated.
>>
>> This change addresses the above:
>>
>> 1. Since the suspend procedure calls drm_atomic_state_clear, our hook
>>     for releasing the dc_state is called. This frees it before
>>     atomic_check creates it during resume. The leak does not occur.
>>
>> 2. The dc_crtc/plane_state references kept by the atomic states need to
>>     be released before calling atomic_check, which warns if they are
>>     non-null. This is because atomic_check is responsible for creating
>>     the dc_*_states. This is a special case for S3 resume, since the
>>     atomic state duplication that occurs during suspend also copies a
>>     reference to the dc_*_states.
>>
>> 3. See 2. comments are also updated to reflect this.
>>
>> Change-Id: I6e342bf8134f0e5dc32888a8d894c2cd20d28296
>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 
>> +++++++++++++++++++++++
>>   1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 1c7f22146bc9..bdef1ed0dfac 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct 
>> amdgpu_device *adev)
>>       struct drm_connector *connector;
>>       struct drm_crtc *crtc;
>>       struct drm_crtc_state *new_crtc_state;
>> +    struct dm_crtc_state *dm_new_crtc_state;
>> +    struct drm_plane *plane;
>> +    struct drm_plane_state *new_plane_state;
>> +    struct dm_plane_state *dm_new_plane_state;
>> +
>>       int ret = 0;
>>       int i;
>>   @@ -685,6 +690,29 @@ int amdgpu_dm_display_resume(struct 
>> amdgpu_device *adev)
>>       for_each_new_crtc_in_state(adev->dm.cached_state, crtc, 
>> new_crtc_state, i)
>>           new_crtc_state->active_changed = true;
>>   +    /*
>> +     * atomic_check is expected to create the dc states. We need to 
>> release
>> +     * them here, since they were duplicated as part of the suspend
>> +     * procedure.
>> +     */
>> +    for_each_new_crtc_in_state(adev->dm.cached_state, crtc, 
>> new_crtc_state, i) {
>> +        dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
>> +        if (dm_new_crtc_state->stream) {
>> + WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
>> +            dc_stream_release(dm_new_crtc_state->stream);
>> +            dm_new_crtc_state->stream = NULL;
>> +        }
>> +    }
>> +
>> +    for_each_new_plane_in_state(adev->dm.cached_state, plane, 
>> new_plane_state, i) {
>> +        dm_new_plane_state = to_dm_plane_state(new_plane_state);
>> +        if (dm_new_plane_state->dc_state) {
>> + WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
>> + dc_plane_state_release(dm_new_plane_state->dc_state);
>> +            dm_new_plane_state->dc_state = NULL;
>> +        }
>> +    }
>
> I guess the warnings you are referring to are in dm_update_crtcs_state 
> and dm_update_planes_state,
> but I don't understand why you need to explicitly release them in 
> amdgpu_dm_resume, any changed
> plane/crtc states will be removed during atomic check anyway and only 
> after that new one will be added,
> I find strange that this doesn't work.
>
> P.S I tried to reproduce this to see the warnings with latest 
> amd-staging-drm-next (776fb8c)on CZ but the system becomes
> unimpressive after going to suspend, might wanna check this on your side.

UNRESPONSIVE (it's unimpressive in any case :) )

Andrey

>
> Thanks,
> Andrey
>
>> +
>>       ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
>>         drm_atomic_state_put(adev->dm.cached_state);
>
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Andrey Grodzovsky]

On 11/09/2017 03:05 PM, Harry Wentland wrote:
> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>
> When disabling pipe splitting, we need to make sure we disable both
> planes used.
>
> This should be done for Linux as well.
>
> Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
> Acked-by: Harry Wentland <harry.wentland@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++++++++++++++++++++++----
>   1 file changed, 35 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 56df1304e49c..d70dbc102123 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
>   	return false;
>   }
>   
> +static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
> +{
> +	int i, j;
> +	struct dc_state *dangling_context = dc_create_state();
> +	struct dc_state *current_ctx;
> +
> +	if (dangling_context == NULL)
> +		return;
> +
> +	dc_resource_state_copy_construct(dc->current_state, dangling_context);
> +
> +	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> +		struct dc_stream_state *old_stream =
> +				dc->current_state->res_ctx.pipe_ctx[i].stream;
> +		bool should_disable = true;
> +
> +		for (j = 0; j < context->stream_count; j++) {
> +			if (old_stream == context->streams[j]) {
> +				should_disable = false;
> +				break;
> +			}
> +		}
> +		if (should_disable && old_stream) {
> +			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);

Why this is not happening in atomic_check during dm_update_planes_state 
with enable set to false ? Since the old stream is present
I assume old crtc_state for planes to disable is present and as I see 
from the code it should happen in that function

Thanks,
Andrey

> +			dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
> +		}
> +	}
> +
> +	current_ctx = dc->current_state;
> +	dc->current_state = dangling_context;
> +	dc_release_state(current_ctx);
> +}
> +
>   /*******************************************************************************
>    * Public functions
>    ******************************************************************************/
> @@ -833,14 +866,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>   	int i, k, l;
>   	struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
>   
> +	disable_dangling_plane(dc, context);
> +
>   	for (i = 0; i < context->stream_count; i++)
>   		dc_streams[i] =  context->streams[i];
>   
>   	if (!dcb->funcs->is_accelerated_mode(dcb))
>   		dc->hwss.enable_accelerated_mode(dc);
>   
> -
> -
>   	for (i = 0; i < context->stream_count; i++) {
>   		const struct dc_sink *sink = context->streams[i]->sink;
>   
> @@ -864,8 +897,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>   			}
>   		}
>   
> -
> -
>   		CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
>   				context->streams[i]->timing.h_addressable,
>   				context->streams[i]->timing.v_addressable,

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Re: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Leo Li]

On 2017-11-10 02:00 PM, Andrey Grodzovsky wrote:
> 
> 
> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>
>> When disabling pipe splitting, we need to make sure we disable both
>> planes used.
>>
>> This should be done for Linux as well.
>>
>> Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>> Acked-by: Harry Wentland <harry.wentland@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/dc/core/dc.c | 39 
>> ++++++++++++++++++++++++++++----
>>   1 file changed, 35 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> index 56df1304e49c..d70dbc102123 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> @@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
>>       return false;
>>   }
>> +static void disable_dangling_plane(struct dc *dc, struct dc_state 
>> *context)
>> +{
>> +    int i, j;
>> +    struct dc_state *dangling_context = dc_create_state();
>> +    struct dc_state *current_ctx;
>> +
>> +    if (dangling_context == NULL)
>> +        return;
>> +
>> +    dc_resource_state_copy_construct(dc->current_state, 
>> dangling_context);
>> +
>> +    for (i = 0; i < dc->res_pool->pipe_count; i++) {
>> +        struct dc_stream_state *old_stream =
>> +                dc->current_state->res_ctx.pipe_ctx[i].stream;
>> +        bool should_disable = true;
>> +
>> +        for (j = 0; j < context->stream_count; j++) {
>> +            if (old_stream == context->streams[j]) {
>> +                should_disable = false;
>> +                break;
>> +            }
>> +        }
>> +        if (should_disable && old_stream) {
>> +            dc_rem_all_planes_for_stream(dc, old_stream, 
>> dangling_context);
> 
> Why this is not happening in atomic_check during dm_update_planes_state 
> with enable set to false ? Since the old stream is present
> I assume old crtc_state for planes to disable is present and as I see 
> from the code it should happen in that function
> 
> Thanks,
> Andrey
You're correct, the above logic should be done in atomic check. However,
the apply_ctx_for_surface call below is the reason why this code (or
rather, this entire function) is here.

Due to some refactoring efforts that rearranged the front-end and
back-end programming sequence, the logic for disabling surfaces for
streams have been moved here. disable_dangling_planes is responsible for
disabling the front end of streams that do not exist in the new dc_state
(i.e. streams that are disabled). See one of the relevant patches here:
https://lists.freedesktop.org/archives/amd-gfx/2017-October/015201.html

This cannot be done in atomic check, because there is currently no
support in DC to explicitly mark a stream or surface as disabled. We
infer it by comparing the current and new dc_states, then call apply_ctx
to program it.

Leo

> 
>> +            dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, 
>> dangling_context);
>> +        }
>> +    }
>> +
>> +    current_ctx = dc->current_state;
>> +    dc->current_state = dangling_context;
>> +    dc_release_state(current_ctx);
>> +}
>> +
>>   
>> /******************************************************************************* 
>>
>>    * Public functions
>>    
>> ******************************************************************************/ 
>>
>> @@ -833,14 +866,14 @@ static enum dc_status 
>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>       int i, k, l;
>>       struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
>> +    disable_dangling_plane(dc, context);
>> +
>>       for (i = 0; i < context->stream_count; i++)
>>           dc_streams[i] =  context->streams[i];
>>       if (!dcb->funcs->is_accelerated_mode(dcb))
>>           dc->hwss.enable_accelerated_mode(dc);
>> -
>> -
>>       for (i = 0; i < context->stream_count; i++) {
>>           const struct dc_sink *sink = context->streams[i]->sink;
>> @@ -864,8 +897,6 @@ static enum dc_status 
>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>               }
>>           }
>> -
>> -
>>           CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
>>                   context->streams[i]->timing.h_addressable,
>>                   context->streams[i]->timing.v_addressable,
> 
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Re: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Andrey Grodzovsky]

On 11/13/2017 04:53 PM, Leo Li wrote:
>
>
> On 2017-11-10 02:00 PM, Andrey Grodzovsky wrote:
>>
>>
>> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>>
>>> When disabling pipe splitting, we need to make sure we disable both
>>> planes used.
>>>
>>> This should be done for Linux as well.
>>>
>>> Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
>>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>>> Acked-by: Harry Wentland <harry.wentland@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/dc/core/dc.c | 39 
>>> ++++++++++++++++++++++++++++----
>>>   1 file changed, 35 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
>>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> index 56df1304e49c..d70dbc102123 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> @@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
>>>       return false;
>>>   }
>>> +static void disable_dangling_plane(struct dc *dc, struct dc_state 
>>> *context)
>>> +{
>>> +    int i, j;
>>> +    struct dc_state *dangling_context = dc_create_state();
>>> +    struct dc_state *current_ctx;
>>> +
>>> +    if (dangling_context == NULL)
>>> +        return;
>>> +
>>> +    dc_resource_state_copy_construct(dc->current_state, 
>>> dangling_context);
>>> +
>>> +    for (i = 0; i < dc->res_pool->pipe_count; i++) {
>>> +        struct dc_stream_state *old_stream =
>>> + dc->current_state->res_ctx.pipe_ctx[i].stream;
>>> +        bool should_disable = true;
>>> +
>>> +        for (j = 0; j < context->stream_count; j++) {
>>> +            if (old_stream == context->streams[j]) {
>>> +                should_disable = false;
>>> +                break;
>>> +            }
>>> +        }
>>> +        if (should_disable && old_stream) {
>>> +            dc_rem_all_planes_for_stream(dc, old_stream, 
>>> dangling_context);
>>
>> Why this is not happening in atomic_check during 
>> dm_update_planes_state with enable set to false ? Since the old 
>> stream is present
>> I assume old crtc_state for planes to disable is present and as I see 
>> from the code it should happen in that function
>>
>> Thanks,
>> Andrey
> You're correct, the above logic should be done in atomic check. However,
> the apply_ctx_for_surface call below is the reason why this code (or
> rather, this entire function) is here.
>
> Due to some refactoring efforts that rearranged the front-end and
> back-end programming sequence, the logic for disabling surfaces for
> streams have been moved here. disable_dangling_planes is responsible for
> disabling the front end of streams that do not exist in the new dc_state
> (i.e. streams that are disabled). See one of the relevant patches here:
> https://lists.freedesktop.org/archives/amd-gfx/2017-October/015201.html
>
> This cannot be done in atomic check, because there is currently no
> support in DC to explicitly mark a stream or surface as disabled. We
> infer it by comparing the current and new dc_states, then call apply_ctx
> to program it.
>
> Leo

I see, at least try to get rid of dangling_context I don't see why 
intermediate state is needed. Adding Tony
and Jonathan, maybe they can explain.
Also please rename  struct dc_state *context in the argument list to 
state, context is obsolete naming.

Thanks,
Andrey

>
>>
>>> + dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
>>> +        }
>>> +    }
>>> +
>>> +    current_ctx = dc->current_state;
>>> +    dc->current_state = dangling_context;
>>> +    dc_release_state(current_ctx);
>>> +}
>>> +
>>> /******************************************************************************* 
>>>
>>>    * Public functions
>>> ******************************************************************************/ 
>>>
>>> @@ -833,14 +866,14 @@ static enum dc_status 
>>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>>       int i, k, l;
>>>       struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
>>> +    disable_dangling_plane(dc, context);
>>> +
>>>       for (i = 0; i < context->stream_count; i++)
>>>           dc_streams[i] =  context->streams[i];
>>>       if (!dcb->funcs->is_accelerated_mode(dcb))
>>>           dc->hwss.enable_accelerated_mode(dc);
>>> -
>>> -
>>>       for (i = 0; i < context->stream_count; i++) {
>>>           const struct dc_sink *sink = context->streams[i]->sink;
>>> @@ -864,8 +897,6 @@ static enum dc_status 
>>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>>               }
>>>           }
>>> -
>>> -
>>>           CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
>>> context->streams[i]->timing.h_addressable,
>>> context->streams[i]->timing.v_addressable,
>>

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RE: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Cheng, Tony]

DC always work off current context.  If we don't swap in a context with plane removed, HWSS will be doing the wrong programming when we enable streams and planes.

-----Original Message-----
From: Grodzovsky, Andrey 
Sent: Tuesday, November 14, 2017 10:08 AM
To: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; amd-gfx@lists.freedesktop.org; Cheng, Tony <Tony.Cheng@amd.com>; Sun, Yongqiang <Yongqiang.Sun@amd.com>
Subject: Re: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state



On 11/13/2017 04:53 PM, Leo Li wrote:
>
>
> On 2017-11-10 02:00 PM, Andrey Grodzovsky wrote:
>>
>>
>> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>>
>>> When disabling pipe splitting, we need to make sure we disable both 
>>> planes used.
>>>
>>> This should be done for Linux as well.
>>>
>>> Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
>>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>>> Acked-by: Harry Wentland <harry.wentland@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/dc/core/dc.c | 39
>>> ++++++++++++++++++++++++++++----
>>>   1 file changed, 35 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> index 56df1304e49c..d70dbc102123 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> @@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
>>>       return false;
>>>   }
>>> +static void disable_dangling_plane(struct dc *dc, struct dc_state
>>> *context)
>>> +{
>>> +    int i, j;
>>> +    struct dc_state *dangling_context = dc_create_state();
>>> +    struct dc_state *current_ctx;
>>> +
>>> +    if (dangling_context == NULL)
>>> +        return;
>>> +
>>> +    dc_resource_state_copy_construct(dc->current_state,
>>> dangling_context);
>>> +
>>> +    for (i = 0; i < dc->res_pool->pipe_count; i++) {
>>> +        struct dc_stream_state *old_stream =
>>> + dc->current_state->res_ctx.pipe_ctx[i].stream;
>>> +        bool should_disable = true;
>>> +
>>> +        for (j = 0; j < context->stream_count; j++) {
>>> +            if (old_stream == context->streams[j]) {
>>> +                should_disable = false;
>>> +                break;
>>> +            }
>>> +        }
>>> +        if (should_disable && old_stream) {
>>> +            dc_rem_all_planes_for_stream(dc, old_stream,
>>> dangling_context);
>>
>> Why this is not happening in atomic_check during 
>> dm_update_planes_state with enable set to false ? Since the old 
>> stream is present I assume old crtc_state for planes to disable is 
>> present and as I see from the code it should happen in that function
>>
>> Thanks,
>> Andrey
> You're correct, the above logic should be done in atomic check. 
> However, the apply_ctx_for_surface call below is the reason why this 
> code (or rather, this entire function) is here.
>
> Due to some refactoring efforts that rearranged the front-end and 
> back-end programming sequence, the logic for disabling surfaces for 
> streams have been moved here. disable_dangling_planes is responsible 
> for disabling the front end of streams that do not exist in the new 
> dc_state (i.e. streams that are disabled). See one of the relevant patches here:
> https://lists.freedesktop.org/archives/amd-gfx/2017-October/015201.htm
> l
>
> This cannot be done in atomic check, because there is currently no 
> support in DC to explicitly mark a stream or surface as disabled. We 
> infer it by comparing the current and new dc_states, then call 
> apply_ctx to program it.
>
> Leo

I see, at least try to get rid of dangling_context I don't see why intermediate state is needed. Adding Tony and Jonathan, maybe they can explain.
Also please rename  struct dc_state *context in the argument list to state, context is obsolete naming.

Thanks,
Andrey

>
>>
>>> + dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, 
>>> + dc->dangling_context);
>>> +        }
>>> +    }
>>> +
>>> +    current_ctx = dc->current_state;
>>> +    dc->current_state = dangling_context;
>>> +    dc_release_state(current_ctx);
>>> +}
>>> +
>>> /*******************************************************************
>>> ************
>>>
>>>    * Public functions
>>> ********************************************************************
>>> **********/
>>>
>>> @@ -833,14 +866,14 @@ static enum dc_status 
>>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>>       int i, k, l;
>>>       struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
>>> +    disable_dangling_plane(dc, context);
>>> +
>>>       for (i = 0; i < context->stream_count; i++)
>>>           dc_streams[i] =  context->streams[i];
>>>       if (!dcb->funcs->is_accelerated_mode(dcb))
>>>           dc->hwss.enable_accelerated_mode(dc);
>>> -
>>> -
>>>       for (i = 0; i < context->stream_count; i++) {
>>>           const struct dc_sink *sink = context->streams[i]->sink; @@ 
>>> -864,8 +897,6 @@ static enum dc_status 
>>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>>               }
>>>           }
>>> -
>>> -
>>>           CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
>>> context->streams[i]->timing.h_addressable,
>>> context->streams[i]->timing.v_addressable,
>>

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Re: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Andrey Grodzovsky]

Ok, got it.

Thanks,
Andrey

On 11/14/2017 10:10 AM, Cheng, Tony wrote:
> DC always work off current context.  If we don't swap in a context with plane removed, HWSS will be doing the wrong programming when we enable streams and planes.
>
> -----Original Message-----
> From: Grodzovsky, Andrey
> Sent: Tuesday, November 14, 2017 10:08 AM
> To: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; amd-gfx@lists.freedesktop.org; Cheng, Tony <Tony.Cheng@amd.com>; Sun, Yongqiang <Yongqiang.Sun@amd.com>
> Subject: Re: [PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state
>
>
>
> On 11/13/2017 04:53 PM, Leo Li wrote:
>>
>> On 2017-11-10 02:00 PM, Andrey Grodzovsky wrote:
>>>
>>> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>>>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>>>
>>>> When disabling pipe splitting, we need to make sure we disable both
>>>> planes used.
>>>>
>>>> This should be done for Linux as well.
>>>>
>>>> Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
>>>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>>>> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>>>> Acked-by: Harry Wentland <harry.wentland@amd.com>
>>>> ---
>>>>    drivers/gpu/drm/amd/display/dc/core/dc.c | 39
>>>> ++++++++++++++++++++++++++++----
>>>>    1 file changed, 35 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> index 56df1304e49c..d70dbc102123 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>> @@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
>>>>        return false;
>>>>    }
>>>> +static void disable_dangling_plane(struct dc *dc, struct dc_state
>>>> *context)
>>>> +{
>>>> +    int i, j;
>>>> +    struct dc_state *dangling_context = dc_create_state();
>>>> +    struct dc_state *current_ctx;
>>>> +
>>>> +    if (dangling_context == NULL)
>>>> +        return;
>>>> +
>>>> +    dc_resource_state_copy_construct(dc->current_state,
>>>> dangling_context);
>>>> +
>>>> +    for (i = 0; i < dc->res_pool->pipe_count; i++) {
>>>> +        struct dc_stream_state *old_stream =
>>>> + dc->current_state->res_ctx.pipe_ctx[i].stream;
>>>> +        bool should_disable = true;
>>>> +
>>>> +        for (j = 0; j < context->stream_count; j++) {
>>>> +            if (old_stream == context->streams[j]) {
>>>> +                should_disable = false;
>>>> +                break;
>>>> +            }
>>>> +        }
>>>> +        if (should_disable && old_stream) {
>>>> +            dc_rem_all_planes_for_stream(dc, old_stream,
>>>> dangling_context);
>>> Why this is not happening in atomic_check during
>>> dm_update_planes_state with enable set to false ? Since the old
>>> stream is present I assume old crtc_state for planes to disable is
>>> present and as I see from the code it should happen in that function
>>>
>>> Thanks,
>>> Andrey
>> You're correct, the above logic should be done in atomic check.
>> However, the apply_ctx_for_surface call below is the reason why this
>> code (or rather, this entire function) is here.
>>
>> Due to some refactoring efforts that rearranged the front-end and
>> back-end programming sequence, the logic for disabling surfaces for
>> streams have been moved here. disable_dangling_planes is responsible
>> for disabling the front end of streams that do not exist in the new
>> dc_state (i.e. streams that are disabled). See one of the relevant patches here:
>> https://lists.freedesktop.org/archives/amd-gfx/2017-October/015201.htm
>> l
>>
>> This cannot be done in atomic check, because there is currently no
>> support in DC to explicitly mark a stream or surface as disabled. We
>> infer it by comparing the current and new dc_states, then call
>> apply_ctx to program it.
>>
>> Leo
> I see, at least try to get rid of dangling_context I don't see why intermediate state is needed. Adding Tony and Jonathan, maybe they can explain.
> Also please rename  struct dc_state *context in the argument list to state, context is obsolete naming.
>
> Thanks,
> Andrey
>
>>>> + dc->hwss.apply_ctx_for_surface(dc, old_stream, 0,
>>>> + dc->dangling_context);
>>>> +        }
>>>> +    }
>>>> +
>>>> +    current_ctx = dc->current_state;
>>>> +    dc->current_state = dangling_context;
>>>> +    dc_release_state(current_ctx);
>>>> +}
>>>> +
>>>> /*******************************************************************
>>>> ************
>>>>
>>>>     * Public functions
>>>> ********************************************************************
>>>> **********/
>>>>
>>>> @@ -833,14 +866,14 @@ static enum dc_status
>>>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>>>        int i, k, l;
>>>>        struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
>>>> +    disable_dangling_plane(dc, context);
>>>> +
>>>>        for (i = 0; i < context->stream_count; i++)
>>>>            dc_streams[i] =  context->streams[i];
>>>>        if (!dcb->funcs->is_accelerated_mode(dcb))
>>>>            dc->hwss.enable_accelerated_mode(dc);
>>>> -
>>>> -
>>>>        for (i = 0; i < context->stream_count; i++) {
>>>>            const struct dc_sink *sink = context->streams[i]->sink; @@
>>>> -864,8 +897,6 @@ static enum dc_status
>>>> dc_commit_state_no_check(struct dc *dc, struct dc_state *c
>>>>                }
>>>>            }
>>>> -
>>>> -
>>>>            CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
>>>> context->streams[i]->timing.h_addressable,
>>>> context->streams[i]->timing.v_addressable,

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Re: [PATCH 38/73] drm/amd/display: Fix warnings on S3 resume

[Leo Li]

On 2017-11-10 01:40 PM, Andrey Grodzovsky wrote:
> 
> 
> On 11/10/2017 01:38 PM, Andrey Grodzovsky wrote:
>>
>>
>> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>>
>>> This is a followup to the following revert:
>>>
>>> Rex Zhu    Revert "drm/amd/display: Match actual state during S3
>>>             resume."
>>>
>>> Three things needed to be addressed:
>>>
>>> 1. Potential memory leak on dc_state creation in atomic_check during
>>>     s3 resume
>>> 2. Warnings are now seen in dmesg during S3 resume
>>> 3. Since dc_state is now created in atomic_check, what the reverted
>>>     patch was addressing needs to be reevaluated.
>>>
>>> This change addresses the above:
>>>
>>> 1. Since the suspend procedure calls drm_atomic_state_clear, our hook
>>>     for releasing the dc_state is called. This frees it before
>>>     atomic_check creates it during resume. The leak does not occur.
>>>
>>> 2. The dc_crtc/plane_state references kept by the atomic states need to
>>>     be released before calling atomic_check, which warns if they are
>>>     non-null. This is because atomic_check is responsible for creating
>>>     the dc_*_states. This is a special case for S3 resume, since the
>>>     atomic state duplication that occurs during suspend also copies a
>>>     reference to the dc_*_states.
>>>
>>> 3. See 2. comments are also updated to reflect this.
>>>
>>> Change-Id: I6e342bf8134f0e5dc32888a8d894c2cd20d28296
>>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>>> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 
>>> +++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> index 1c7f22146bc9..bdef1ed0dfac 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> @@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct 
>>> amdgpu_device *adev)
>>>       struct drm_connector *connector;
>>>       struct drm_crtc *crtc;
>>>       struct drm_crtc_state *new_crtc_state;
>>> +    struct dm_crtc_state *dm_new_crtc_state;
>>> +    struct drm_plane *plane;
>>> +    struct drm_plane_state *new_plane_state;
>>> +    struct dm_plane_state *dm_new_plane_state;
>>> +
>>>       int ret = 0;
>>>       int i;
>>>   @@ -685,6 +690,29 @@ int amdgpu_dm_display_resume(struct 
>>> amdgpu_device *adev)
>>>       for_each_new_crtc_in_state(adev->dm.cached_state, crtc, 
>>> new_crtc_state, i)
>>>           new_crtc_state->active_changed = true;
>>>   +    /*
>>> +     * atomic_check is expected to create the dc states. We need to 
>>> release
>>> +     * them here, since they were duplicated as part of the suspend
>>> +     * procedure.
>>> +     */
>>> +    for_each_new_crtc_in_state(adev->dm.cached_state, crtc, 
>>> new_crtc_state, i) {
>>> +        dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
>>> +        if (dm_new_crtc_state->stream) {
>>> + WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
>>> +            dc_stream_release(dm_new_crtc_state->stream);
>>> +            dm_new_crtc_state->stream = NULL;
>>> +        }
>>> +    }
>>> +
>>> +    for_each_new_plane_in_state(adev->dm.cached_state, plane, 
>>> new_plane_state, i) {
>>> +        dm_new_plane_state = to_dm_plane_state(new_plane_state);
>>> +        if (dm_new_plane_state->dc_state) {
>>> + WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
>>> + dc_plane_state_release(dm_new_plane_state->dc_state);
>>> +            dm_new_plane_state->dc_state = NULL;
>>> +        }
>>> +    }
>>
>> I guess the warnings you are referring to are in dm_update_crtcs_state 
>> and dm_update_planes_state,
>> but I don't understand why you need to explicitly release them in 
>> amdgpu_dm_resume, any changed
>> plane/crtc states will be removed during atomic check anyway and only 
>> after that new one will be added,
>> I find strange that this doesn't work.
>>
>> P.S I tried to reproduce this to see the warnings with latest 
>> amd-staging-drm-next (776fb8c)on CZ but the system becomes
>> unimpressive after going to suspend, might wanna check this on your side.
> 
> UNRESPONSIVE (it's unimpressive in any case :) )
> 
> Andrey
> 

It's just a special case for s3 resume. The suspend helper first 
duplicates the existing atomic state (which in turn, duplicates 
references to dc states), then calls the disable_all helper. This means 
that during resume, the old state will have everything disabled, while 
the new state is the duplicated state that we're trying to restore.

Our atomic check isn't very happy with this. From it's perspective, 
we're clearly trying to enable a CRTC. It doesn't expect the new 
drm_*_states to have associated dc_*_states yet. This is why the 
releases are necessary within amdgpu_dm_resume; to make things 
consistent for atomic_check.

Leo

>>
>> Thanks,
>> Andrey
>>
>>> +
>>>       ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
>>>         drm_atomic_state_put(adev->dm.cached_state);
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
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Re: [PATCH 38/73] drm/amd/display: Fix warnings on S3 resume

[Andrey Grodzovsky]

On 11/14/2017 11:00 AM, Leo Li wrote:
>
>
> On 2017-11-10 01:40 PM, Andrey Grodzovsky wrote:
>>
>>
>> On 11/10/2017 01:38 PM, Andrey Grodzovsky wrote:
>>>
>>>
>>> On 11/09/2017 03:05 PM, Harry Wentland wrote:
>>>> From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
>>>>
>>>> This is a followup to the following revert:
>>>>
>>>> Rex Zhu    Revert "drm/amd/display: Match actual state during S3
>>>>             resume."
>>>>
>>>> Three things needed to be addressed:
>>>>
>>>> 1. Potential memory leak on dc_state creation in atomic_check during
>>>>     s3 resume
>>>> 2. Warnings are now seen in dmesg during S3 resume
>>>> 3. Since dc_state is now created in atomic_check, what the reverted
>>>>     patch was addressing needs to be reevaluated.
>>>>
>>>> This change addresses the above:
>>>>
>>>> 1. Since the suspend procedure calls drm_atomic_state_clear, our hook
>>>>     for releasing the dc_state is called. This frees it before
>>>>     atomic_check creates it during resume. The leak does not occur.
>>>>
>>>> 2. The dc_crtc/plane_state references kept by the atomic states 
>>>> need to
>>>>     be released before calling atomic_check, which warns if they are
>>>>     non-null. This is because atomic_check is responsible for creating
>>>>     the dc_*_states. This is a special case for S3 resume, since the
>>>>     atomic state duplication that occurs during suspend also copies a
>>>>     reference to the dc_*_states.
>>>>
>>>> 3. See 2. comments are also updated to reflect this.
>>>>
>>>> Change-Id: I6e342bf8134f0e5dc32888a8d894c2cd20d28296
>>>> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
>>>> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 
>>>> +++++++++++++++++++++++
>>>>   1 file changed, 28 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> index 1c7f22146bc9..bdef1ed0dfac 100644
>>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> @@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct 
>>>> amdgpu_device *adev)
>>>>       struct drm_connector *connector;
>>>>       struct drm_crtc *crtc;
>>>>       struct drm_crtc_state *new_crtc_state;
>>>> +    struct dm_crtc_state *dm_new_crtc_state;
>>>> +    struct drm_plane *plane;
>>>> +    struct drm_plane_state *new_plane_state;
>>>> +    struct dm_plane_state *dm_new_plane_state;
>>>> +
>>>>       int ret = 0;
>>>>       int i;
>>>>   @@ -685,6 +690,29 @@ int amdgpu_dm_display_resume(struct 
>>>> amdgpu_device *adev)
>>>>       for_each_new_crtc_in_state(adev->dm.cached_state, crtc, 
>>>> new_crtc_state, i)
>>>>           new_crtc_state->active_changed = true;
>>>>   +    /*
>>>> +     * atomic_check is expected to create the dc states. We need 
>>>> to release
>>>> +     * them here, since they were duplicated as part of the suspend
>>>> +     * procedure.
>>>> +     */
>>>> +    for_each_new_crtc_in_state(adev->dm.cached_state, crtc, 
>>>> new_crtc_state, i) {
>>>> +        dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
>>>> +        if (dm_new_crtc_state->stream) {
>>>> + WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
>>>> + dc_stream_release(dm_new_crtc_state->stream);
>>>> +            dm_new_crtc_state->stream = NULL;
>>>> +        }
>>>> +    }
>>>> +
>>>> +    for_each_new_plane_in_state(adev->dm.cached_state, plane, 
>>>> new_plane_state, i) {
>>>> +        dm_new_plane_state = to_dm_plane_state(new_plane_state);
>>>> +        if (dm_new_plane_state->dc_state) {
>>>> + WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
>>>> + dc_plane_state_release(dm_new_plane_state->dc_state);
>>>> +            dm_new_plane_state->dc_state = NULL;
>>>> +        }
>>>> +    }
>>>
>>> I guess the warnings you are referring to are in 
>>> dm_update_crtcs_state and dm_update_planes_state,
>>> but I don't understand why you need to explicitly release them in 
>>> amdgpu_dm_resume, any changed
>>> plane/crtc states will be removed during atomic check anyway and 
>>> only after that new one will be added,
>>> I find strange that this doesn't work.
>>>
>>> P.S I tried to reproduce this to see the warnings with latest 
>>> amd-staging-drm-next (776fb8c)on CZ but the system becomes
>>> unimpressive after going to suspend, might wanna check this on your 
>>> side.
>>
>> UNRESPONSIVE (it's unimpressive in any case :) )
>>
>> Andrey
>>
>
> It's just a special case for s3 resume. The suspend helper first 
> duplicates the existing atomic state (which in turn, duplicates 
> references to dc states), then calls the disable_all helper. This 
> means that during resume, the old state will have everything disabled, 
> while the new state is the duplicated state that we're trying to restore.
>
> Our atomic check isn't very happy with this. From it's perspective, 
> we're clearly trying to enable a CRTC. It doesn't expect the new 
> drm_*_states to have associated dc_*_states yet. This is why the 
> releases are necessary within amdgpu_dm_resume; to make things 
> consistent for atomic_check.
>
> Leo

I see, this change Reviewed-by: Andrey Grodzovsky 
<andrey.grodzovsky@amd.com>

Thanks,
Andrey
>
>>>
>>> Thanks,
>>> Andrey
>>>
>>>> +
>>>>       ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
>>>>         drm_atomic_state_put(adev->dm.cached_state);
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>

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