* [PATCH] drm/i915: There is only one fault register from GEN8 onwards
@ 2017-11-10 19:01 Michel Thierry
2017-11-10 19:22 ` ✓ Fi.CI.BAT: success for drm/i915: There is only one fault register from Gen8 onwards (rev3) Patchwork
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Michel Thierry @ 2017-11-10 19:01 UTC (permalink / raw)
To: intel-gfx
Until Haswell/Baytrail, the hardware used to have a per engine fault
register (e.g. 0x4094 - render fault register, 0x4194 - media fault
register and so on). But since Broadwell, all these registers were
combined into a singe one and the engine id stored in bits 14:12.
Not only we should not been reading (and writing to) registers that do
not exist, in platforms with VCS2 (SKL), the address that would belong
this engine (0x4494, VCS2_HW = 4) is already assigned to other register.
References: IHD-OS-BDW-Vol 2c-11.15, page 75.
References: IHD-OS-SKL-Vol 2c-05.16, page 350.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1e40eeb31f9d..66a907330ad2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2256,16 +2256,13 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
}
-void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
+void __check_and_clear_faults(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
-
- if (INTEL_INFO(dev_priv)->gen < 6)
- return;
+ u32 fault_reg;
for_each_engine(engine, dev_priv, id) {
- u32 fault_reg;
fault_reg = I915_READ(RING_FAULT_REG(engine));
if (fault_reg & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
@@ -2281,6 +2278,37 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
fault_reg & ~RING_FAULT_VALID);
}
}
+}
+
+void __gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
+{
+ u32 fault_reg = I915_READ(GEN8_RING_FAULT_REG);
+
+ if (fault_reg & RING_FAULT_VALID) {
+ DRM_DEBUG_DRIVER("Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault_reg & PAGE_MASK,
+ GEN8_RING_FAULT_ENGINE_ID(fault_reg),
+ RING_FAULT_SRCID(fault_reg),
+ RING_FAULT_FAULT_TYPE(fault_reg));
+ I915_WRITE(GEN8_RING_FAULT_REG,
+ fault_reg & ~RING_FAULT_VALID);
+ }
+}
+
+void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_GEN(dev_priv) < 6)
+ return;
+
+ /* From GEN8 onwards we only have one 'All Engine Fault Register' */
+ if (INTEL_GEN(dev_priv) >= 8)
+ __gen8_check_and_clear_faults(dev_priv);
+ else
+ __check_and_clear_faults(dev_priv);
/* Engine specific init may not have been done till this point. */
if (dev_priv->engine[RCS])
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5c2d83a838d8..7481c8e1b5a8 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1217,11 +1217,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 6) {
ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
- ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
- if (INTEL_GEN(dev_priv) >= 8)
+ if (INTEL_GEN(dev_priv) >= 8) {
gen8_record_semaphore_state(error, engine, ee);
- else
+ ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
+ } else {
gen6_record_semaphore_state(engine, ee);
+ ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+ }
}
if (INTEL_GEN(dev_priv) >= 4) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ef33422f762..7ef82ba670e9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2329,6 +2329,8 @@ enum i915_power_well_id {
#define ARB_MODE_SWIZZLE_BDW (1<<1)
#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
+#define GEN8_RING_FAULT_REG _MMIO(0x4094)
+#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1<<11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
--
2.15.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: There is only one fault register from Gen8 onwards (rev3)
2017-11-10 19:01 [PATCH] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry
@ 2017-11-10 19:22 ` Patchwork
2017-11-10 20:24 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-10 20:51 ` [PATCH] drm/i915: There is only one fault register from GEN8 onwards Chris Wilson
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-11-10 19:22 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: There is only one fault register from Gen8 onwards (rev3)
URL : https://patchwork.freedesktop.org/series/26317/
State : success
== Summary ==
Series 26317v3 drm/i915: There is only one fault register from Gen8 onwards
https://patchwork.freedesktop.org/api/1.0/series/26317/revisions/3/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-fail -> PASS (fi-kbl-7560u) fdo#103039
Subgroup basic-s4-devices:
dmesg-fail -> PASS (fi-kbl-7560u) fdo#102846 +1
Test gem_flink_basic:
Subgroup bad-flink:
dmesg-warn -> PASS (fi-kbl-7560u) fdo#103049 +4
Test gem_linear_blits:
Subgroup basic:
incomplete -> PASS (fi-kbl-7560u) fdo#103163
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail -> PASS (fi-gdg-551) fdo#102618
fdo#103039 https://bugs.freedesktop.org/show_bug.cgi?id=103039
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846
fdo#103049 https://bugs.freedesktop.org/show_bug.cgi?id=103049
fdo#103163 https://bugs.freedesktop.org/show_bug.cgi?id=103163
fdo#102618 https://bugs.freedesktop.org/show_bug.cgi?id=102618
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:456s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:382s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:548s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:274s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:497s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:489s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:428s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:263s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:544s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:436s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:443s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:430s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:474s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:489s
fi-kbl-7560u total:247 pass:230 dwarn:0 dfail:0 fail:0 skip:16
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:476s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:544s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:568s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:549s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:566s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:523s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:503s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:565s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:425s
Blacklisted hosts:
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:546s
fi-glk-dsi total:62 pass:45 dwarn:0 dfail:0 fail:0 skip:16
fi-bxt-dsi failed to connect after reboot
6f3dca38f7a939db9658bd11d9c37357089cabef drm-tip: 2017y-11m-10d-12h-56m-44s UTC integration manifest
bf772f904fe3 drm/i915: There is only one fault register from GEN8 onwards
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7067/
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^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: There is only one fault register from Gen8 onwards (rev3)
2017-11-10 19:01 [PATCH] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry
2017-11-10 19:22 ` ✓ Fi.CI.BAT: success for drm/i915: There is only one fault register from Gen8 onwards (rev3) Patchwork
@ 2017-11-10 20:24 ` Patchwork
2017-11-10 20:51 ` [PATCH] drm/i915: There is only one fault register from GEN8 onwards Chris Wilson
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-11-10 20:24 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: There is only one fault register from Gen8 onwards (rev3)
URL : https://patchwork.freedesktop.org/series/26317/
State : success
== Summary ==
Test kms_flip:
Subgroup modeset-vs-vblank-race-interruptible:
fail -> PASS (shard-hsw) fdo#103060
Subgroup plain-flip-ts-check-interruptible:
pass -> FAIL (shard-hsw) fdo#100368
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
Test kms_frontbuffer_tracking:
Subgroup fbc-farfromfence:
skip -> PASS (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-a:
pass -> DMESG-WARN (shard-hsw) fdo#102249
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
shard-hsw total:2584 pass:1471 dwarn:2 dfail:1 fail:11 skip:1099 time:9454s
Blacklisted hosts:
shard-apl total:2584 pass:1620 dwarn:4 dfail:1 fail:23 skip:936 time:13241s
shard-kbl total:2556 pass:1688 dwarn:17 dfail:1 fail:23 skip:825 time:9926s
shard-snb total:2584 pass:1211 dwarn:2 dfail:1 fail:12 skip:1358 time:7801s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7067/shards.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915: There is only one fault register from GEN8 onwards
2017-11-10 19:01 [PATCH] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry
2017-11-10 19:22 ` ✓ Fi.CI.BAT: success for drm/i915: There is only one fault register from Gen8 onwards (rev3) Patchwork
2017-11-10 20:24 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-11-10 20:51 ` Chris Wilson
2017-11-10 23:42 ` Michel Thierry
2 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2017-11-10 20:51 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
Quoting Michel Thierry (2017-11-10 19:01:16)
> Until Haswell/Baytrail, the hardware used to have a per engine fault
> register (e.g. 0x4094 - render fault register, 0x4194 - media fault
> register and so on). But since Broadwell, all these registers were
> combined into a singe one and the engine id stored in bits 14:12.
>
> Not only we should not been reading (and writing to) registers that do
> not exist, in platforms with VCS2 (SKL), the address that would belong
> this engine (0x4494, VCS2_HW = 4) is already assigned to other register.
>
> References: IHD-OS-BDW-Vol 2c-11.15, page 75.
> References: IHD-OS-SKL-Vol 2c-05.16, page 350.
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 3 files changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1e40eeb31f9d..66a907330ad2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2256,16 +2256,13 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
> return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
> }
>
> -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
> +void __check_and_clear_faults(struct drm_i915_private *dev_priv)
I am amazed that -Wextra doesn't complain. Try with sparse.
There's an old thread where this was raised and how we are not clearing
the faults early enough.
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915: There is only one fault register from GEN8 onwards
2017-11-10 20:51 ` [PATCH] drm/i915: There is only one fault register from GEN8 onwards Chris Wilson
@ 2017-11-10 23:42 ` Michel Thierry
2017-11-10 23:50 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Michel Thierry @ 2017-11-10 23:42 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 11/10/2017 12:51 PM, Chris Wilson wrote:
> Quoting Michel Thierry (2017-11-10 19:01:16)
>> Until Haswell/Baytrail, the hardware used to have a per engine fault
>> register (e.g. 0x4094 - render fault register, 0x4194 - media fault
>> register and so on). But since Broadwell, all these registers were
>> combined into a singe one and the engine id stored in bits 14:12.
>>
>> Not only we should not been reading (and writing to) registers that do
>> not exist, in platforms with VCS2 (SKL), the address that would belong
>> this engine (0x4494, VCS2_HW = 4) is already assigned to other register.
>>
>> References: IHD-OS-BDW-Vol 2c-11.15, page 75.
>> References: IHD-OS-SKL-Vol 2c-05.16, page 350.
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> 3 files changed, 40 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 1e40eeb31f9d..66a907330ad2 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2256,16 +2256,13 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
>> return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
>> }
>>
>> -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>> +void __check_and_clear_faults(struct drm_i915_private *dev_priv)
>
> I am amazed that -Wextra doesn't complain. Try with sparse.
>
Hmm, no they didn't... gen6_check_and_clear_faults and
gen8_check_and_clear_faults are less controversial.
> There's an old thread where this was raised and how we are not clearing
> the faults early enough.
Ah, I found that thread [1], and as you said there, right now the
for_each_engine is a nop (with this patch at least gen8+ would do the
right thing).
Since gen6/gen7 engines are well known and can't change, do we really
need for_each_engine?
[1] https://patchwork.freedesktop.org/patch/101331/
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915: There is only one fault register from GEN8 onwards
2017-11-10 23:42 ` Michel Thierry
@ 2017-11-10 23:50 ` Chris Wilson
2017-11-11 0:15 ` Michel Thierry
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2017-11-10 23:50 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
Quoting Michel Thierry (2017-11-10 23:42:31)
> On 11/10/2017 12:51 PM, Chris Wilson wrote:
> > Quoting Michel Thierry (2017-11-10 19:01:16)
> >> Until Haswell/Baytrail, the hardware used to have a per engine fault
> >> register (e.g. 0x4094 - render fault register, 0x4194 - media fault
> >> register and so on). But since Broadwell, all these registers were
> >> combined into a singe one and the engine id stored in bits 14:12.
> >>
> >> Not only we should not been reading (and writing to) registers that do
> >> not exist, in platforms with VCS2 (SKL), the address that would belong
> >> this engine (0x4494, VCS2_HW = 4) is already assigned to other register.
> >>
> >> References: IHD-OS-BDW-Vol 2c-11.15, page 75.
> >> References: IHD-OS-SKL-Vol 2c-05.16, page 350.
> >> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++++++++++++++-----
> >> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
> >> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> >> 3 files changed, 40 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> index 1e40eeb31f9d..66a907330ad2 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> @@ -2256,16 +2256,13 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
> >> return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
> >> }
> >>
> >> -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
> >> +void __check_and_clear_faults(struct drm_i915_private *dev_priv)
> >
> > I am amazed that -Wextra doesn't complain. Try with sparse.
> >
>
> Hmm, no they didn't... gen6_check_and_clear_faults and
> gen8_check_and_clear_faults are less controversial.
The missing static and lack of extern declaration. I know sparse catches
it, I guess for K&R the order is just right for it not to complain.
> > There's an old thread where this was raised and how we are not clearing
> > the faults early enough.
>
> Ah, I found that thread [1], and as you said there, right now the
> for_each_engine is a nop (with this patch at least gen8+ would do the
> right thing).
>
> Since gen6/gen7 engines are well known and can't change, do we really
> need for_each_engine?
For consistency, yeah it would be nice to keep for_each_engine. We should
be ok to do the clear around i915_driver_init_mmio (it's mmio, it has to
be there ;), maybe worth pulling it into intel_engines_init_mmio() or
i915_gem_init_mmio(). I'm learning towards sanitization from within
intel_engines_init_mmio()
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915: There is only one fault register from GEN8 onwards
2017-11-10 23:50 ` Chris Wilson
@ 2017-11-11 0:15 ` Michel Thierry
0 siblings, 0 replies; 10+ messages in thread
From: Michel Thierry @ 2017-11-11 0:15 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 11/10/2017 3:50 PM, Chris Wilson wrote:
> Quoting Michel Thierry (2017-11-10 23:42:31)
>> On 11/10/2017 12:51 PM, Chris Wilson wrote:
>>> Quoting Michel Thierry (2017-11-10 19:01:16)
>>>> Until Haswell/Baytrail, the hardware used to have a per engine fault
>>>> register (e.g. 0x4094 - render fault register, 0x4194 - media fault
>>>> register and so on). But since Broadwell, all these registers were
>>>> combined into a singe one and the engine id stored in bits 14:12.
>>>>
>>>> Not only we should not been reading (and writing to) registers that do
>>>> not exist, in platforms with VCS2 (SKL), the address that would belong
>>>> this engine (0x4494, VCS2_HW = 4) is already assigned to other register.
>>>>
>>>> References: IHD-OS-BDW-Vol 2c-11.15, page 75.
>>>> References: IHD-OS-SKL-Vol 2c-05.16, page 350.
>>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++++++++++++++-----
>>>> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
>>>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>>>> 3 files changed, 40 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>>> index 1e40eeb31f9d..66a907330ad2 100644
>>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>>> @@ -2256,16 +2256,13 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
>>>> return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
>>>> }
>>>>
>>>> -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>>>> +void __check_and_clear_faults(struct drm_i915_private *dev_priv)
>>>
>>> I am amazed that -Wextra doesn't complain. Try with sparse.
>>>
>>
>> Hmm, no they didn't... gen6_check_and_clear_faults and
>> gen8_check_and_clear_faults are less controversial.
>
> The missing static and lack of extern declaration. I know sparse catches
> it, I guess for K&R the order is just right for it not to complain.
>
>>> There's an old thread where this was raised and how we are not clearing
>>> the faults early enough.
>>
>> Ah, I found that thread [1], and as you said there, right now the
>> for_each_engine is a nop (with this patch at least gen8+ would do the
>> right thing).
>>
>> Since gen6/gen7 engines are well known and can't change, do we really
>> need for_each_engine?
>
> For consistency, yeah it would be nice to keep for_each_engine. We should
> be ok to do the clear around i915_driver_init_mmio (it's mmio, it has to
> be there ;), maybe worth pulling it into intel_engines_init_mmio() or
> i915_gem_init_mmio(). I'm learning towards sanitization from within
> intel_engines_init_mmio()
Ok, I'll move the check_and_clear_faults from intel_uncore_init to
intel_engines_init_mmio (that's the one checking at driver load time).
Thanks,
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915: There is only one fault register from Gen8 onwards
2017-06-23 23:35 ` Chris Wilson
@ 2017-06-23 23:43 ` Michel Thierry
0 siblings, 0 replies; 10+ messages in thread
From: Michel Thierry @ 2017-06-23 23:43 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 23/06/17 16:35, Chris Wilson wrote:
> Quoting Michel Thierry (2017-06-24 00:17:29)
>> Until Haswell/Baytrail, the hardware used to have a per engine fault
>> register (e.g. 0x4094 - render fault register, 0x4194 - media fault
>> register, etc). But since Broadwell, all these registers were combined
>> into a singe one, which specifies the engine id in bits 14:12.
>>
>> Luckily, the additional register addresses haven't been reused, but we
>> should not been reading (and writing to) registers that do not exist.
>>
>> References: IHD-OS-BDW-Vol 2c-11.15, page 75.
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++++++++++++++-----
>> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> 3 files changed, 31 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index de67084d5fcf..83deb004368c 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2000,22 +2000,41 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>> if (INTEL_INFO(dev_priv)->gen < 6)
>> return;
>>
>> - for_each_engine(engine, dev_priv, id) {
>> + /* From GEN8 onwards we only have one 'All Engine Fault Register' */
>> + if (INTEL_INFO(dev_priv)->gen >= 8) {
> INTEL_GEN() >= 8
>
Oops, busted copy-pasting old code, I'll also change it
(INTEL_INFO(dev_priv)->gen < 6).
>> u32 fault_reg;
>
> Newline after variable blocks (might as well fix up the coding style in
> passing).
>
> u32 fault;
>
> foo_reg is more commonly used to refer to the register offset itself,
> i.e. i915_reg_t. Might as well move it to the start of the function as
> it is shared between all branches, and I don't think we are overly
> concerned with aiding gcc's liverange analysis here.
I thought about moving it to the start of the function. Let me make
these changes.
Thanks,
-Michel
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915: There is only one fault register from Gen8 onwards
2017-06-23 23:17 [PATCH] drm/i915: There is only one fault register from Gen8 onwards Michel Thierry
@ 2017-06-23 23:35 ` Chris Wilson
2017-06-23 23:43 ` Michel Thierry
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2017-06-23 23:35 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
Quoting Michel Thierry (2017-06-24 00:17:29)
> Until Haswell/Baytrail, the hardware used to have a per engine fault
> register (e.g. 0x4094 - render fault register, 0x4194 - media fault
> register, etc). But since Broadwell, all these registers were combined
> into a singe one, which specifies the engine id in bits 14:12.
>
> Luckily, the additional register addresses haven't been reused, but we
> should not been reading (and writing to) registers that do not exist.
>
> References: IHD-OS-BDW-Vol 2c-11.15, page 75.
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 3 files changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index de67084d5fcf..83deb004368c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2000,22 +2000,41 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
> if (INTEL_INFO(dev_priv)->gen < 6)
> return;
>
> - for_each_engine(engine, dev_priv, id) {
> + /* From GEN8 onwards we only have one 'All Engine Fault Register' */
> + if (INTEL_INFO(dev_priv)->gen >= 8) {
INTEL_GEN() >= 8
> u32 fault_reg;
Newline after variable blocks (might as well fix up the coding style in
passing).
u32 fault;
foo_reg is more commonly used to refer to the register offset itself,
i.e. i915_reg_t. Might as well move it to the start of the function as
it is shared between all branches, and I don't think we are overly
concerned with aiding gcc's liverange analysis here.
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] drm/i915: There is only one fault register from Gen8 onwards
@ 2017-06-23 23:17 Michel Thierry
2017-06-23 23:35 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Michel Thierry @ 2017-06-23 23:17 UTC (permalink / raw)
To: intel-gfx
Until Haswell/Baytrail, the hardware used to have a per engine fault
register (e.g. 0x4094 - render fault register, 0x4194 - media fault
register, etc). But since Broadwell, all these registers were combined
into a singe one, which specifies the engine id in bits 14:12.
Luckily, the additional register addresses haven't been reused, but we
should not been reading (and writing to) registers that do not exist.
References: IHD-OS-BDW-Vol 2c-11.15, page 75.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index de67084d5fcf..83deb004368c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2000,22 +2000,41 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
if (INTEL_INFO(dev_priv)->gen < 6)
return;
- for_each_engine(engine, dev_priv, id) {
+ /* From GEN8 onwards we only have one 'All Engine Fault Register' */
+ if (INTEL_INFO(dev_priv)->gen >= 8) {
u32 fault_reg;
- fault_reg = I915_READ(RING_FAULT_REG(engine));
+ fault_reg = I915_READ(GEN8_RING_FAULT_REG);
if (fault_reg & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
"\tAddr: 0x%08lx\n"
- "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
"\tSource ID: %d\n"
"\tType: %d\n",
fault_reg & PAGE_MASK,
- fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault_reg),
RING_FAULT_SRCID(fault_reg),
RING_FAULT_FAULT_TYPE(fault_reg));
- I915_WRITE(RING_FAULT_REG(engine),
+ I915_WRITE(GEN8_RING_FAULT_REG,
fault_reg & ~RING_FAULT_VALID);
}
+ } else {
+ for_each_engine(engine, dev_priv, id) {
+ u32 fault_reg;
+ fault_reg = I915_READ(RING_FAULT_REG(engine));
+ if (fault_reg & RING_FAULT_VALID) {
+ DRM_DEBUG_DRIVER("Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault_reg & PAGE_MASK,
+ fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+ RING_FAULT_SRCID(fault_reg),
+ RING_FAULT_FAULT_TYPE(fault_reg));
+ I915_WRITE(RING_FAULT_REG(engine),
+ fault_reg & ~RING_FAULT_VALID);
+ }
+ }
}
/* Engine specific init may not have been done till this point. */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index ae70283470a6..b7f147b1b6dd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1167,11 +1167,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 6) {
ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
- ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
- if (INTEL_GEN(dev_priv) >= 8)
+ if (INTEL_GEN(dev_priv) >= 8) {
gen8_record_semaphore_state(error, engine, ee);
- else
+ ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
+ } else {
gen6_record_semaphore_state(engine, ee);
+ ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+ }
}
if (INTEL_GEN(dev_priv) >= 4) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8647cfa81ba..54a828aad777 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2149,6 +2149,8 @@ enum skl_disp_power_wells {
#define ARB_MODE_SWIZZLE_BDW (1<<1)
#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
+#define GEN8_RING_FAULT_REG _MMIO(0x4094)
+#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1<<11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
--
2.11.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-11-11 0:15 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-10 19:01 [PATCH] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry
2017-11-10 19:22 ` ✓ Fi.CI.BAT: success for drm/i915: There is only one fault register from Gen8 onwards (rev3) Patchwork
2017-11-10 20:24 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-10 20:51 ` [PATCH] drm/i915: There is only one fault register from GEN8 onwards Chris Wilson
2017-11-10 23:42 ` Michel Thierry
2017-11-10 23:50 ` Chris Wilson
2017-11-11 0:15 ` Michel Thierry
-- strict thread matches above, loose matches on Subject: below --
2017-06-23 23:17 [PATCH] drm/i915: There is only one fault register from Gen8 onwards Michel Thierry
2017-06-23 23:35 ` Chris Wilson
2017-06-23 23:43 ` Michel Thierry
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