All of lore.kernel.org
 help / color / mirror / Atom feed
From: Cornelia Huck <cohuck@redhat.com>
To: Pierre Morel <pmorel@linux.vnet.ibm.com>
Cc: Yi Min Zhao <zyimin@linux.vnet.ibm.com>,
	qemu-devel@nongnu.org, agraf@suse.de, borntraeger@de.ibm.com,
	pasic@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH 6/7] s390x/pci: move the memory region write from pcistg
Date: Mon, 13 Nov 2017 12:54:56 +0100	[thread overview]
Message-ID: <20171113125456.2c7fc9d2.cohuck@redhat.com> (raw)
In-Reply-To: <8a33e51f-ab4e-bd07-a998-d19897cdd87e@linux.vnet.ibm.com>

On Mon, 13 Nov 2017 10:39:50 +0100
Pierre Morel <pmorel@linux.vnet.ibm.com> wrote:

> On 10/11/2017 10:51, Cornelia Huck wrote:
> > On Fri, 10 Nov 2017 17:40:12 +0800
> > Yi Min Zhao <zyimin@linux.vnet.ibm.com> wrote:
> >   
> >> 在 2017/11/10 上午3:23, Cornelia Huck 写道:  
> >>> On Tue,  7 Nov 2017 18:24:38 +0100
> >>> Pierre Morel <pmorel@linux.vnet.ibm.com> wrote:
> >>>     
> >>>> Let's move the memory region write from pcistg into a dedicated
> >>>> function.
> >>>> This allows us to prepare a later patch searching for subregions
> >>>> inside of the memory region.  
> >>> OK, so here is the memory region write. Do we have any sleeping
> >>> endianness bugs in there for when we wire up tcg? I'm not sure how this
> >>> plays with the bswaps (see patch 1).
> >>>
> >>> But maybe I've just gotten lost somewhere.  
> >> I think there's no error. For PCI bars' MRs, we got the little-endian data
> >> that is exactly fit to the byte ordering of pcilg instruction. For PCI
> >> config
> >> space, the data has been swapped according to the cpu byte ordering.  
> > 
> > Host or target cpu?
> >   
> >> So we use zpci_swap_endian() to swap the data back to the little-endian
> >> ordering.  
> >   
> 
> 
> I do not see where we use the zpci_swap_endian() function in this patch 
> or in the zpci_write_bar() function.

So, is that swap function only ever used to convert BE register
contents to LE?

> 
> 
> 
> > That swap is unconditional. If we were running on a little-endian host,
> > it would be wrong, wouldn't it?  
> 
> I think there is no problem here, we do not use the swap function but we 
> use the memory_region_dispatch_write() to access a subregion of the PCI 
> device which is defined as DEVICE_LITTLE_ENDIAN
> 
> AFAIU The memory access process the endianness correctly.

OK, if this is all going through generic memory mechanisms, we should
be fine.

> 
> 
> >   
> >>>     
> >>>> Signed-off-by: Pierre Morel <pmorel@linux.vnet.ibm.com>
> >>>> Reviewed-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com>
> >>>> ---
> >>>>    hw/s390x/s390-pci-inst.c | 27 +++++++++++++++++----------
> >>>>    1 file changed, 17 insertions(+), 10 deletions(-)  
> >   
> 
> 

  reply	other threads:[~2017-11-13 11:55 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-07 17:24 [Qemu-devel] [PATCH 0/7] s390x/pci: Improve zPCI to cover more cases Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 1/7] s390x/pci: factor out endianess conversion Pierre Morel
2017-11-09 16:38   ` Cornelia Huck
2017-11-09 18:55     ` Philippe Mathieu-Daudé
2017-11-09 19:20       ` Cornelia Huck
2017-11-13 15:36         ` Pierre Morel
2017-11-13 16:38           ` Cornelia Huck
2017-11-13 16:43             ` Pierre Morel
2017-11-13  9:34       ` Pierre Morel
2017-11-13  9:37       ` Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 2/7] s390x/pci: rework PCI STORE Pierre Morel
2017-11-09 16:50   ` Cornelia Huck
2017-11-10  9:22     ` Yi Min Zhao
2017-11-13  9:03     ` Pierre Morel
2017-11-13 11:48       ` Cornelia Huck
2017-11-13 14:40         ` Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 3/7] s390x/pci: rework PCI LOAD Pierre Morel
2017-11-09 16:51   ` Cornelia Huck
2017-11-13  9:07     ` Pierre Morel
2017-11-13  9:44     ` Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 4/7] s390x/pci: rework PCI STORE BLOCK Pierre Morel
2017-11-13 15:23   ` Cornelia Huck
2017-11-13 16:38     ` Pierre Morel
2017-11-13 17:10       ` Cornelia Huck
2017-11-15 10:05         ` Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 5/7] s390x/pci: move the memory region read from pcilg Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 6/7] s390x/pci: move the memory region write from pcistg Pierre Morel
2017-11-09 19:23   ` Cornelia Huck
2017-11-10  9:40     ` Yi Min Zhao
2017-11-10  9:51       ` Cornelia Huck
2017-11-13  9:17         ` Pierre Morel
2017-11-13  9:39         ` Pierre Morel
2017-11-13 11:54           ` Cornelia Huck [this message]
2017-11-13 14:44             ` Pierre Morel
2017-11-07 17:24 ` [Qemu-devel] [PATCH 7/7] s390x/pci: search for subregion inside the BARs Pierre Morel
2017-11-13 16:03   ` Cornelia Huck
2017-11-07 17:31 ` [Qemu-devel] [PATCH 0/7] s390x/pci: Improve zPCI to cover more cases Cornelia Huck
2017-11-07 17:50   ` Christian Borntraeger
2017-11-08  8:46     ` Cornelia Huck
2017-11-13 17:13 ` Cornelia Huck
2017-11-15 10:02   ` Pierre Morel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20171113125456.2c7fc9d2.cohuck@redhat.com \
    --to=cohuck@redhat.com \
    --cc=agraf@suse.de \
    --cc=borntraeger@de.ibm.com \
    --cc=pasic@linux.vnet.ibm.com \
    --cc=pmorel@linux.vnet.ibm.com \
    --cc=qemu-devel@nongnu.org \
    --cc=zyimin@linux.vnet.ibm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.