* [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible @ 2017-11-11 0:44 Michel Thierry 2017-11-11 0:44 ` [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry ` (4 more replies) 0 siblings, 5 replies; 10+ messages in thread From: Michel Thierry @ 2017-11-11 0:44 UTC (permalink / raw) To: intel-gfx From gen6, the hardware tracks address lookup failures and we should clear those registers upon startup to prevent false positives. However, this was happening before we have the engines defined (intel_uncore_init()) and the for_each_engine loop was just a nop. The earliest we can call this is inside intel_engines_init_mmio(). Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/intel_uncore.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a0f9d0eb4bce..70bbe8ef8f54 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -289,6 +289,8 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv) device_info->num_rings = hweight32(mask); + i915_check_and_clear_faults(dev_priv); + return 0; cleanup: diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 211acee7c31d..a78ceafcc825 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1420,8 +1420,6 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) iosf_mbi_register_pmic_bus_access_notifier( &dev_priv->uncore.pmic_bus_access_nb); - - i915_check_and_clear_faults(dev_priv); } void intel_uncore_fini(struct drm_i915_private *dev_priv) -- 2.15.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards 2017-11-11 0:44 [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible Michel Thierry @ 2017-11-11 0:44 ` Michel Thierry 2017-11-13 17:36 ` [PATCH v3] " Michel Thierry 2017-11-11 1:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible Patchwork ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Michel Thierry @ 2017-11-11 0:44 UTC (permalink / raw) To: intel-gfx Until Haswell/Baytrail, the hardware used to have a per engine fault register (e.g. 0x4094 - render fault register, 0x4194 - media fault register and so on). But since Broadwell, all these registers were combined into a singe one and the engine id stored in bits 14:12. Not only we should not been reading (and writing to) registers that do not exist, in platforms with VCS2 (SKL), the address that would belong this engine (0x4494, VCS2_HW = 4) is already assigned to other register. v2: use less controversial function names (Chris). References: IHD-OS-BDW-Vol 2c-11.15, page 75. References: IHD-OS-SKL-Vol 2c-05.16, page 350. Signed-off-by: Michel Thierry <michel.thierry@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 52 +++++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 47 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1e40eeb31f9d..c7cfadc7103c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2256,31 +2256,59 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); } -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) +void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - - if (INTEL_INFO(dev_priv)->gen < 6) - return; + u32 fault; for_each_engine(engine, dev_priv, id) { - u32 fault_reg; - fault_reg = I915_READ(RING_FAULT_REG(engine)); - if (fault_reg & RING_FAULT_VALID) { + fault = I915_READ(RING_FAULT_REG(engine)); + if (fault & RING_FAULT_VALID) { DRM_DEBUG_DRIVER("Unexpected fault\n" "\tAddr: 0x%08lx\n" "\tAddress space: %s\n" "\tSource ID: %d\n" "\tType: %d\n", - fault_reg & PAGE_MASK, - fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", - RING_FAULT_SRCID(fault_reg), - RING_FAULT_FAULT_TYPE(fault_reg)); + fault & PAGE_MASK, + fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", + RING_FAULT_SRCID(fault), + RING_FAULT_FAULT_TYPE(fault)); I915_WRITE(RING_FAULT_REG(engine), - fault_reg & ~RING_FAULT_VALID); + fault & ~RING_FAULT_VALID); } } +} + +void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv) +{ + u32 fault = I915_READ(GEN8_RING_FAULT_REG); + + if (fault & RING_FAULT_VALID) { + DRM_DEBUG_DRIVER("Unexpected fault\n" + "\tAddr: 0x%08lx\n" + "\tEngine ID: %d\n" + "\tSource ID: %d\n" + "\tType: %d\n", + fault & PAGE_MASK, + GEN8_RING_FAULT_ENGINE_ID(fault), + RING_FAULT_SRCID(fault), + RING_FAULT_FAULT_TYPE(fault)); + I915_WRITE(GEN8_RING_FAULT_REG, + fault & ~RING_FAULT_VALID); + } +} + +void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) +{ + if (INTEL_GEN(dev_priv) < 6) + return; + + /* From GEN8 onwards we only have one 'All Engine Fault Register' */ + if (INTEL_GEN(dev_priv) >= 8) + gen8_check_and_clear_faults(dev_priv); + else + gen6_check_and_clear_faults(dev_priv); /* Engine specific init may not have been done till this point. */ if (dev_priv->engine[RCS]) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 5c2d83a838d8..7481c8e1b5a8 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1217,11 +1217,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error, if (INTEL_GEN(dev_priv) >= 6) { ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); - ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); - if (INTEL_GEN(dev_priv) >= 8) + if (INTEL_GEN(dev_priv) >= 8) { gen8_record_semaphore_state(error, engine, ee); - else + ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); + } else { gen6_record_semaphore_state(engine, ee); + ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); + } } if (INTEL_GEN(dev_priv) >= 4) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6ef33422f762..7ef82ba670e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2329,6 +2329,8 @@ enum i915_power_well_id { #define ARB_MODE_SWIZZLE_BDW (1<<1) #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id) +#define GEN8_RING_FAULT_REG _MMIO(0x4094) +#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) #define RING_FAULT_GTTSEL_MASK (1<<11) #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) -- 2.15.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3] drm/i915: There is only one fault register from GEN8 onwards 2017-11-11 0:44 ` [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry @ 2017-11-13 17:36 ` Michel Thierry 0 siblings, 0 replies; 10+ messages in thread From: Michel Thierry @ 2017-11-13 17:36 UTC (permalink / raw) To: intel-gfx Until Haswell/Baytrail, the hardware used to have a per engine fault register (e.g. 0x4094 - render fault register, 0x4194 - media fault register and so on). But since Broadwell, all these registers were combined into a singe one and the engine id stored in bits 14:12. Not only we should not been reading (and writing to) registers that do not exist, in platforms with VCS2 (SKL), the address that would belong this engine (0x4494, VCS2_HW = 4) is already assigned to other register. v2: use less controversial function names (Chris). v3: make non-exported functions static, remove now obsolete check for engine presence before posting_read (Chris). References: IHD-OS-BDW-Vol 2c-11.15, page 75. References: IHD-OS-SKL-Vol 2c-05.16, page 350. Signed-off-by: Michel Thierry <michel.thierry@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 57 ++++++++++++++++++++++++++--------- drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 49 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1e40eeb31f9d..3c3a699436c9 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2256,35 +2256,62 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); } -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) +static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - - if (INTEL_INFO(dev_priv)->gen < 6) - return; + u32 fault; for_each_engine(engine, dev_priv, id) { - u32 fault_reg; - fault_reg = I915_READ(RING_FAULT_REG(engine)); - if (fault_reg & RING_FAULT_VALID) { + fault = I915_READ(RING_FAULT_REG(engine)); + if (fault & RING_FAULT_VALID) { DRM_DEBUG_DRIVER("Unexpected fault\n" "\tAddr: 0x%08lx\n" "\tAddress space: %s\n" "\tSource ID: %d\n" "\tType: %d\n", - fault_reg & PAGE_MASK, - fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", - RING_FAULT_SRCID(fault_reg), - RING_FAULT_FAULT_TYPE(fault_reg)); + fault & PAGE_MASK, + fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", + RING_FAULT_SRCID(fault), + RING_FAULT_FAULT_TYPE(fault)); I915_WRITE(RING_FAULT_REG(engine), - fault_reg & ~RING_FAULT_VALID); + fault & ~RING_FAULT_VALID); } } - /* Engine specific init may not have been done till this point. */ - if (dev_priv->engine[RCS]) - POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); + POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); +} + +static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv) +{ + u32 fault = I915_READ(GEN8_RING_FAULT_REG); + + if (fault & RING_FAULT_VALID) { + DRM_DEBUG_DRIVER("Unexpected fault\n" + "\tAddr: 0x%08lx\n" + "\tEngine ID: %d\n" + "\tSource ID: %d\n" + "\tType: %d\n", + fault & PAGE_MASK, + GEN8_RING_FAULT_ENGINE_ID(fault), + RING_FAULT_SRCID(fault), + RING_FAULT_FAULT_TYPE(fault)); + I915_WRITE(GEN8_RING_FAULT_REG, + fault & ~RING_FAULT_VALID); + } + + POSTING_READ(GEN8_RING_FAULT_REG); +} + +void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) +{ + /* From GEN8 onwards we only have one 'All Engine Fault Register' */ + if (INTEL_GEN(dev_priv) >= 8) + gen8_check_and_clear_faults(dev_priv); + else if (INTEL_GEN(dev_priv) >= 6) + gen6_check_and_clear_faults(dev_priv); + else + return; } void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 5c2d83a838d8..7481c8e1b5a8 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1217,11 +1217,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error, if (INTEL_GEN(dev_priv) >= 6) { ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); - ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); - if (INTEL_GEN(dev_priv) >= 8) + if (INTEL_GEN(dev_priv) >= 8) { gen8_record_semaphore_state(error, engine, ee); - else + ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); + } else { gen6_record_semaphore_state(engine, ee); + ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); + } } if (INTEL_GEN(dev_priv) >= 4) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6ef33422f762..7ef82ba670e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2329,6 +2329,8 @@ enum i915_power_well_id { #define ARB_MODE_SWIZZLE_BDW (1<<1) #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id) +#define GEN8_RING_FAULT_REG _MMIO(0x4094) +#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) #define RING_FAULT_GTTSEL_MASK (1<<11) #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) -- 2.15.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible 2017-11-11 0:44 [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible Michel Thierry 2017-11-11 0:44 ` [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry @ 2017-11-11 1:03 ` Patchwork 2017-11-11 1:15 ` Chris Wilson 2017-11-11 2:38 ` ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Patchwork @ 2017-11-11 1:03 UTC (permalink / raw) To: Michel Thierry; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible URL : https://patchwork.freedesktop.org/series/33649/ State : success == Summary == Series 33649v1 series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible https://patchwork.freedesktop.org/api/1.0/series/33649/revisions/1/mbox/ Test gem_exec_reloc: Subgroup basic-gtt-read-active: fail -> PASS (fi-gdg-551) fdo#102582 fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:444s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:453s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:380s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:542s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:273s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:499s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:499s fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:497s fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:489s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:428s fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:262s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:541s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:431s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:439s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:423s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:486s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:462s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:488s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:517s fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:482s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:538s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:458s fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:542s fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:566s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:518s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:496s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:468s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:561s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:422s Blacklisted hosts: fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:532s fi-cnl-y total:289 pass:260 dwarn:0 dfail:0 fail:2 skip:27 time:559s fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:487s 1342299348dec3bd4890284390a2209a00beafce drm-tip: 2017y-11m-10d-18h-11m-22s UTC integration manifest 796cd765f8e4 drm/i915: There is only one fault register from GEN8 onwards 8d1f057f7dab drm/i915: Clear per-engine fault register as early as possible == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7078/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible 2017-11-11 1:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible Patchwork @ 2017-11-11 1:15 ` Chris Wilson 2017-11-11 1:26 ` Michel Thierry 0 siblings, 1 reply; 10+ messages in thread From: Chris Wilson @ 2017-11-11 1:15 UTC (permalink / raw) To: Patchwork, Michel Thierry; +Cc: intel-gfx Quoting Patchwork (2017-11-11 01:03:20) > == Series Details == > > Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible > URL : https://patchwork.freedesktop.org/series/33649/ > State : success BAT results arrived before patches, yay! Patch 1 looks ok for the minimal fix. I think we want to juggle around the suspend/resume i915_check_and_clear_faults() some more, but for now that looks fine. R-b. Patch 2 still has a lack of statics on the non-exported functions. But the names are indeed clearer. I would make the if-else-chain: if (GEN >= 8) gen8_check_and_clear_faults(); else if (GEN >= 6) gen6_check_and_clear_faults(); else return; You also want to move the POSTING_READ since it is still chasing the wrong register on gen8, no? -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible 2017-11-11 1:15 ` Chris Wilson @ 2017-11-11 1:26 ` Michel Thierry 0 siblings, 0 replies; 10+ messages in thread From: Michel Thierry @ 2017-11-11 1:26 UTC (permalink / raw) To: Chris Wilson, intel-gfx, Patchwork On 11/10/2017 5:15 PM, Chris Wilson wrote: > Quoting Patchwork (2017-11-11 01:03:20) >> == Series Details == >> >> Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible >> URL : https://patchwork.freedesktop.org/series/33649/ >> State : success > > BAT results arrived before patches, yay! > > Patch 1 looks ok for the minimal fix. I think we want to juggle around > the suspend/resume i915_check_and_clear_faults() some more, but for now > that looks fine. R-b. > > Patch 2 still has a lack of statics on the non-exported functions. But > the names are indeed clearer. I would make the if-else-chain: > > if (GEN >= 8) > gen8_check_and_clear_faults(); > else if (GEN >= 6) > gen6_check_and_clear_faults(); > else > return; > > You also want to move the POSTING_READ since it is still chasing the > wrong register on gen8, no? I left the POSTING_READ because it's the RCS reg, which is same as gen8, but then the comment above it is no longer valid anyway (the first patch is addressing that)... v3 soon. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible 2017-11-11 0:44 [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible Michel Thierry 2017-11-11 0:44 ` [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry 2017-11-11 1:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible Patchwork @ 2017-11-11 2:38 ` Patchwork 2017-11-13 18:13 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) Patchwork 2017-11-13 19:44 ` ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2017-11-11 2:38 UTC (permalink / raw) To: Michel Thierry; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible URL : https://patchwork.freedesktop.org/series/33649/ State : success == Summary == Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (shard-hsw) fdo#102707 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 shard-hsw total:2584 pass:1469 dwarn:5 dfail:2 fail:9 skip:1099 time:9462s Blacklisted hosts: shard-apl total:2565 pass:1602 dwarn:3 dfail:1 fail:22 skip:936 time:12915s shard-kbl total:2565 pass:1705 dwarn:6 dfail:1 fail:24 skip:828 time:10537s shard-snb total:2512 pass:1175 dwarn:3 dfail:1 fail:14 skip:1319 time:7342s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7078/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) 2017-11-11 0:44 [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible Michel Thierry ` (2 preceding siblings ...) 2017-11-11 2:38 ` ✓ Fi.CI.IGT: " Patchwork @ 2017-11-13 18:13 ` Patchwork 2017-11-13 18:56 ` Chris Wilson 2017-11-13 19:44 ` ✓ Fi.CI.IGT: " Patchwork 4 siblings, 1 reply; 10+ messages in thread From: Patchwork @ 2017-11-13 18:13 UTC (permalink / raw) To: Michel Thierry; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) URL : https://patchwork.freedesktop.org/series/33649/ State : success == Summary == Series 33649v2 series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible https://patchwork.freedesktop.org/api/1.0/series/33649/revisions/2/mbox/ Test chamelium: Subgroup dp-crc-fast: dmesg-fail -> PASS (fi-kbl-7500u) fdo#102514 Test vgem_basic: Subgroup dmabuf-export: incomplete -> PASS (fi-glk-1) fdo#103706 Subgroup unload: notrun -> INCOMPLETE (fi-glk-1) fdo#103702 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#103706 https://bugs.freedesktop.org/show_bug.cgi?id=103706 fdo#103702 https://bugs.freedesktop.org/show_bug.cgi?id=103702 fi-bdw-5557u total:285 pass:263 dwarn:0 dfail:1 fail:0 skip:20 fi-blb-e6850 total:285 pass:218 dwarn:1 dfail:1 fail:0 skip:64 fi-bsw-n3050 total:285 pass:238 dwarn:0 dfail:1 fail:0 skip:45 fi-bwr-2160 total:285 pass:178 dwarn:0 dfail:1 fail:0 skip:105 fi-bxt-dsi total:285 pass:254 dwarn:0 dfail:1 fail:0 skip:29 fi-bxt-j4205 total:285 pass:255 dwarn:0 dfail:1 fail:0 skip:28 fi-byt-j1900 total:285 pass:249 dwarn:0 dfail:1 fail:0 skip:34 fi-byt-n2820 total:278 pass:238 dwarn:0 dfail:1 fail:0 skip:38 fi-elk-e7500 total:285 pass:224 dwarn:0 dfail:1 fail:0 skip:59 fi-gdg-551 total:285 pass:174 dwarn:0 dfail:1 fail:1 skip:108 fi-glk-1 total:285 pass:256 dwarn:0 dfail:1 fail:0 skip:27 fi-hsw-4770 total:285 pass:257 dwarn:0 dfail:1 fail:0 skip:26 fi-hsw-4770r total:285 pass:257 dwarn:0 dfail:1 fail:0 skip:26 fi-ilk-650 total:285 pass:223 dwarn:0 dfail:1 fail:0 skip:60 fi-ivb-3520m total:285 pass:255 dwarn:0 dfail:1 fail:0 skip:28 fi-ivb-3770 total:285 pass:255 dwarn:0 dfail:1 fail:0 skip:28 fi-kbl-7500u total:285 pass:259 dwarn:1 dfail:1 fail:0 skip:23 fi-kbl-7560u total:285 pass:265 dwarn:0 dfail:1 fail:0 skip:18 fi-kbl-7567u total:285 pass:264 dwarn:0 dfail:1 fail:0 skip:19 fi-kbl-r total:285 pass:257 dwarn:0 dfail:1 fail:0 skip:26 fi-pnv-d510 total:285 pass:217 dwarn:1 dfail:1 fail:0 skip:65 fi-skl-6260u total:285 pass:264 dwarn:0 dfail:1 fail:0 skip:19 fi-skl-6700hq total:285 pass:258 dwarn:0 dfail:1 fail:0 skip:25 fi-skl-6700k total:285 pass:260 dwarn:0 dfail:1 fail:0 skip:23 fi-skl-6770hq total:285 pass:264 dwarn:0 dfail:1 fail:0 skip:19 fi-skl-gvtdvm total:285 pass:261 dwarn:0 dfail:1 fail:0 skip:22 fi-snb-2520m total:285 pass:245 dwarn:0 dfail:1 fail:0 skip:38 fi-snb-2600 total:285 pass:244 dwarn:0 dfail:1 fail:0 skip:39 Blacklisted hosts: fi-cfl-s total:285 pass:252 dwarn:0 dfail:1 fail:0 skip:31 9891b4090c6e6a5299a4134f7bd6c463fb2cd485 drm-tip: 2017y-11m-13d-16h-04m-46s UTC integration manifest f9faa34650e8 drm/i915: There is only one fault register from GEN8 onwards 1a9f6b0c2e8f drm/i915: Clear per-engine fault register as early as possible == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7099/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) 2017-11-13 18:13 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) Patchwork @ 2017-11-13 18:56 ` Chris Wilson 0 siblings, 0 replies; 10+ messages in thread From: Chris Wilson @ 2017-11-13 18:56 UTC (permalink / raw) To: Patchwork, Michel Thierry; +Cc: intel-gfx Quoting Patchwork (2017-11-13 18:13:01) > == Series Details == > > Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) > URL : https://patchwork.freedesktop.org/series/33649/ > State : success More MTA fun, so I'll plonk my Reviewed-by here and pick these up from pw. Thanks for the patches, -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) 2017-11-11 0:44 [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible Michel Thierry ` (3 preceding siblings ...) 2017-11-13 18:13 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) Patchwork @ 2017-11-13 19:44 ` Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2017-11-13 19:44 UTC (permalink / raw) To: Michel Thierry; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) URL : https://patchwork.freedesktop.org/series/33649/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test kms_plane_lowres: Subgroup pipe-b-tiling-none: pass -> SKIP (shard-hsw) fdo#103181 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#103181 https://bugs.freedesktop.org/show_bug.cgi?id=103181 shard-hsw total:2584 pass:1469 dwarn:3 dfail:2 fail:10 skip:1100 time:9504s Blacklisted hosts: shard-apl total:2495 pass:1561 dwarn:1 dfail:1 fail:24 skip:906 time:12458s shard-kbl total:2565 pass:1709 dwarn:2 dfail:1 fail:25 skip:827 time:10530s shard-snb total:2584 pass:1211 dwarn:2 dfail:2 fail:13 skip:1356 time:7738s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7099/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-11-13 19:44 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-11-11 0:44 [PATCH 1/2] drm/i915: Clear per-engine fault register as early as possible Michel Thierry 2017-11-11 0:44 ` [PATCH 2/2 v2] drm/i915: There is only one fault register from GEN8 onwards Michel Thierry 2017-11-13 17:36 ` [PATCH v3] " Michel Thierry 2017-11-11 1:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible Patchwork 2017-11-11 1:15 ` Chris Wilson 2017-11-11 1:26 ` Michel Thierry 2017-11-11 2:38 ` ✓ Fi.CI.IGT: " Patchwork 2017-11-13 18:13 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear per-engine fault register as early as possible (rev2) Patchwork 2017-11-13 18:56 ` Chris Wilson 2017-11-13 19:44 ` ✓ Fi.CI.IGT: " Patchwork
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