* [CI 1/2] drm/i915: Remove pre-production Broxton register workarounds
@ 2017-11-14 13:43 Chris Wilson
2017-11-14 13:43 ` [CI 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2017-11-14 13:43 UTC (permalink / raw)
To: intel-gfx
We've begun excluding pre-production Broxton machines since commit
0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of preproduction
machines"), now remove the list of workaround register values for those
early machines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170927093325.24206-1-chris@chris-wilson.co.uk
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 56 +---------------------------------
1 file changed, 1 insertion(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 70bbe8ef8f54..88923e9ecdf8 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1020,22 +1020,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
- /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
- GEN9_DG_MIRROR_FIX_ENABLE);
-
- /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
- GEN9_RHWO_OPTIMIZATION_DISABLE);
- /*
- * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
- * but we do that in per ctx batchbuffer as there is an issue
- * with this register not getting restored on ctx restore
- */
- }
-
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
@@ -1051,11 +1035,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
- /* WaDisableMaskBasedCammingInRCC:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
- PIXEL_MASK_CAMMING_DISABLE);
-
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
@@ -1085,8 +1064,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
if (IS_SKYLAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
- IS_COFFEELAKE(dev_priv) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+ IS_COFFEELAKE(dev_priv))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1216,17 +1194,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
- /* WaStoreMultiplePTEenable:bxt */
- /* This is a requirement according to Hardware specification */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
-
- /* WaSetClckGatingDisableMedia:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
- ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
- }
-
/* WaDisableThreadStallDopClockGating:bxt */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
@@ -1237,27 +1204,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
_MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
}
- /* WaDisableSbeCacheDispatchPortSharing:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
- WA_SET_BIT_MASKED(
- GEN7_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
- }
-
- /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
- /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
- /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
- /* WaDisableLSQCROPERFforOCL:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
- if (ret)
- return ret;
-
- ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
- if (ret)
- return ret;
- }
-
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
u32 val = I915_READ(GEN8_L3SQCREG1);
--
2.15.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI 2/2] drm/i915: Unconditionally apply the Broxton register workaround set
2017-11-14 13:43 [CI 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
@ 2017-11-14 13:43 ` Chris Wilson
2017-11-14 14:11 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds Patchwork
2017-11-14 15:28 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-11-14 13:43 UTC (permalink / raw)
To: intel-gfx
Having removed the preproduction Broxton support (see commit 0102ba1fd8af
("drm/i915: Add early BXT sdv to the list of preproduction machines")),
we know we then always need the production Broxton workaround set and do
not need a predicate upon revision.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 88923e9ecdf8..6eb705420a2b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1188,6 +1188,7 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
static int bxt_init_workarounds(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ u32 val;
int ret;
ret = gen9_init_workarounds(engine);
@@ -1199,29 +1200,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
STALL_DOP_GATING_DISABLE);
/* WaDisablePooledEuLoadBalancingFix:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
- I915_WRITE(FF_SLICE_CS_CHICKEN2,
- _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
- }
+ I915_WRITE(FF_SLICE_CS_CHICKEN2,
+ _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
- u32 val = I915_READ(GEN8_L3SQCREG1);
- val &= ~L3_PRIO_CREDITS_MASK;
- val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
- I915_WRITE(GEN8_L3SQCREG1, val);
- }
+ val = I915_READ(GEN8_L3SQCREG1);
+ val &= ~L3_PRIO_CREDITS_MASK;
+ val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
+ I915_WRITE(GEN8_L3SQCREG1, val);
/* WaToEnableHwFixForPushConstHWBug:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
- WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
- GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaInPlaceDecompressionHang:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
- (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
return 0;
}
--
2.15.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-11-14 13:43 [CI 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
2017-11-14 13:43 ` [CI 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
@ 2017-11-14 14:11 ` Patchwork
2017-11-14 15:28 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-11-14 14:11 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
URL : https://patchwork.freedesktop.org/series/33780/
State : success
== Summary ==
Series 33780v1 series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
https://patchwork.freedesktop.org/api/1.0/series/33780/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:383s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:536s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:276s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:506s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:502s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:489s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:426s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:265s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:547s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:431s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:442s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:430s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:486s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:463s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:485s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:519s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:482s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:537s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:573s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:548s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:565s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:520s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:501s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:465s
fi-snb-2520m total:246 pass:212 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:426s
Blacklisted hosts:
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:532s
fi-cnl-y total:289 pass:261 dwarn:0 dfail:0 fail:1 skip:27 time:569s
fi-glk-dsi failed to connect after reboot
150c0315ce448d88e22e7e675eed6e55abbe04cd drm-tip: 2017y-11m-14d-10h-02m-23s UTC integration manifest
f473ceb7499a drm/i915: Unconditionally apply the Broxton register workaround set
9671dd7dcfcc drm/i915: Remove pre-production Broxton register workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7115/
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-11-14 13:43 [CI 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
2017-11-14 13:43 ` [CI 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
2017-11-14 14:11 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds Patchwork
@ 2017-11-14 15:28 ` Patchwork
2017-11-14 15:32 ` Chris Wilson
2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2017-11-14 15:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
URL : https://patchwork.freedesktop.org/series/33780/
State : success
== Summary ==
Warning: bzip CI_DRM_3343/shard-glkb6/results34.json.bz2 wasn't in correct JSON format
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-b:
pass -> DMESG-WARN (shard-hsw) fdo#103038
fdo#103038 https://bugs.freedesktop.org/show_bug.cgi?id=103038
shard-hsw total:2584 pass:1471 dwarn:3 dfail:1 fail:10 skip:1099 time:9498s
Blacklisted hosts:
shard-apl total:2584 pass:1623 dwarn:2 dfail:1 fail:22 skip:936 time:12986s
shard-kbl total:2450 pass:1630 dwarn:5 dfail:2 fail:23 skip:788 time:10001s
shard-snb total:2584 pass:1200 dwarn:3 dfail:1 fail:12 skip:1368 time:7765s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7115/shards.html
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-11-14 15:28 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-11-14 15:32 ` Chris Wilson
2017-11-15 17:58 ` David Weinehall
0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2017-11-14 15:32 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
Quoting Patchwork (2017-11-14 15:28:51)
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
> URL : https://patchwork.freedesktop.org/series/33780/
> State : success
>
> == Summary ==
>
> Warning: bzip CI_DRM_3343/shard-glkb6/results34.json.bz2 wasn't in correct JSON format
> Test kms_busy:
> Subgroup extended-modeset-hang-newfb-with-reset-render-b:
> pass -> DMESG-WARN (shard-hsw) fdo#103038
>
> fdo#103038 https://bugs.freedesktop.org/show_bug.cgi?id=103038
>
> shard-hsw total:2584 pass:1471 dwarn:3 dfail:1 fail:10 skip:1099 time:9498s
> Blacklisted hosts:
> shard-apl total:2584 pass:1623 dwarn:2 dfail:1 fail:22 skip:936 time:12986s
> shard-kbl total:2450 pass:1630 dwarn:5 dfail:2 fail:23 skip:788 time:10001s
> shard-snb total:2584 pass:1200 dwarn:3 dfail:1 fail:12 skip:1368 time:7765s
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7115/shards.html
After a few months waiting for David Weinehall to wean himself off his
bxt sdp, I've given in and pushed. Thanks for the review, and yes we can
probably start reducing the unused macros for checking for preproduction
machines.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-11-14 15:32 ` Chris Wilson
@ 2017-11-15 17:58 ` David Weinehall
0 siblings, 0 replies; 6+ messages in thread
From: David Weinehall @ 2017-11-15 17:58 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Tue, Nov 14, 2017 at 03:32:17PM +0000, Chris Wilson wrote:
> Quoting Patchwork (2017-11-14 15:28:51)
> > == Series Details ==
> >
> > Series: series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds
> > URL : https://patchwork.freedesktop.org/series/33780/
> > State : success
> >
> > == Summary ==
> >
> > Warning: bzip CI_DRM_3343/shard-glkb6/results34.json.bz2 wasn't in correct JSON format
> > Test kms_busy:
> > Subgroup extended-modeset-hang-newfb-with-reset-render-b:
> > pass -> DMESG-WARN (shard-hsw) fdo#103038
> >
> > fdo#103038 https://bugs.freedesktop.org/show_bug.cgi?id=103038
> >
> > shard-hsw total:2584 pass:1471 dwarn:3 dfail:1 fail:10 skip:1099 time:9498s
> > Blacklisted hosts:
> > shard-apl total:2584 pass:1623 dwarn:2 dfail:1 fail:22 skip:936 time:12986s
> > shard-kbl total:2450 pass:1630 dwarn:5 dfail:2 fail:23 skip:788 time:10001s
> > shard-snb total:2584 pass:1200 dwarn:3 dfail:1 fail:12 skip:1368 time:7765s
> >
> > == Logs ==
> >
> > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7115/shards.html
>
> After a few months waiting for David Weinehall to wean himself off his
> bxt sdp, I've given in and pushed. Thanks for the review, and yes we can
> probably start reducing the unused macros for checking for preproduction
> machines.
I actually removed the BXT RVP from our farm a while ago, so that's fine
:)
Kind regards ,David
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-11-15 17:58 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-14 13:43 [CI 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
2017-11-14 13:43 ` [CI 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
2017-11-14 14:11 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Remove pre-production Broxton register workarounds Patchwork
2017-11-14 15:28 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-14 15:32 ` Chris Wilson
2017-11-15 17:58 ` David Weinehall
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