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* [PATCH] arm64: ITS: fix cacheability adjustment
@ 2017-11-16 12:02 Andre Przywara
  2017-11-28 14:05 ` Andre Przywara
  0 siblings, 1 reply; 3+ messages in thread
From: Andre Przywara @ 2017-11-16 12:02 UTC (permalink / raw)
  To: Julien Grall, Stefano Stabellini; +Cc: Manish Jaggi, xen-devel

If the host GICv3 redistributor reports that the pending table cannot
use shareable memory, we try to drop the cacheability attributes as
well. However we fail horribly in doing computer science 101 bit
masking, effectively clearing the whole register instead of just a few
bits.
Fix this by removing the one redundant masking operation and adding the
magic negation for the actually needed other operation.

Reported-by: Manish Jaggi <manish.jaggi@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
---
Julien,

can we have this still for 4.10, please? Seems like an obvious bug to me.

Cheers,
Andre

 xen/arch/arm/gic-v3-lpi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
index c3474f5434..84582157b8 100644
--- a/xen/arch/arm/gic-v3-lpi.c
+++ b/xen/arch/arm/gic-v3-lpi.c
@@ -359,8 +359,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base)
     /* If the hardware reports non-shareable, drop cacheability as well. */
     if ( !(table_reg & GICR_PENDBASER_SHAREABILITY_MASK) )
     {
-        table_reg &= GICR_PENDBASER_SHAREABILITY_MASK;
-        table_reg &= GICR_PENDBASER_INNER_CACHEABILITY_MASK;
+        table_reg &= ~GICR_PENDBASER_INNER_CACHEABILITY_MASK;
         table_reg |= GIC_BASER_CACHE_nC << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT;
 
         writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER);
-- 
2.14.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] arm64: ITS: fix cacheability adjustment
  2017-11-16 12:02 [PATCH] arm64: ITS: fix cacheability adjustment Andre Przywara
@ 2017-11-28 14:05 ` Andre Przywara
  2017-11-28 19:01   ` Julien Grall
  0 siblings, 1 reply; 3+ messages in thread
From: Andre Przywara @ 2017-11-28 14:05 UTC (permalink / raw)
  To: Julien Grall, Stefano Stabellini, Manish Jaggi; +Cc: xen-devel

Hi,

On 16/11/17 12:02, Andre Przywara wrote:
> If the host GICv3 redistributor reports that the pending table cannot
> use shareable memory, we try to drop the cacheability attributes as
> well. However we fail horribly in doing computer science 101 bit
> masking, effectively clearing the whole register instead of just a few
> bits.
> Fix this by removing the one redundant masking operation and adding the
> magic negation for the actually needed other operation.
> 
> Reported-by: Manish Jaggi <manish.jaggi@linaro.org>

Manish, can you please test this patch and confirm that it works?
Also how does the bug manifest for you?

Julien, Stefano: Are there any objections against taking this patch for
4.10? This was introduced with the ITS emulation.

Cheers,
Andre.

> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
> ---
> Julien,
> 
> can we have this still for 4.10, please? Seems like an obvious bug to me.
> 
> Cheers,
> Andre
> 
>  xen/arch/arm/gic-v3-lpi.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
> index c3474f5434..84582157b8 100644
> --- a/xen/arch/arm/gic-v3-lpi.c
> +++ b/xen/arch/arm/gic-v3-lpi.c
> @@ -359,8 +359,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base)
>      /* If the hardware reports non-shareable, drop cacheability as well. */
>      if ( !(table_reg & GICR_PENDBASER_SHAREABILITY_MASK) )
>      {
> -        table_reg &= GICR_PENDBASER_SHAREABILITY_MASK;
> -        table_reg &= GICR_PENDBASER_INNER_CACHEABILITY_MASK;
> +        table_reg &= ~GICR_PENDBASER_INNER_CACHEABILITY_MASK;
>          table_reg |= GIC_BASER_CACHE_nC << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT;
>  
>          writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER);
> 

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^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] arm64: ITS: fix cacheability adjustment
  2017-11-28 14:05 ` Andre Przywara
@ 2017-11-28 19:01   ` Julien Grall
  0 siblings, 0 replies; 3+ messages in thread
From: Julien Grall @ 2017-11-28 19:01 UTC (permalink / raw)
  To: Andre Przywara, Stefano Stabellini, Manish Jaggi; +Cc: xen-devel

On 11/28/2017 02:05 PM, Andre Przywara wrote:
> Hi,

Hi Andre,

Sorry someone I skipped that patch :/.

> On 16/11/17 12:02, Andre Przywara wrote:
>> If the host GICv3 redistributor reports that the pending table cannot
>> use shareable memory, we try to drop the cacheability attributes as
>> well. However we fail horribly in doing computer science 101 bit
>> masking, effectively clearing the whole register instead of just a few
>> bits.
>> Fix this by removing the one redundant masking operation and adding the
>> magic negation for the actually needed other operation.
>>
>> Reported-by: Manish Jaggi <manish.jaggi@linaro.org>
> 
> Manish, can you please test this patch and confirm that it works?
> Also how does the bug manifest for you?
> 
> Julien, Stefano: Are there any objections against taking this patch for > 4.10? This was introduced with the ITS emulation.

Reviewed-by: Julien Grall <julien.grall@linaro.org>

This is new code and in technical preview. So I think it is fine to get 
them in Xen 4.10.

Release-Acked-by: Julien Grall <julien.grall@linaro.org>

Cheers,

--
Julien Grall

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^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2017-11-28 19:01 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2017-11-16 12:02 [PATCH] arm64: ITS: fix cacheability adjustment Andre Przywara
2017-11-28 14:05 ` Andre Przywara
2017-11-28 19:01   ` Julien Grall

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