* [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
@ 2017-11-21 10:22 Lucas De Marchi
2017-11-21 10:58 ` Jani Nikula
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Lucas De Marchi @ 2017-11-21 10:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Arthur J Runyan, Lucas De Marchi, Rodrigo Vivi
Wa Display #1183 was recently added to workaround
"Failures when enabling DPLL0 with eDP link rate 2.16
or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
(CDCLK_CTL CD Frequency Select 10b or 11b) used in this
enabling or in previous enabling."
This Workaround was designed to minimize the impact only
to save the bad case with that link rates. But HW engineers
indicated that it should be safe to apply broadly, although
they were expecting the DPLL0 link rate to be unchanged on
runtime.
We need to cover 2 cases: when we are in fact enabling DPLL0
and when we are just changing the frequency with small
differences.
This is based on previous patch by Rodrigo Vivi with suggestions
from Ville Syrjälä.
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_cdclk.c | 36 ++++++++++++++++++++++++---------
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++++++
3 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 96c80fa0fcac..6dd3538c2074 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7018,6 +7018,7 @@ enum {
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
+#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
#define MASK_WAKEMEM (1<<13)
#define SKL_DFSM _MMIO(0x51000)
@@ -8572,6 +8573,7 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
+#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index e8884c2ade98..7f899a0e1e4a 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -931,16 +931,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
{
- int min_cdclk = skl_calc_cdclk(0, vco);
u32 val;
WARN_ON(vco != 8100000 && vco != 8640000);
- /* select the minimum CDCLK before enabling DPLL 0 */
- val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
- I915_WRITE(CDCLK_CTL, val);
- POSTING_READ(CDCLK_CTL);
-
/*
* We always enable DPLL0 with the lowest link rate possible, but still
* taking into account the VCO required to operate the eDP panel at the
@@ -994,7 +988,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
- u32 freq_select;
+ u32 freq_select, cdclk_ctl;
int ret;
mutex_lock(&dev_priv->pcu_lock);
@@ -1009,7 +1003,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- /* set CDCLK_CTL */
+ /* Choose frequency for this cdclk */
switch (cdclk) {
default:
WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
@@ -1036,11 +1030,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
dev_priv->cdclk.hw.vco != vco)
skl_dpll0_disable(dev_priv);
+ cdclk_ctl = I915_READ(CDCLK_CTL);
+
+ if (dev_priv->cdclk.hw.vco != vco) {
+ /* Wa Display #1183: skl,kbl,cfl */
+ cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
+ cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
+ I915_WRITE(CDCLK_CTL, cdclk_ctl);
+ }
+
+ /* Wa Display #1183: skl,kbl,cfl */
+ cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
+ I915_WRITE(CDCLK_CTL, cdclk_ctl);
+ POSTING_READ(CDCLK_CTL);
+
if (dev_priv->cdclk.hw.vco != vco)
skl_dpll0_enable(dev_priv, vco);
- I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
- POSTING_READ(CDCLK_CTL);
+ /* Wa Display #1183: skl,kbl,cfl */
+ cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
+ I915_WRITE(CDCLK_CTL, cdclk_ctl);
+
+ cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
+ I915_WRITE(CDCLK_CTL, cdclk_ctl);
+
+ /* Wa Display #1183: skl,kbl,cfl */
+ cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
+ I915_WRITE(CDCLK_CTL, cdclk_ctl);
/* inform PCU of the change */
mutex_lock(&dev_priv->pcu_lock);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8315499452dc..35796fa8e6b4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling DC5\n");
+ /* Wa Display #1183: skl,kbl,cfl */
+ if (IS_GEN9_BC(dev_priv))
+ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+ SKL_SELECT_ALTERNATE_DC_EXIT);
+
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
}
@@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
{
DRM_DEBUG_KMS("Disabling DC6\n");
+ /* Wa Display #1183: skl,kbl,cfl */
+ if (IS_GEN9_BC(dev_priv))
+ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+ SKL_SELECT_ALTERNATE_DC_EXIT);
+
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
}
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
2017-11-21 10:22 [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl Lucas De Marchi
@ 2017-11-21 10:58 ` Jani Nikula
2017-11-21 11:33 ` ✗ Fi.CI.BAT: warning for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3) Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2017-11-21 10:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Arthur J Runyan, Lucas De Marchi, Rodrigo Vivi
On Tue, 21 Nov 2017, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Wa Display #1183 was recently added to workaround
> "Failures when enabling DPLL0 with eDP link rate 2.16
> or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
> (CDCLK_CTL CD Frequency Select 10b or 11b) used in this
> enabling or in previous enabling."
>
> This Workaround was designed to minimize the impact only
> to save the bad case with that link rates. But HW engineers
> indicated that it should be safe to apply broadly, although
> they were expecting the DPLL0 link rate to be unchanged on
> runtime.
>
> We need to cover 2 cases: when we are in fact enabling DPLL0
> and when we are just changing the frequency with small
> differences.
>
> This is based on previous patch by Rodrigo Vivi with suggestions
> from Ville Syrjälä.
>
> Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Should this be Cc: stable@vger.kernel.org?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_cdclk.c | 36 ++++++++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++++++
> 3 files changed, 38 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 96c80fa0fcac..6dd3538c2074 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7018,6 +7018,7 @@ enum {
> #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
>
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> +#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
> #define MASK_WAKEMEM (1<<13)
>
> #define SKL_DFSM _MMIO(0x51000)
> @@ -8572,6 +8573,7 @@ enum skl_power_gate {
> #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
> #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
> #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
> +#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
> #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index e8884c2ade98..7f899a0e1e4a 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -931,16 +931,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
>
> static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> {
> - int min_cdclk = skl_calc_cdclk(0, vco);
> u32 val;
>
> WARN_ON(vco != 8100000 && vco != 8640000);
>
> - /* select the minimum CDCLK before enabling DPLL 0 */
> - val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
> - I915_WRITE(CDCLK_CTL, val);
> - POSTING_READ(CDCLK_CTL);
> -
> /*
> * We always enable DPLL0 with the lowest link rate possible, but still
> * taking into account the VCO required to operate the eDP panel at the
> @@ -994,7 +988,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> {
> int cdclk = cdclk_state->cdclk;
> int vco = cdclk_state->vco;
> - u32 freq_select;
> + u32 freq_select, cdclk_ctl;
> int ret;
>
> mutex_lock(&dev_priv->pcu_lock);
> @@ -1009,7 +1003,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> return;
> }
>
> - /* set CDCLK_CTL */
> + /* Choose frequency for this cdclk */
> switch (cdclk) {
> default:
> WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> @@ -1036,11 +1030,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> dev_priv->cdclk.hw.vco != vco)
> skl_dpll0_disable(dev_priv);
>
> + cdclk_ctl = I915_READ(CDCLK_CTL);
> +
> + if (dev_priv->cdclk.hw.vco != vco) {
> + /* Wa Display #1183: skl,kbl,cfl */
> + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> + I915_WRITE(CDCLK_CTL, cdclk_ctl);
> + }
> +
> + /* Wa Display #1183: skl,kbl,cfl */
> + cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
> + I915_WRITE(CDCLK_CTL, cdclk_ctl);
> + POSTING_READ(CDCLK_CTL);
> +
> if (dev_priv->cdclk.hw.vco != vco)
> skl_dpll0_enable(dev_priv, vco);
>
> - I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> - POSTING_READ(CDCLK_CTL);
> + /* Wa Display #1183: skl,kbl,cfl */
> + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> + I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> + I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> + /* Wa Display #1183: skl,kbl,cfl */
> + cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
> + I915_WRITE(CDCLK_CTL, cdclk_ctl);
>
> /* inform PCU of the change */
> mutex_lock(&dev_priv->pcu_lock);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 8315499452dc..35796fa8e6b4 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>
> DRM_DEBUG_KMS("Enabling DC5\n");
>
> + /* Wa Display #1183: skl,kbl,cfl */
> + if (IS_GEN9_BC(dev_priv))
> + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> + SKL_SELECT_ALTERNATE_DC_EXIT);
> +
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> @@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
> {
> DRM_DEBUG_KMS("Disabling DC6\n");
>
> + /* Wa Display #1183: skl,kbl,cfl */
> + if (IS_GEN9_BC(dev_priv))
> + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> + SKL_SELECT_ALTERNATE_DC_EXIT);
> +
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
2017-11-21 10:22 [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl Lucas De Marchi
2017-11-21 10:58 ` Jani Nikula
@ 2017-11-21 11:33 ` Patchwork
2017-11-21 19:06 ` Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-11-21 11:33 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
URL : https://patchwork.freedesktop.org/series/33508/
State : warning
== Summary ==
Series 33508v3 drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
https://patchwork.freedesktop.org/api/1.0/series/33508/revisions/3/mbox/
Test gem_exec_reloc:
Subgroup basic-cpu-active:
pass -> FAIL (fi-gdg-551) fdo#102582 +2
Test kms_cursor_legacy:
Subgroup basic-flip-before-cursor-varying-size:
skip -> PASS (fi-hsw-4770r)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
pass -> SKIP (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:442s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:454s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:382s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:541s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:277s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:510s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:502s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:492s
fi-cfl-s2 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:604s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s
fi-gdg-551 total:289 pass:176 dwarn:1 dfail:0 fail:3 skip:109 time:264s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:539s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:429s
fi-hsw-4770r total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:436s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:426s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:489s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:470s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:484s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:533s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:477s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:540s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:570s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:550s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:570s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:522s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:498s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:564s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:426s
Blacklisted hosts:
fi-glk-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:490s
ee3fc3c956f817479cfe2bac3cc2a72112dbdec1 drm-tip: 2017y-11m-21d-09h-02m-11s UTC integration manifest
6e7dd60c6443 drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7215/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
2017-11-21 10:22 [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl Lucas De Marchi
2017-11-21 10:58 ` Jani Nikula
2017-11-21 11:33 ` ✗ Fi.CI.BAT: warning for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3) Patchwork
@ 2017-11-21 19:06 ` Patchwork
2017-11-21 21:11 ` ✓ Fi.CI.BAT: success " Patchwork
2017-11-21 22:03 ` ✗ Fi.CI.IGT: warning " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-11-21 19:06 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
URL : https://patchwork.freedesktop.org/series/33508/
State : warning
== Summary ==
Series 33508v3 drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
https://patchwork.freedesktop.org/api/1.0/series/33508/revisions/3/mbox/
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c:
pass -> SKIP (fi-hsw-4770r)
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:445s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:460s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:387s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:537s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:277s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:506s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:519s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:502s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:497s
fi-cfl-s2 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:618s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:435s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:268s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:537s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:427s
fi-hsw-4770r total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:438s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:426s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:490s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:460s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:474s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:528s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:480s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:528s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:582s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:548s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:567s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:520s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:498s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:462s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:568s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:427s
Blacklisted hosts:
fi-cnl-y total:241 pass:216 dwarn:0 dfail:0 fail:0 skip:24
fi-glk-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:492s
f71044153bec6b5fbde984769d97b38fccf06722 drm-tip: 2017y-11m-21d-10h-48m-53s UTC integration manifest
c94c3a68a3f4 drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7226/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
2017-11-21 10:22 [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl Lucas De Marchi
` (2 preceding siblings ...)
2017-11-21 19:06 ` Patchwork
@ 2017-11-21 21:11 ` Patchwork
2017-11-21 22:03 ` ✗ Fi.CI.IGT: warning " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-11-21 21:11 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
URL : https://patchwork.freedesktop.org/series/33508/
State : success
== Summary ==
Series 33508v3 drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
https://patchwork.freedesktop.org/api/1.0/series/33508/revisions/3/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:456s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:381s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:534s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:279s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:512s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:503s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:487s
fi-cfl-s2 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:605s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:432s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:264s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:539s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:440s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:426s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:482s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:480s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:535s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:477s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:532s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:578s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:546s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:567s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:516s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:497s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:458s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:554s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:422s
Blacklisted hosts:
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:549s
fi-glk-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:500s
9cbb5ad289f8f874e048120d6ac3862b2f36a8ac drm-tip: 2017y-11m-21d-19h-39m-42s UTC integration manifest
592309e740c3 drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7227/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
2017-11-21 10:22 [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl Lucas De Marchi
` (3 preceding siblings ...)
2017-11-21 21:11 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-11-21 22:03 ` Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-11-21 22:03 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3)
URL : https://patchwork.freedesktop.org/series/33508/
State : warning
== Summary ==
Test kms_flip:
Subgroup flip-vs-panning:
pass -> DMESG-WARN (shard-hsw)
Test kms_plane_lowres:
Subgroup pipe-a-tiling-none:
pass -> INCOMPLETE (shard-hsw) fdo#102614
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail -> PASS (shard-snb) fdo#101623 +1
Test kms_draw_crc:
Subgroup draw-method-xrgb2101010-render-xtiled:
pass -> SKIP (shard-snb)
Test drv_suspend:
Subgroup fence-restore-untiled:
pass -> SKIP (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2551 pass:1445 dwarn:2 dfail:1 fail:10 skip:1092 time:9211s
shard-snb total:2585 pass:1258 dwarn:1 dfail:1 fail:11 skip:1314 time:8045s
Blacklisted hosts:
shard-apl total:2565 pass:1601 dwarn:3 dfail:0 fail:23 skip:937 time:12987s
shard-kbl total:2419 pass:1596 dwarn:9 dfail:2 fail:22 skip:786 time:9847s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7227/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-11-21 22:03 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-21 10:22 [PATCH v5] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl Lucas De Marchi
2017-11-21 10:58 ` Jani Nikula
2017-11-21 11:33 ` ✗ Fi.CI.BAT: warning for drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl (rev3) Patchwork
2017-11-21 19:06 ` Patchwork
2017-11-21 21:11 ` ✓ Fi.CI.BAT: success " Patchwork
2017-11-21 22:03 ` ✗ Fi.CI.IGT: warning " Patchwork
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