[U-Boot] [PATCH 0/3] MIPS: Caching fixes

[U-Boot] [PATCH 0/3] MIPS: Caching fixes

[Paul Burton]

This short series fixes a few issues related to our caching code - with
regards to DMA coherence, instruction cache coherence & systems with no
caches at all.

Applies atop u-boot-mips/next as of d7d9fc01a4ef ("Update Paul Burton's
email address").


Paul Burton (3):
  MIPS: Ensure cache ops complete in cache maintenance functions
  MIPS: Clear instruction hazards in flush_cache()
  MIPS: Break out of cache loops for unimplemented caches

 arch/mips/include/asm/system.h | 13 +++++++++++++
 arch/mips/lib/cache.c          | 30 ++++++++++++++++++++++--------
 2 files changed, 35 insertions(+), 8 deletions(-)

-- 
2.15.0

[U-Boot] [PATCH 1/3] MIPS: Ensure cache ops complete in cache maintenance functions

[Paul Burton]

A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a device to read memory. This requires that we
place a completion barrier (ie. sync instruction) between the cache ops
and whatever write informs the device to perform DMA.

Whilst strictly speaking this isn't all users of the cache maintenance
functions & we could instead place the barriers in the drivers that
require them, it would be much more invasive to do so than to just have
the barrier be the default by placing it in the cache functions
themselves. The cost is low enough that it shouldn't matter to us in any
rare cases that we use the cache functions when not performing DMA.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot at lists.denx.de
---

 arch/mips/lib/cache.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 91b037f87d..eba7fff316 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -10,6 +10,7 @@
 #ifdef CONFIG_MIPS_L2_CACHE
 #include <asm/cm.h>
 #endif
+#include <asm/io.h>
 #include <asm/mipsregs.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -116,7 +117,7 @@ void flush_cache(ulong start_addr, ulong size)
 		/* flush I-cache & D-cache simultaneously */
 		cache_loop(start_addr, start_addr + size, ilsize,
 			   HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
-		return;
+		goto ops_done;
 	}
 
 	/* flush D-cache */
@@ -129,6 +130,10 @@ void flush_cache(ulong start_addr, ulong size)
 
 	/* flush I-cache */
 	cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
+
+ops_done:
+	/* ensure cache ops complete before any further memory accesses */
+	sync();
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
@@ -145,6 +150,9 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 	/* flush L2 cache */
 	if (slsize)
 		cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
+
+	/* ensure cache ops complete before any further memory accesses */
+	sync();
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -161,4 +169,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
 
 	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
+
+	/* ensure cache ops complete before any further memory accesses */
+	sync();
 }
-- 
2.15.0

[U-Boot] [PATCH 2/3] MIPS: Clear instruction hazards in flush_cache()

[Paul Burton]

When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.

In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot at lists.denx.de
---

 arch/mips/include/asm/system.h | 13 +++++++++++++
 arch/mips/lib/cache.c          |  4 ++++
 2 files changed, 17 insertions(+)

diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index c9c5961462..eaf1b2290d 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -14,8 +14,10 @@
 #ifndef _ASM_SYSTEM_H
 #define _ASM_SYSTEM_H
 
+#include <asm/asm.h>
 #include <asm/sgidefs.h>
 #include <asm/ptrace.h>
+#include <linux/stringify.h>
 #if 0
 #include <linux/kernel.h>
 #endif
@@ -270,4 +272,15 @@ static inline void execution_hazard_barrier(void)
 		".set reorder");
 }
 
+static inline void instruction_hazard_barrier(void)
+{
+	unsigned long tmp;
+
+	asm volatile(
+	__stringify(PTR_LA) "\t%0, 1f\n"
+	"	jr.hb	%0\n"
+	"1:	.insn"
+	: "=&r"(tmp));
+}
+
 #endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index eba7fff316..8e5b028c66 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -12,6 +12,7 @@
 #endif
 #include <asm/io.h>
 #include <asm/mipsregs.h>
+#include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -134,6 +135,9 @@ void flush_cache(ulong start_addr, ulong size)
 ops_done:
 	/* ensure cache ops complete before any further memory accesses */
 	sync();
+
+	/* ensure the pipeline doesn't contain now-invalid instructions */
+	instruction_hazard_barrier();
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
-- 
2.15.0

[U-Boot] [PATCH 3/3] MIPS: Break out of cache loops for unimplemented caches

[Paul Burton]

If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot at lists.denx.de

---

 arch/mips/lib/cache.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 8e5b028c66..e305f3207a 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -98,6 +98,9 @@ static inline unsigned long scache_line_size(void)
 	const unsigned int cache_ops[] = { ops };			\
 	unsigned int i;							\
 									\
+	if (!lsize)							\
+		break;							\
+									\
 	for (; addr <= aend; addr += lsize) {				\
 		for (i = 0; i < ARRAY_SIZE(cache_ops); i++)		\
 			mips_cache(cache_ops[i], addr);			\
@@ -125,9 +128,7 @@ void flush_cache(ulong start_addr, ulong size)
 	cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
 
 	/* flush L2 cache */
-	if (slsize)
-		cache_loop(start_addr, start_addr + size, slsize,
-			   HIT_WRITEBACK_INV_SD);
+	cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
 
 	/* flush I-cache */
 	cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
@@ -152,8 +153,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 	cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
 
 	/* flush L2 cache */
-	if (slsize)
-		cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
+	cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
 
 	/* ensure cache ops complete before any further memory accesses */
 	sync();
@@ -169,8 +169,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		return;
 
 	/* invalidate L2 cache */
-	if (slsize)
-		cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
+	cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
 
 	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 
-- 
2.15.0

[U-Boot] [PATCH 0/3] MIPS: Caching fixes

[Daniel Schwierzeck]

Am 21.11.2017 um 20:18 schrieb Paul Burton:
> This short series fixes a few issues related to our caching code - with
> regards to DMA coherence, instruction cache coherence & systems with no
> caches at all.
> 
> Applies atop u-boot-mips/next as of d7d9fc01a4ef ("Update Paul Burton's
> email address").
> 
> 
> Paul Burton (3):
>   MIPS: Ensure cache ops complete in cache maintenance functions
>   MIPS: Clear instruction hazards in flush_cache()
>   MIPS: Break out of cache loops for unimplemented caches
> 
>  arch/mips/include/asm/system.h | 13 +++++++++++++
>  arch/mips/lib/cache.c          | 30 ++++++++++++++++++++++--------
>  2 files changed, 35 insertions(+), 8 deletions(-)
> 

series applied to u-boot-mips, thanks.

Do you have further patches for this merge windows? I'll wait with the
pull request then.

-- 
- Daniel

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[U-Boot] [PATCH 0/3] MIPS: Caching fixes

[Paul Burton]

Hi Daniel,

On Tue, Nov 21, 2017 at 08:57:15PM +0100, Daniel Schwierzeck wrote:
> Am 21.11.2017 um 20:18 schrieb Paul Burton:
> > This short series fixes a few issues related to our caching code - with
> > regards to DMA coherence, instruction cache coherence & systems with no
> > caches at all.
> > 
> > Applies atop u-boot-mips/next as of d7d9fc01a4ef ("Update Paul Burton's
> > email address").
> > 
> > 
> > Paul Burton (3):
> >   MIPS: Ensure cache ops complete in cache maintenance functions
> >   MIPS: Clear instruction hazards in flush_cache()
> >   MIPS: Break out of cache loops for unimplemented caches
> > 
> >  arch/mips/include/asm/system.h | 13 +++++++++++++
> >  arch/mips/lib/cache.c          | 30 ++++++++++++++++++++++--------
> >  2 files changed, 35 insertions(+), 8 deletions(-)
> > 
> 
> series applied to u-boot-mips, thanks.

Great - thanks for your prompt response :)

> Do you have further patches for this merge windows? I'll wait with the
> pull request then.

I have some patches for Boston which I've been tidying up & am just
waiting on buildman to finish testing, but they do touch other areas
than arch/mips & board/imgtec/boston so I'll understand if you don't
want to hold things up on waiting for reviews.

I also have a port to the SEAD-3 platform, another development board we
use for smaller cores, which is in fairly good shape but similarly would
need review from some others.

Thanks,
    Paul