* [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop.
@ 2017-11-23 15:03 Chris Wilson
2017-11-23 19:52 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Chris Wilson @ 2017-11-23 15:03 UTC (permalink / raw)
To: intel-gfx
We have to be careful in our calibration loop, too slow and we timeout,
too fast and we don't emit an interrupt! On fast legacy devices, we
would overflow the calibration calcuation...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/perf_pmu.c | 112 ++++++++++++++++++++++++++-----------------------------
1 file changed, 52 insertions(+), 60 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index c699fb00..b8800e61 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -40,6 +40,7 @@
#include "igt_core.h"
#include "igt_perf.h"
#include "igt_sysfs.h"
+#include "sw_sync.h"
IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
@@ -802,18 +803,18 @@ static void cpu_hotplug(int gem_fd)
assert_within_epsilon(val, ref, tolerance);
}
-static unsigned long calibrate_nop(int fd, const unsigned int calibration_us)
+static unsigned long calibrate_nop(int fd, const uint64_t calibration_us)
{
- const unsigned int cal_min_us = calibration_us * 3;
+ const uint64_t cal_min_us = calibration_us * 3;
const unsigned int tolerance_pct = 10;
const uint32_t bbe = MI_BATCH_BUFFER_END;
const unsigned int loops = 17;
struct drm_i915_gem_exec_object2 obj = {};
- struct drm_i915_gem_execbuffer2 eb =
- { .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1, .buffers_ptr = to_user_pointer(&obj),
+ };
struct timespec t_begin = { };
- long size, last_size;
- unsigned long ns;
+ uint64_t size, last_size, ns;
igt_nsec_elapsed(&t_begin);
@@ -843,81 +844,72 @@ static unsigned long calibrate_nop(int fd, const unsigned int calibration_us)
} while (igt_nsec_elapsed(&t_begin) / 1000 < cal_min_us ||
abs(size - last_size) > (size * tolerance_pct / 100));
- return size / sizeof(uint32_t);
+ return size;
}
-static void exec_nop(int gem_fd, unsigned long sz)
+static void
+test_interrupts(int gem_fd)
{
- struct drm_i915_gem_exec_object2 obj = {};
- struct drm_i915_gem_execbuffer2 eb =
- { .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 obj = { };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = I915_EXEC_FENCE_OUT,
+ };
+ unsigned long sz;
+ igt_spin_t *spin;
+ const int target = 30;
struct pollfd pfd;
- int fence;
+ uint64_t idle, busy;
+ int fd;
- sz = ALIGN(sz, sizeof(uint32_t));
+ sz = calibrate_nop(gem_fd, 1e6 / target);
+ gem_quiescent_gpu(gem_fd);
+
+ fd = open_pmu(I915_PMU_INTERRUPTS);
+ spin = igt_spin_batch_new(gem_fd, 0, 0, 0);
obj.handle = gem_create(gem_fd, sz);
gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe, sizeof(bbe));
- eb.flags = I915_EXEC_RENDER | I915_EXEC_FENCE_OUT;
-
- gem_execbuf_wr(gem_fd, &eb);
- fence = eb.rsvd2 >> 32;
+ pfd.fd = -1;
+ for (int i = 0; i < target; i++) {
+ int new;
- /*
- * Poll on the output fence to ensure user interrupts will be
- * generated and listened to.
- */
- pfd.fd = fence;
- pfd.events = POLLIN;
- igt_assert_eq(poll(&pfd, 1, -1), 1);
-
- close(fence);
- gem_close(gem_fd, obj.handle);
-}
-
-static void
-test_interrupts(int gem_fd)
-{
- const unsigned int calibration_us = 250000;
- const unsigned int batch_len_us = 100000;
- const unsigned int batch_count = 3e6 / batch_len_us;
- uint64_t idle, busy, prev;
- unsigned long cal, sz;
- unsigned int i;
- int fd;
-
- fd = open_pmu(I915_PMU_INTERRUPTS);
-
- cal = calibrate_nop(gem_fd, calibration_us);
- sz = batch_len_us * cal / calibration_us;
-
- gem_quiescent_gpu(gem_fd);
+ /* Merge all the fences together so we can wait on them all */
+ gem_execbuf_wr(gem_fd, &eb);
+ new = eb.rsvd2 >> 32;
+ if (pfd.fd == -1) {
+ pfd.fd = new;
+ } else {
+ int old = pfd.fd;
+ pfd.fd = sync_fence_merge(old, new);
+ close(old);
+ close(new);
+ }
+ }
/* Wait for idle state. */
- prev = pmu_read_single(fd);
- idle = prev + 1;
- while (idle != prev) {
- usleep(1e6);
- prev = idle;
+ idle = pmu_read_single(fd);
+ do {
+ busy = idle;
+ usleep(1e3);
idle = pmu_read_single(fd);
- }
+ } while (idle != busy);
- igt_assert_eq(idle - prev, 0);
+ pfd.events = POLLIN;
+ igt_assert_eq(poll(&pfd, 1, 10), 0);
- /*
- * Send some no-op batches waiting on output fences to
- * ensure interrupts.
- */
- for (i = 0; i < batch_count; i++)
- exec_nop(gem_fd, sz);
+ igt_spin_batch_free(gem_fd, spin);
+ igt_assert_eq(poll(&pfd, 1, 2000), 1);
+ close(pfd.fd);
/* Check at least as many interrupts has been generated. */
busy = pmu_read_single(fd) - idle;
close(fd);
- igt_assert(busy >= batch_count);
+ igt_assert_lte(target, busy);
}
static void
--
2.15.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for igt/perf_pmu: Recalibrate interrupt loop.
2017-11-23 15:03 [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop Chris Wilson
@ 2017-11-23 19:52 ` Patchwork
2017-11-23 23:33 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-11-24 9:11 ` [PATCH igt] " Tvrtko Ursulin
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-11-23 19:52 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: igt/perf_pmu: Recalibrate interrupt loop.
URL : https://patchwork.freedesktop.org/series/34310/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
a1e444f4c8178acb590d41c21e921c6447668be4 tests/perf_pmu: Bump measuring duration for semaphores as well
with latest DRM-Tip kernel build CI_DRM_3378
b407e5f38397 drm-tip: 2017y-11m-23d-16h-14m-59s UTC integration manifest
No testlist changes.
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS (fi-cfl-s2)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:459s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:461s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:543s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:279s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:506s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:502s
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:491s
fi-cfl-s2 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:612s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:265s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:548s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:431s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:440s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:429s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:484s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:464s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:587s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:456s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:541s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:571s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:518s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:507s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:465s
fi-snb-2520m total:246 pass:212 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:425s
Blacklisted hosts:
fi-cnl-y total:253 pass:226 dwarn:0 dfail:0 fail:1 skip:25
fi-glk-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:495s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:495s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:531s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:481s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:534s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_545/
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^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: failure for igt/perf_pmu: Recalibrate interrupt loop.
2017-11-23 15:03 [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop Chris Wilson
2017-11-23 19:52 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-11-23 23:33 ` Patchwork
2017-11-24 9:11 ` [PATCH igt] " Tvrtko Ursulin
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-11-23 23:33 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: igt/perf_pmu: Recalibrate interrupt loop.
URL : https://patchwork.freedesktop.org/series/34310/
State : failure
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
Test kms_flip:
Subgroup vblank-vs-modeset-suspend:
pass -> DMESG-WARN (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass -> FAIL (shard-snb) fdo#101623
Subgroup fbc-suspend:
pass -> FAIL (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2667 pass:1535 dwarn:1 dfail:0 fail:10 skip:1121 time:9570s
shard-snb total:2667 pass:1311 dwarn:2 dfail:0 fail:13 skip:1341 time:8129s
Blacklisted hosts:
shard-kbl total:2667 pass:1804 dwarn:1 dfail:0 fail:23 skip:839 time:10931s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_545/shards.html
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop.
2017-11-23 15:03 [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop Chris Wilson
2017-11-23 19:52 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-23 23:33 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-11-24 9:11 ` Tvrtko Ursulin
2017-11-24 9:28 ` Chris Wilson
2 siblings, 1 reply; 7+ messages in thread
From: Tvrtko Ursulin @ 2017-11-24 9:11 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 23/11/2017 15:03, Chris Wilson wrote:
> We have to be careful in our calibration loop, too slow and we timeout,
> too fast and we don't emit an interrupt! On fast legacy devices, we
> would overflow the calibration calcuation...
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/perf_pmu.c | 112 ++++++++++++++++++++++++++-----------------------------
> 1 file changed, 52 insertions(+), 60 deletions(-)
>
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index c699fb00..b8800e61 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -40,6 +40,7 @@
> #include "igt_core.h"
> #include "igt_perf.h"
> #include "igt_sysfs.h"
> +#include "sw_sync.h"
>
> IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
>
> @@ -802,18 +803,18 @@ static void cpu_hotplug(int gem_fd)
> assert_within_epsilon(val, ref, tolerance);
> }
>
> -static unsigned long calibrate_nop(int fd, const unsigned int calibration_us)
> +static unsigned long calibrate_nop(int fd, const uint64_t calibration_us)
> {
> - const unsigned int cal_min_us = calibration_us * 3;
> + const uint64_t cal_min_us = calibration_us * 3;
> const unsigned int tolerance_pct = 10;
> const uint32_t bbe = MI_BATCH_BUFFER_END;
> const unsigned int loops = 17;
> struct drm_i915_gem_exec_object2 obj = {};
> - struct drm_i915_gem_execbuffer2 eb =
> - { .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1, .buffers_ptr = to_user_pointer(&obj),
> + };
> struct timespec t_begin = { };
> - long size, last_size;
> - unsigned long ns;
> + uint64_t size, last_size, ns;
>
> igt_nsec_elapsed(&t_begin);
>
> @@ -843,81 +844,72 @@ static unsigned long calibrate_nop(int fd, const unsigned int calibration_us)
> } while (igt_nsec_elapsed(&t_begin) / 1000 < cal_min_us ||
> abs(size - last_size) > (size * tolerance_pct / 100));
>
> - return size / sizeof(uint32_t);
> + return size;
Ah.. I did not spot this at all.. strange..
> }
>
> -static void exec_nop(int gem_fd, unsigned long sz)
> +static void
> +test_interrupts(int gem_fd)
> {
> - struct drm_i915_gem_exec_object2 obj = {};
> - struct drm_i915_gem_execbuffer2 eb =
> - { .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
> const uint32_t bbe = MI_BATCH_BUFFER_END;
> + struct drm_i915_gem_exec_object2 obj = { };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffers_ptr = to_user_pointer(&obj),
> + .buffer_count = 1,
> + .flags = I915_EXEC_FENCE_OUT,
> + };
> + unsigned long sz;
> + igt_spin_t *spin;
> + const int target = 30;
> struct pollfd pfd;
> - int fence;
> + uint64_t idle, busy;
> + int fd;
>
> - sz = ALIGN(sz, sizeof(uint32_t));
> + sz = calibrate_nop(gem_fd, 1e6 / target);
> + gem_quiescent_gpu(gem_fd);
> +
> + fd = open_pmu(I915_PMU_INTERRUPTS);
> + spin = igt_spin_batch_new(gem_fd, 0, 0, 0);
What's the spin batch for?
>
> obj.handle = gem_create(gem_fd, sz);
> gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe, sizeof(bbe));
>
> - eb.flags = I915_EXEC_RENDER | I915_EXEC_FENCE_OUT;
> -
> - gem_execbuf_wr(gem_fd, &eb);
> - fence = eb.rsvd2 >> 32;
> + pfd.fd = -1;
> + for (int i = 0; i < target; i++) {
> + int new;
>
> - /*
> - * Poll on the output fence to ensure user interrupts will be
> - * generated and listened to.
> - */
> - pfd.fd = fence;
> - pfd.events = POLLIN;
> - igt_assert_eq(poll(&pfd, 1, -1), 1);
> -
> - close(fence);
> - gem_close(gem_fd, obj.handle);
> -}
> -
> -static void
> -test_interrupts(int gem_fd)
> -{
> - const unsigned int calibration_us = 250000;
> - const unsigned int batch_len_us = 100000;
> - const unsigned int batch_count = 3e6 / batch_len_us;
> - uint64_t idle, busy, prev;
> - unsigned long cal, sz;
> - unsigned int i;
> - int fd;
> -
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> -
> - cal = calibrate_nop(gem_fd, calibration_us);
> - sz = batch_len_us * cal / calibration_us;
> -
> - gem_quiescent_gpu(gem_fd);
> + /* Merge all the fences together so we can wait on them all */
> + gem_execbuf_wr(gem_fd, &eb);
> + new = eb.rsvd2 >> 32;
> + if (pfd.fd == -1) {
> + pfd.fd = new;
> + } else {
> + int old = pfd.fd;
> + pfd.fd = sync_fence_merge(old, new);
> + close(old);
> + close(new);
> + }
> + }
>
> /* Wait for idle state. */
> - prev = pmu_read_single(fd);
> - idle = prev + 1;
> - while (idle != prev) {
> - usleep(1e6);
> - prev = idle;
> + idle = pmu_read_single(fd);
> + do {
> + busy = idle;
> + usleep(1e3);
> idle = pmu_read_single(fd);
> - }
> + } while (idle != busy);
>
> - igt_assert_eq(idle - prev, 0);
> + pfd.events = POLLIN;
> + igt_assert_eq(poll(&pfd, 1, 10), 0);
>
> - /*
> - * Send some no-op batches waiting on output fences to
> - * ensure interrupts.
> - */
> - for (i = 0; i < batch_count; i++)
> - exec_nop(gem_fd, sz);
> + igt_spin_batch_free(gem_fd, spin);
> + igt_assert_eq(poll(&pfd, 1, 2000), 1);
> + close(pfd.fd);
>
> /* Check at least as many interrupts has been generated. */
> busy = pmu_read_single(fd) - idle;
> close(fd);
>
> - igt_assert(busy >= batch_count);
> + igt_assert_lte(target, busy);
> }
>
> static void
>
Rest looks good.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop.
2017-11-24 9:11 ` [PATCH igt] " Tvrtko Ursulin
@ 2017-11-24 9:28 ` Chris Wilson
2017-11-24 9:52 ` Tvrtko Ursulin
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2017-11-24 9:28 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2017-11-24 09:11:06)
>
> On 23/11/2017 15:03, Chris Wilson wrote:
> > We have to be careful in our calibration loop, too slow and we timeout,
> > too fast and we don't emit an interrupt! On fast legacy devices, we
> > would overflow the calibration calcuation...
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > - sz = ALIGN(sz, sizeof(uint32_t));
> > + sz = calibrate_nop(gem_fd, 1e6 / target);
> > + gem_quiescent_gpu(gem_fd);
> > +
> > + fd = open_pmu(I915_PMU_INTERRUPTS);
> > + spin = igt_spin_batch_new(gem_fd, 0, 0, 0);
>
> What's the spin batch for?
It's just a plug to ensure that the queue of calibrated execs don't start
executing before we're waiting on them. Instead of doing exec + sync, we
want to switch to exec[N] + sync.
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop.
2017-11-24 9:28 ` Chris Wilson
@ 2017-11-24 9:52 ` Tvrtko Ursulin
2017-11-24 10:40 ` Chris Wilson
0 siblings, 1 reply; 7+ messages in thread
From: Tvrtko Ursulin @ 2017-11-24 9:52 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 24/11/2017 09:28, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-11-24 09:11:06)
>>
>> On 23/11/2017 15:03, Chris Wilson wrote:
>>> We have to be careful in our calibration loop, too slow and we timeout,
>>> too fast and we don't emit an interrupt! On fast legacy devices, we
>>> would overflow the calibration calcuation...
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>> - sz = ALIGN(sz, sizeof(uint32_t));
>>> + sz = calibrate_nop(gem_fd, 1e6 / target);
>>> + gem_quiescent_gpu(gem_fd);
>>> +
>>> + fd = open_pmu(I915_PMU_INTERRUPTS);
>>> + spin = igt_spin_batch_new(gem_fd, 0, 0, 0);
>>
>> What's the spin batch for?
>
> It's just a plug to ensure that the queue of calibrated execs don't start
> executing before we're waiting on them. Instead of doing exec + sync, we
> want to switch to exec[N] + sync.
Of course, makes sense.
Only improvement I can think of is to define the target time (1e6) and
poll timeout (2000ms) from a common local variable.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop.
2017-11-24 9:52 ` Tvrtko Ursulin
@ 2017-11-24 10:40 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2017-11-24 10:40 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2017-11-24 09:52:23)
>
> On 24/11/2017 09:28, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-11-24 09:11:06)
> >>
> >> On 23/11/2017 15:03, Chris Wilson wrote:
> >>> We have to be careful in our calibration loop, too slow and we timeout,
> >>> too fast and we don't emit an interrupt! On fast legacy devices, we
> >>> would overflow the calibration calcuation...
> >>>
> >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>> ---
> >>> - sz = ALIGN(sz, sizeof(uint32_t));
> >>> + sz = calibrate_nop(gem_fd, 1e6 / target);
> >>> + gem_quiescent_gpu(gem_fd);
> >>> +
> >>> + fd = open_pmu(I915_PMU_INTERRUPTS);
> >>> + spin = igt_spin_batch_new(gem_fd, 0, 0, 0);
> >>
> >> What's the spin batch for?
> >
> > It's just a plug to ensure that the queue of calibrated execs don't start
> > executing before we're waiting on them. Instead of doing exec + sync, we
> > want to switch to exec[N] + sync.
>
> Of course, makes sense.
>
> Only improvement I can think of is to define the target time (1e6) and
> poll timeout (2000ms) from a common local variable.
Called it test_duration_ms. Thanks,
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
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-- links below jump to the message on this page --
2017-11-23 15:03 [PATCH igt] igt/perf_pmu: Recalibrate interrupt loop Chris Wilson
2017-11-23 19:52 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-23 23:33 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-11-24 9:11 ` [PATCH igt] " Tvrtko Ursulin
2017-11-24 9:28 ` Chris Wilson
2017-11-24 9:52 ` Tvrtko Ursulin
2017-11-24 10:40 ` Chris Wilson
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