* [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass
@ 2017-11-23 17:05 Cédric Le Goater
2017-11-24 0:09 ` David Gibson
0 siblings, 1 reply; 4+ messages in thread
From: Cédric Le Goater @ 2017-11-23 17:05 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson; +Cc: Cédric Le Goater
and use the value to define precisely the default value of the LPCR in
the helper routine cpu_ppc_set_papr()
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu-qom.h | 1 +
target/ppc/translate_init.c | 23 +++++++++++------------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 429b47f959dc..deaa46a14b2e 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -191,6 +191,7 @@ typedef struct PowerPCCPUClass {
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
+ uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
powerpc_input_t bus_model;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index b9c49c22f29f..828d7e778c3b 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8535,6 +8535,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8704,6 +8705,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
}
#ifdef CONFIG_SOFTMMU
@@ -8898,11 +8901,13 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
@@ -8932,8 +8937,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
lpcr->default_value &= ~LPCR_RMLS;
lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
- switch (env->mmu_model) {
- case POWERPC_MMU_3_00:
+ if (env->mmu_model == POWERPC_MMU_3_00) {
/* By default we choose legacy mode and switch to new hash or radix
* when a register process table hcall is made. So disable process
* tables and guest translation shootdown by default
@@ -8947,18 +8951,13 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
} else {
lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
}
- lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
- LPCR_OEE;
- break;
- default:
- /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
- * bit 47 and 48 which are reserved on P7. Here we set them all, which
- * will work as expected for both implementations
- */
- lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
}
+ /* Also set the power-saving mode bits which depend on the CPU
+ * family
+ */
+ lpcr->default_value |= pcc->lpcr_pm;
+
/* We should be followed by a CPU reset but update the active value
* just in case...
*/
--
2.13.6
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass
2017-11-23 17:05 [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass Cédric Le Goater
@ 2017-11-24 0:09 ` David Gibson
2017-11-24 7:04 ` Cédric Le Goater
0 siblings, 1 reply; 4+ messages in thread
From: David Gibson @ 2017-11-24 0:09 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 536 bytes --]
On Thu, Nov 23, 2017 at 06:05:24PM +0100, Cédric Le Goater wrote:
> and use the value to define precisely the default value of the LPCR in
> the helper routine cpu_ppc_set_papr()
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to ppc-for-2.12.
Sorry, I forgot if we needed this for 2.11 - if so, I can move it
over.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass
2017-11-24 0:09 ` David Gibson
@ 2017-11-24 7:04 ` Cédric Le Goater
2017-11-24 11:12 ` David Gibson
0 siblings, 1 reply; 4+ messages in thread
From: Cédric Le Goater @ 2017-11-24 7:04 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel
On 11/24/2017 01:09 AM, David Gibson wrote:
> On Thu, Nov 23, 2017 at 06:05:24PM +0100, Cédric Le Goater wrote:
>> and use the value to define precisely the default value of the LPCR in
>> the helper routine cpu_ppc_set_papr()
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Applied to ppc-for-2.12.
>
> Sorry, I forgot if we needed this for 2.11 - if so, I can move it
> over.
The next patchset fixes reboot and CPU hotplug under TCG.
But we are 10 days before 2.11, TCG is clearly not the most
used accelerators for sPAPR, I am the only one complaining
about it because of XIVE. I Let you decide.
Sending the v4 of ""disable the decrementer interrupt when a
CPU is unplugged" now.
Thanks,
C.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass
2017-11-24 7:04 ` Cédric Le Goater
@ 2017-11-24 11:12 ` David Gibson
0 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2017-11-24 11:12 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1135 bytes --]
On Fri, Nov 24, 2017 at 08:04:59AM +0100, Cédric Le Goater wrote:
> On 11/24/2017 01:09 AM, David Gibson wrote:
> > On Thu, Nov 23, 2017 at 06:05:24PM +0100, Cédric Le Goater wrote:
> >> and use the value to define precisely the default value of the LPCR in
> >> the helper routine cpu_ppc_set_papr()
> >>
> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >
> > Applied to ppc-for-2.12.
> >
> > Sorry, I forgot if we needed this for 2.11 - if so, I can move it
> > over.
>
> The next patchset fixes reboot and CPU hotplug under TCG.
>
> But we are 10 days before 2.11, TCG is clearly not the most
> used accelerators for sPAPR, I am the only one complaining
> about it because of XIVE. I Let you decide.
Ah, yes, I remember now.
Yeah, 2.12 it is. I'm already squeezing in quite enough late fixes
for 2.11 :/.
> Sending the v4 of ""disable the decrementer interrupt when a
> CPU is unplugged" now.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-11-23 17:05 [Qemu-devel] [PATCH] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass Cédric Le Goater
2017-11-24 0:09 ` David Gibson
2017-11-24 7:04 ` Cédric Le Goater
2017-11-24 11:12 ` David Gibson
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