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* [PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
@ 2017-11-20 16:26 ` Yazen Ghannam
  0 siblings, 0 replies; 6+ messages in thread
From: Yazen Ghannam @ 2017-11-20 16:26 UTC (permalink / raw)
  To: linux-edac; +Cc: Yazen Ghannam, Borislav Petkov, Tony Luck, x86, linux-kernel

From: Yazen Ghannam <yazen.ghannam@amd.com>

The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e4e27adedc81..32008a8d293f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	    (deferred_error_int_vector != amd_deferred_error_interrupt))
 		deferred_error_int_vector = amd_deferred_error_interrupt;
 
-	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+	if (!mce_flags.smca)
+		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 
-- 
2.14.1

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
@ 2017-11-20 16:26 ` Yazen Ghannam
  0 siblings, 0 replies; 6+ messages in thread
From: Yazen Ghannam @ 2017-11-20 16:26 UTC (permalink / raw)
  To: linux-edac; +Cc: Yazen Ghannam, Borislav Petkov, Tony Luck, x86, linux-kernel

From: Yazen Ghannam <yazen.ghannam@amd.com>

The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e4e27adedc81..32008a8d293f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	    (deferred_error_int_vector != amd_deferred_error_interrupt))
 		deferred_error_int_vector = amd_deferred_error_interrupt;
 
-	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+	if (!mce_flags.smca)
+		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
@ 2017-11-27 10:36   ` Borislav Petkov
  0 siblings, 0 replies; 6+ messages in thread
From: Borislav Petkov @ 2017-11-27 10:36 UTC (permalink / raw)
  To: Yazen Ghannam; +Cc: linux-edac, Borislav Petkov, Tony Luck, x86, linux-kernel

On Mon, Nov 20, 2017 at 10:26:46AM -0600, Yazen Ghannam wrote:
> From: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
> is used on SMCA systems to set the LVT offset for the Threshold and
> Deferred error interrupts.
> 
> This register was used on non-SMCA systems to also set the Deferred
> interrupt type in bits 2:1. However, these bits are reserved on SMCA
> systems.
> 
> Only set MSRC000_0410[2:1] on non-SMCA systems.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> index e4e27adedc81..32008a8d293f 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> @@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
>  	    (deferred_error_int_vector != amd_deferred_error_interrupt))
>  		deferred_error_int_vector = amd_deferred_error_interrupt;
>  
> -	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> +	if (!mce_flags.smca)
> +		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> +
>  	wrmsr(MSR_CU_DEF_ERR, low, high);
>  }
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

^ permalink raw reply	[flat|nested] 6+ messages in thread
* x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
@ 2017-11-27 10:36   ` Borislav Petkov
  0 siblings, 0 replies; 6+ messages in thread
From: Borislav Petkov @ 2017-11-27 10:36 UTC (permalink / raw)
  To: Yazen Ghannam; +Cc: linux-edac, Borislav Petkov, Tony Luck, x86, linux-kernel

On Mon, Nov 20, 2017 at 10:26:46AM -0600, Yazen Ghannam wrote:
> From: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
> is used on SMCA systems to set the LVT offset for the Threshold and
> Deferred error interrupts.
> 
> This register was used on non-SMCA systems to also set the Deferred
> interrupt type in bits 2:1. However, these bits are reserved on SMCA
> systems.
> 
> Only set MSRC000_0410[2:1] on non-SMCA systems.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> index e4e27adedc81..32008a8d293f 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> @@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
>  	    (deferred_error_int_vector != amd_deferred_error_interrupt))
>  		deferred_error_int_vector = amd_deferred_error_interrupt;
>  
> -	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> +	if (!mce_flags.smca)
> +		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> +
>  	wrmsr(MSR_CU_DEF_ERR, low, high);
>  }
>  
> -- 

Applied, thanks.

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [tip:ras/core] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
@ 2017-12-04 19:44   ` tip-bot for Borislav Petkov
  0 siblings, 0 replies; 6+ messages in thread
From: tip-bot for Yazen Ghannam @ 2017-12-04 19:44 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: bp, tony.luck, tglx, yazen.ghannam, hpa, mingo, linux-kernel, linux-edac

Commit-ID:  c8a4364c33ac7ed63278267b8f6d8c15810d5fd1
Gitweb:     https://git.kernel.org/tip/c8a4364c33ac7ed63278267b8f6d8c15810d5fd1
Author:     Yazen Ghannam <yazen.ghannam@amd.com>
AuthorDate: Mon, 4 Dec 2017 17:54:38 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 4 Dec 2017 20:38:44 +0100

x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

The McaIntrCfg register (MSRC000_0410), previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20171120162646.5210-1-Yazen.Ghannam@amd.com

---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 486f640..a38ab1f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -407,7 +407,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	    (deferred_error_int_vector != amd_deferred_error_interrupt))
 		deferred_error_int_vector = amd_deferred_error_interrupt;
 
-	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+	if (!mce_flags.smca)
+		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [tip:ras/core] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
@ 2017-12-04 19:44   ` tip-bot for Borislav Petkov
  0 siblings, 0 replies; 6+ messages in thread
From: tip-bot for Borislav Petkov @ 2017-12-04 19:44 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: bp, tony.luck, tglx, yazen.ghannam, hpa, mingo, linux-kernel, linux-edac

Commit-ID:  c8a4364c33ac7ed63278267b8f6d8c15810d5fd1
Gitweb:     https://git.kernel.org/tip/c8a4364c33ac7ed63278267b8f6d8c15810d5fd1
Author:     Yazen Ghannam <yazen.ghannam@amd.com>
AuthorDate: Mon, 4 Dec 2017 17:54:38 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 4 Dec 2017 20:38:44 +0100

x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

The McaIntrCfg register (MSRC000_0410), previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20171120162646.5210-1-Yazen.Ghannam@amd.com
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

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diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 486f640..a38ab1f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -407,7 +407,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	    (deferred_error_int_vector != amd_deferred_error_interrupt))
 		deferred_error_int_vector = amd_deferred_error_interrupt;
 
-	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+	if (!mce_flags.smca)
+		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 

^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-12-04 19:45 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-20 16:26 [PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems Yazen Ghannam
2017-11-20 16:26 ` Yazen Ghannam
2017-11-27 10:36 ` [PATCH] " Borislav Petkov
2017-11-27 10:36   ` Borislav Petkov
2017-12-04 19:44 ` [tip:ras/core] " tip-bot for Yazen Ghannam
2017-12-04 19:44   ` tip-bot for Borislav Petkov

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