* [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles
@ 2017-11-28 22:05 Lucas De Marchi
2017-11-28 22:35 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Lucas De Marchi @ 2017-11-28 22:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Arthur J Runyan, Lucas De Marchi, Rodrigo Vivi
Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. Although it is for type C, HW engineers reported
that it can be applied to all external ports even if they are not going
to type C.
For CNL we apply the workaround every time Aux B, C and D are powering
up since they will lose the configuration when powered down.
v2: Use common tag for WA
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bf043c1c2e..0214327d8af7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8335,6 +8335,17 @@ enum skl_power_gate {
#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
+#define _CNL_AUX_REG_IDX(pw) ((pw - 1) >> 4)
+#define _CNL_AUX_ANAOVRD1_B 0x162250
+#define _CNL_AUX_ANAOVRD1_C 0x162210
+#define _CNL_AUX_ANAOVRD1_D 0x1622D0
+#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
+ _CNL_AUX_ANAOVRD1_B, \
+ _CNL_AUX_ANAOVRD1_C, \
+ _CNL_AUX_ANAOVRD1_D))
+#define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
+#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8315499452dc..29f14e724f41 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -388,6 +388,15 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
hsw_wait_for_power_well_enable(dev_priv, power_well);
+ /* Display WA #1178: cnl */
+ if (IS_CANNONLAKE(dev_priv) &&
+ (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
+ id == CNL_DISP_PW_AUX_D)) {
+ val = I915_READ(CNL_AUX_ANAOVRD1(id));
+ val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
+ I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
+ }
+
if (wait_fuses)
gen9_wait_for_power_well_fuses(dev_priv, pg);
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: apply Display WA #1178 to fix type C dongles
2017-11-28 22:05 [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
@ 2017-11-28 22:35 ` Patchwork
2017-11-29 8:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-18 19:39 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-11-28 22:35 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: apply Display WA #1178 to fix type C dongles
URL : https://patchwork.freedesktop.org/series/34566/
State : success
== Summary ==
Series 34566v1 drm/i915/cnl: apply Display WA #1178 to fix type C dongles
https://patchwork.freedesktop.org/api/1.0/series/34566/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:439s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:379s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:511s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:278s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:497s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:499s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:479s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:467s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:419s
fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:266s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:533s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:369s
fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:256s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:425s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:481s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:479s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:527s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:473s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:527s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:596s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:447s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:538s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:563s
fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:513s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:498s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:416s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:607s
fi-cnl-y total:272 pass:245 dwarn:0 dfail:0 fail:0 skip:26
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:498s
5144438448829ec2a3d94fd16a9e69a52cfa7b3b drm-tip: 2017y-11m-28d-17h-04m-56s UTC integration manifest
a0ec9ac8817a drm/i915/cnl: apply Display WA #1178 to fix type C dongles
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7331/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnl: apply Display WA #1178 to fix type C dongles
2017-11-28 22:05 [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2017-11-28 22:35 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-11-29 8:28 ` Patchwork
2018-01-18 19:39 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-11-29 8:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: apply Display WA #1178 to fix type C dongles
URL : https://patchwork.freedesktop.org/series/34566/
State : success
== Summary ==
Blacklisted hosts:
shard-apl total:2458 pass:1522 dwarn:23 dfail:16 fail:13 skip:877 time:11304s
shard-hsw total:2635 pass:1512 dwarn:9 dfail:0 fail:10 skip:1103 time:8851s
shard-kbl total:2394 pass:1584 dwarn:24 dfail:10 fail:16 skip:754 time:8972s
shard-snb total:2575 pass:1252 dwarn:16 dfail:4 fail:6 skip:1294 time:7719s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7331/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles
2017-11-28 22:05 [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2017-11-28 22:35 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-29 8:28 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-01-18 19:39 ` Rodrigo Vivi
2018-01-18 19:53 ` Rodrigo Vivi
2 siblings, 1 reply; 5+ messages in thread
From: Rodrigo Vivi @ 2018-01-18 19:39 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Arthur J Runyan
On Tue, Nov 28, 2017 at 10:05:53PM +0000, Lucas De Marchi wrote:
> Display WA #1178 is meant to fix Aux channel voltage swing too low with
> some type C dongles. Although it is for type C, HW engineers reported
> that it can be applied to all external ports even if they are not going
> to type C.
>
> For CNL we apply the workaround every time Aux B, C and D are powering
> up since they will lose the configuration when powered down.
>
> v2: Use common tag for WA
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
we got all confirmations that we need. Thanks Art.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09bf043c1c2e..0214327d8af7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8335,6 +8335,17 @@ enum skl_power_gate {
> #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
> #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
>
> +#define _CNL_AUX_REG_IDX(pw) ((pw - 1) >> 4)
> +#define _CNL_AUX_ANAOVRD1_B 0x162250
> +#define _CNL_AUX_ANAOVRD1_C 0x162210
> +#define _CNL_AUX_ANAOVRD1_D 0x1622D0
> +#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
> + _CNL_AUX_ANAOVRD1_B, \
> + _CNL_AUX_ANAOVRD1_C, \
> + _CNL_AUX_ANAOVRD1_D))
> +#define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
> +#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
> +
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 8315499452dc..29f14e724f41 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -388,6 +388,15 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> + /* Display WA #1178: cnl */
> + if (IS_CANNONLAKE(dev_priv) &&
> + (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
> + id == CNL_DISP_PW_AUX_D)) {
> + val = I915_READ(CNL_AUX_ANAOVRD1(id));
> + val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> + I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
> + }
> +
> if (wait_fuses)
> gen9_wait_for_power_well_fuses(dev_priv, pg);
>
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles
2018-01-18 19:39 ` [PATCH] " Rodrigo Vivi
@ 2018-01-18 19:53 ` Rodrigo Vivi
0 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2018-01-18 19:53 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Arthur J Runyan
On Thu, Jan 18, 2018 at 07:39:51PM +0000, Rodrigo Vivi wrote:
> On Tue, Nov 28, 2017 at 10:05:53PM +0000, Lucas De Marchi wrote:
> > Display WA #1178 is meant to fix Aux channel voltage swing too low with
> > some type C dongles. Although it is for type C, HW engineers reported
> > that it can be applied to all external ports even if they are not going
> > to type C.
> >
> > For CNL we apply the workaround every time Aux B, C and D are powering
> > up since they will lose the configuration when powered down.
> >
> > v2: Use common tag for WA
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> we got all confirmations that we need. Thanks Art.
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
merged. Thanks for the patch.
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++
> > 2 files changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 09bf043c1c2e..0214327d8af7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8335,6 +8335,17 @@ enum skl_power_gate {
> > #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
> > #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
> >
> > +#define _CNL_AUX_REG_IDX(pw) ((pw - 1) >> 4)
> > +#define _CNL_AUX_ANAOVRD1_B 0x162250
> > +#define _CNL_AUX_ANAOVRD1_C 0x162210
> > +#define _CNL_AUX_ANAOVRD1_D 0x1622D0
> > +#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
> > + _CNL_AUX_ANAOVRD1_B, \
> > + _CNL_AUX_ANAOVRD1_C, \
> > + _CNL_AUX_ANAOVRD1_D))
> > +#define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
> > +#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
> > +
> > /* Per-pipe DDI Function Control */
> > #define _TRANS_DDI_FUNC_CTL_A 0x60400
> > #define _TRANS_DDI_FUNC_CTL_B 0x61400
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 8315499452dc..29f14e724f41 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -388,6 +388,15 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> > I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
> > hsw_wait_for_power_well_enable(dev_priv, power_well);
> >
> > + /* Display WA #1178: cnl */
> > + if (IS_CANNONLAKE(dev_priv) &&
> > + (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
> > + id == CNL_DISP_PW_AUX_D)) {
> > + val = I915_READ(CNL_AUX_ANAOVRD1(id));
> > + val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> > + I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
> > + }
> > +
> > if (wait_fuses)
> > gen9_wait_for_power_well_fuses(dev_priv, pg);
> >
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-01-18 19:53 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-28 22:05 [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2017-11-28 22:35 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-29 8:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-18 19:39 ` [PATCH] " Rodrigo Vivi
2018-01-18 19:53 ` Rodrigo Vivi
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.