From: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org, ralf@linux-mips.org, James Hogan <james.hogan@mips.com>, netdev@vger.kernel.org, "David S. Miller" <davem@davemloft.net>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, devel@driverdev.osuosl.org, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-kernel@vger.kernel.org, "Steven J. Hill" <steven.hill@cavium.com>, devicetree@vger.kernel.org, Andrew Lunn <andrew@lunn.ch>, Florian Fainelli <f.fainelli@gmail.com>, Carlos Munoz <cmunoz@cavium.com>, "Steven J . Hill" <Steven.Hill@cavium.com>, David Daney <david.daney@cavium.com> Subject: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations. Date: Tue, 28 Nov 2017 16:55:34 -0800 [thread overview] Message-ID: <20171129005540.28829-3-david.daney@cavium.com> (raw) In-Reply-To: <20171129005540.28829-1-david.daney@cavium.com> From: Carlos Munoz <cmunoz@cavium.com> LMTDMA/LMTST operations move data between cores and I/O devices: * LMTST operations can send an address and a variable length (up to 128 bytes) of data to an I/O device. * LMTDMA operations can send an address and a variable length (up to 128) of data to the I/O device and then return a variable length (up to 128 bytes) response from the IOI device. Signed-off-by: Carlos Munoz <cmunoz@cavium.com> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/cavium-octeon/setup.c | 6 ++++++ arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index a8034d0dcade..99e6a68bc652 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -609,6 +609,12 @@ void octeon_user_io_init(void) #else cvmmemctl.s.cvmsegenak = 0; #endif + if (OCTEON_IS_OCTEON3()) { + /* Enable LMTDMA */ + cvmmemctl.s.lmtena = 1; + /* Scratch line to use for LMT operation */ + cvmmemctl.s.lmtline = 2; + } /* R/W If set, CVMSEG is available for loads/stores in * supervisor mode. */ cvmmemctl.s.cvmsegenas = 0; diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index c99c4b6a79f4..92a17d67c1fa 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -179,7 +179,15 @@ union octeon_cvmemctl { /* RO 1 = BIST fail, 0 = BIST pass */ __BITFIELD_FIELD(uint64_t wbfbist:1, /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved:17, + __BITFIELD_FIELD(uint64_t reserved_52_57:6, + /* When set, LMTDMA/LMTST operations are permitted */ + __BITFIELD_FIELD(uint64_t lmtena:1, + /* Selects the CVMSEG LM cacheline used by LMTDMA + * LMTST and wide atomic store operations. + */ + __BITFIELD_FIELD(uint64_t lmtline:6, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_41_44:4, /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU. * This field selects between the TLB replacement policies: * bitmask LRU or NLU. Bitmask LRU maintains a mask of @@ -275,7 +283,7 @@ union octeon_cvmemctl { /* R/W Size of local memory in cache blocks, 54 (6912 * bytes) is max legal value. */ __BITFIELD_FIELD(uint64_t lmemsz:6, - ;))))))))))))))))))))))))))))))))) + ;)))))))))))))))))))))))))))))))))))) } s; }; -- 2.14.3
WARNING: multiple messages have this Message-ID (diff)
From: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org, ralf@linux-mips.org, James Hogan <james.hogan@mips.com>, netdev@vger.kernel.org, "David S. Miller" <davem@davemloft.net>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, devel@driverdev.osuosl.org, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devicetree@vger.kernel.org, Florian Fainelli <f.fainelli@gmail.com>, Andrew Lunn <andrew@lunn.ch>, David Daney <david.daney@cavium.com>, linux-kernel@vger.kernel.org, Carlos Munoz <cmunoz@cavium.com>, "Steven J . Hill" <Steven.Hill@cavium.com> Subject: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations. Date: Tue, 28 Nov 2017 16:55:34 -0800 [thread overview] Message-ID: <20171129005540.28829-3-david.daney@cavium.com> (raw) In-Reply-To: <20171129005540.28829-1-david.daney@cavium.com> From: Carlos Munoz <cmunoz@cavium.com> LMTDMA/LMTST operations move data between cores and I/O devices: * LMTST operations can send an address and a variable length (up to 128 bytes) of data to an I/O device. * LMTDMA operations can send an address and a variable length (up to 128) of data to the I/O device and then return a variable length (up to 128 bytes) response from the IOI device. Signed-off-by: Carlos Munoz <cmunoz@cavium.com> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/cavium-octeon/setup.c | 6 ++++++ arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index a8034d0dcade..99e6a68bc652 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -609,6 +609,12 @@ void octeon_user_io_init(void) #else cvmmemctl.s.cvmsegenak = 0; #endif + if (OCTEON_IS_OCTEON3()) { + /* Enable LMTDMA */ + cvmmemctl.s.lmtena = 1; + /* Scratch line to use for LMT operation */ + cvmmemctl.s.lmtline = 2; + } /* R/W If set, CVMSEG is available for loads/stores in * supervisor mode. */ cvmmemctl.s.cvmsegenas = 0; diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index c99c4b6a79f4..92a17d67c1fa 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -179,7 +179,15 @@ union octeon_cvmemctl { /* RO 1 = BIST fail, 0 = BIST pass */ __BITFIELD_FIELD(uint64_t wbfbist:1, /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved:17, + __BITFIELD_FIELD(uint64_t reserved_52_57:6, + /* When set, LMTDMA/LMTST operations are permitted */ + __BITFIELD_FIELD(uint64_t lmtena:1, + /* Selects the CVMSEG LM cacheline used by LMTDMA + * LMTST and wide atomic store operations. + */ + __BITFIELD_FIELD(uint64_t lmtline:6, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_41_44:4, /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU. * This field selects between the TLB replacement policies: * bitmask LRU or NLU. Bitmask LRU maintains a mask of @@ -275,7 +283,7 @@ union octeon_cvmemctl { /* R/W Size of local memory in cache blocks, 54 (6912 * bytes) is max legal value. */ __BITFIELD_FIELD(uint64_t lmemsz:6, - ;))))))))))))))))))))))))))))))))) + ;)))))))))))))))))))))))))))))))))))) } s; }; -- 2.14.3
next prev parent reply other threads:[~2017-11-29 0:59 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-11-29 0:55 [PATCH v4 0/8] Cavium OCTEON-III network driver David Daney 2017-11-29 0:55 ` David Daney 2017-11-29 0:55 ` [PATCH v4 1/8] dt-bindings: Add Cavium Octeon Common Ethernet Interface David Daney 2017-11-29 0:55 ` David Daney 2017-11-29 2:01 ` Andrew Lunn 2017-11-29 2:01 ` Andrew Lunn 2017-11-29 2:54 ` David Daney 2017-11-29 0:55 ` David Daney [this message] 2017-11-29 0:55 ` [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations David Daney 2017-11-30 21:36 ` James Hogan 2017-11-30 21:36 ` James Hogan 2017-11-30 21:36 ` James Hogan 2017-11-30 21:49 ` David Daney 2017-11-30 21:49 ` David Daney 2017-11-30 22:56 ` James Hogan 2017-11-30 22:56 ` James Hogan 2017-11-30 23:09 ` David Daney 2017-11-30 23:09 ` David Daney 2017-11-30 23:12 ` James Hogan 2017-11-30 23:12 ` James Hogan 2017-11-30 23:12 ` James Hogan 2017-11-30 23:12 ` James Hogan 2017-11-29 0:55 ` [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager David Daney 2017-11-30 22:53 ` James Hogan 2017-11-30 22:53 ` James Hogan 2017-11-30 22:53 ` James Hogan 2017-11-30 22:53 ` James Hogan 2017-12-01 1:51 ` David Daney 2017-12-01 1:51 ` David Daney 2017-12-01 7:53 ` Philippe Ombredanne 2017-12-01 7:53 ` Philippe Ombredanne 2017-12-01 17:42 ` David Daney 2017-12-01 17:42 ` David Daney 2017-12-01 19:49 ` Philippe Ombredanne 2017-12-01 19:49 ` Philippe Ombredanne 2017-12-01 20:01 ` David Daney 2017-12-01 20:01 ` David Daney 2017-12-01 20:41 ` Philippe Ombredanne 2017-12-01 20:41 ` Philippe Ombredanne 2017-12-01 20:56 ` David Daney 2017-12-01 20:56 ` David Daney 2017-12-01 20:56 ` David Daney 2017-12-01 23:33 ` Philippe Ombredanne 2017-12-01 23:33 ` Philippe Ombredanne 2017-12-01 23:33 ` Philippe Ombredanne 2017-11-29 0:55 ` [PATCH v4 4/8] MIPS: Octeon: Add Free Pointer Unit (FPA) support David Daney 2017-11-29 0:55 ` David Daney 2017-11-29 0:55 ` David Daney 2017-11-29 0:55 ` [PATCH v4 5/8] MIPS: Octeon: Automatically provision CVMSEG space David Daney 2017-11-29 0:55 ` David Daney 2017-11-29 0:55 ` [PATCH v4 6/8] staging: octeon: Remove USE_ASYNC_IOBDMA macro David Daney 2017-11-29 0:55 ` David Daney 2017-12-07 14:28 ` Greg Kroah-Hartman 2017-12-07 14:28 ` Greg Kroah-Hartman 2017-11-29 0:55 ` [PATCH v4 7/8] netdev: octeon-ethernet: Add Cavium Octeon III support David Daney 2017-11-29 10:30 ` Souptick Joarder 2017-11-29 10:30 ` Souptick Joarder 2017-11-29 13:47 ` Andrew Lunn 2017-11-29 13:47 ` Andrew Lunn 2017-11-29 16:07 ` Souptick Joarder 2017-11-29 16:07 ` Souptick Joarder 2017-11-29 19:11 ` Dan Carpenter 2017-11-29 19:11 ` Dan Carpenter 2017-11-29 22:16 ` Andrew Lunn 2017-11-29 22:16 ` Andrew Lunn 2017-11-29 19:20 ` David Daney 2017-11-29 19:20 ` David Daney 2017-11-30 7:12 ` Souptick Joarder 2017-11-29 22:56 ` Andrew Lunn 2017-11-29 22:56 ` Andrew Lunn 2017-11-29 23:04 ` David Daney 2017-11-29 23:04 ` David Daney 2017-11-29 0:55 ` [PATCH v4 8/8] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-* David Daney 2017-11-29 0:55 ` David Daney 2017-11-29 14:18 ` [PATCH v4 0/8] Cavium OCTEON-III network driver David Miller 2017-11-29 14:18 ` David Miller
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