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From: Peter Zijlstra <peterz@infradead.org>
To: Jan Dakinevich <jan.dakinevich@virtuozzo.com>
Cc: linux-kernel@vger.kernel.org,
	"Denis V . Lunev" <den@virtuozzo.com>,
	"Roman Kagan" <rkagan@virtuozzo.com>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Arnaldo Carvalho de Melo" <acme@kernel.org>,
	"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
	"Jiri Olsa" <jolsa@redhat.com>,
	"Namhyung Kim" <namhyung@kernel.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>,
	"Andi Kleen" <ak@linux.intel.com>,
	"Kan Liang" <kan.liang@intel.com>,
	"Stephane Eranian" <eranian@google.com>,
	"Zhou Chengming" <zhouchengming1@huawei.com>,
	"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
	"Colin King" <colin.king@canonical.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jin Yao" <yao.jin@linux.intel.com>,
	kvm@vger.kernel.org
Subject: Re: [PATCH RFC 1/2] perf/x86/intel: make reusable LBR initialization code
Date: Wed, 6 Dec 2017 13:51:14 +0100	[thread overview]
Message-ID: <20171206125114.jfp56mhmvbugqpan@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1512560585-27263-2-git-send-email-jan.dakinevich@virtuozzo.com>

On Wed, Dec 06, 2017 at 02:43:02PM +0300, Jan Dakinevich wrote:
> This patch introduces globally visible intel_pmu_lbr_fill() routine,
> which gathers information which LBR MSRs are support for specific CPU
> family/model.
> 
> It is supposed that the routine would be used in KVM code, using guest
> CPU information as an input. By this reason, it should not have any side
> effect which could affect host system.
> 
>  * LBR information moved to separate structure `struct x86_pmu_lbr';
>  * All family-specific tweaks on gathered information are applied only
>    for global x86_pmu.lbr to keep current perf initialization behavior.
> 
> Signed-off-by: Jan Dakinevich <jan.dakinevich@virtuozzo.com>

Hurch, that's a lot of churn. Nothing bad stood out though.

WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org>
To: Jan Dakinevich <jan.dakinevich@virtuozzo.com>
Cc: linux-kernel@vger.kernel.org,
	"Denis V . Lunev" <den@virtuozzo.com>,
	"Roman Kagan" <rkagan@virtuozzo.com>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Arnaldo Carvalho de Melo" <acme@kernel.org>,
	"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
	"Jiri Olsa" <jolsa@redhat.com>,
	"Namhyung Kim" <namhyung@kernel.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>,
	"Andi Kleen" <ak@linux.intel.com>,
	"Kan Liang" <kan.liang@intel.com>,
	"Stephane Eranian" <eranian@google.com>,
	"Zhou Chengming" <zhouchengming1@huawei.com>,
	"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
	"Colin King" <colin.king@canonical.com>,
	"Greg Kroah-Hartman" <gregkh@linu>
Subject: Re: [PATCH RFC 1/2] perf/x86/intel: make reusable LBR initialization code
Date: Wed, 6 Dec 2017 13:51:14 +0100	[thread overview]
Message-ID: <20171206125114.jfp56mhmvbugqpan@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1512560585-27263-2-git-send-email-jan.dakinevich@virtuozzo.com>

On Wed, Dec 06, 2017 at 02:43:02PM +0300, Jan Dakinevich wrote:
> This patch introduces globally visible intel_pmu_lbr_fill() routine,
> which gathers information which LBR MSRs are support for specific CPU
> family/model.
> 
> It is supposed that the routine would be used in KVM code, using guest
> CPU information as an input. By this reason, it should not have any side
> effect which could affect host system.
> 
>  * LBR information moved to separate structure `struct x86_pmu_lbr';
>  * All family-specific tweaks on gathered information are applied only
>    for global x86_pmu.lbr to keep current perf initialization behavior.
> 
> Signed-off-by: Jan Dakinevich <jan.dakinevich@virtuozzo.com>

Hurch, that's a lot of churn. Nothing bad stood out though.

  reply	other threads:[~2017-12-06 12:51 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-06 11:43 [PATCH RFC 0/2] ignore LBR-related MSRs Jan Dakinevich
2017-12-06 11:43 ` Jan Dakinevich
2017-12-06 11:43 ` [PATCH RFC 1/2] perf/x86/intel: make reusable LBR initialization code Jan Dakinevich
2017-12-06 11:43   ` Jan Dakinevich
2017-12-06 12:51   ` Peter Zijlstra [this message]
2017-12-06 12:51     ` Peter Zijlstra
2017-12-06 11:43 ` [PATCH RFC 2/2] KVM: x86/vPMU: ignore access to LBR-related MSRs Jan Dakinevich
2017-12-06 11:43   ` Jan Dakinevich
2017-12-06 12:52   ` Peter Zijlstra
2017-12-06 15:57   ` Andi Kleen
2017-12-06 17:02     ` Jan Dakinevich
2017-12-06 17:55       ` Andi Kleen
2017-12-06 15:06 ` [PATCH RFC 0/2] ignore " Konrad Rzeszutek Wilk
2017-12-06 15:06   ` Konrad Rzeszutek Wilk
2017-12-06 16:39   ` Jan Dakinevich
2017-12-06 16:39     ` Jan Dakinevich
2017-12-06 16:45     ` Denis V. Lunev
2017-12-06 16:45       ` Denis V. Lunev
2017-12-06 16:23 ` Jiri Olsa
2017-12-06 16:23   ` Jiri Olsa
2017-12-20 16:26 ` Jan Dakinevich
2017-12-20 16:26   ` Jan Dakinevich

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