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From: Mark Rutland <mark.rutland@arm.com>
To: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
	ard.biesheuvel@linaro.org, sboyd@codeaurora.org,
	dave.hansen@linux.intel.com, keescook@chromium.org,
	msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de
Subject: Re: [PATCH v3 19/20] arm64: mm: Introduce TTBR_ASID_MASK for getting at the ASID in the TTBR
Date: Wed, 6 Dec 2017 14:12:47 +0000	[thread overview]
Message-ID: <20171206141247.jwcu3hgda4ieembr@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <1512563739-25239-20-git-send-email-will.deacon@arm.com>

On Wed, Dec 06, 2017 at 12:35:38PM +0000, Will Deacon wrote:
> There are now a handful of open-coded masks to extract the ASID from a
> TTBR value, so introduce a TTBR_ASID_MASK and use that instead.
> 
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>

Thanks!

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/include/asm/asm-uaccess.h | 3 ++-
>  arch/arm64/include/asm/mmu.h         | 1 +
>  arch/arm64/include/asm/uaccess.h     | 4 ++--
>  arch/arm64/kernel/entry.S            | 2 +-
>  4 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
> index 21b8cf304028..f4f234b6155e 100644
> --- a/arch/arm64/include/asm/asm-uaccess.h
> +++ b/arch/arm64/include/asm/asm-uaccess.h
> @@ -4,6 +4,7 @@
>  
>  #include <asm/alternative.h>
>  #include <asm/kernel-pgtable.h>
> +#include <asm/mmu.h>
>  #include <asm/sysreg.h>
>  #include <asm/assembler.h>
>  
> @@ -17,7 +18,7 @@
>  	msr	ttbr0_el1, \tmp1		// set reserved TTBR0_EL1
>  	isb
>  	sub	\tmp1, \tmp1, #SWAPPER_DIR_SIZE
> -	bic	\tmp1, \tmp1, #(0xffff << 48)
> +	bic	\tmp1, \tmp1, #TTBR_ASID_MASK
>  	msr	ttbr1_el1, \tmp1		// set reserved ASID
>  	isb
>  	.endm
> diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
> index da6f12e40714..6f7bdb89817f 100644
> --- a/arch/arm64/include/asm/mmu.h
> +++ b/arch/arm64/include/asm/mmu.h
> @@ -18,6 +18,7 @@
>  
>  #define MMCF_AARCH32	0x1	/* mm context flag for AArch32 executables */
>  #define USER_ASID_FLAG	(UL(1) << 48)
> +#define TTBR_ASID_MASK	(UL(0xffff) << 48)
>  
>  #ifndef __ASSEMBLY__
>  
> diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
> index 750a3b76a01c..6eadf55ebaf0 100644
> --- a/arch/arm64/include/asm/uaccess.h
> +++ b/arch/arm64/include/asm/uaccess.h
> @@ -112,7 +112,7 @@ static inline void __uaccess_ttbr0_disable(void)
>  	write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1);
>  	isb();
>  	/* Set reserved ASID */
> -	ttbr &= ~(0xffffUL << 48);
> +	ttbr &= ~TTBR_ASID_MASK;
>  	write_sysreg(ttbr, ttbr1_el1);
>  	isb();
>  }
> @@ -131,7 +131,7 @@ static inline void __uaccess_ttbr0_enable(void)
>  
>  	/* Restore active ASID */
>  	ttbr1 = read_sysreg(ttbr1_el1);
> -	ttbr1 |= ttbr0 & (0xffffUL << 48);
> +	ttbr1 |= ttbr0 & TTBR_ASID_MASK;
>  	write_sysreg(ttbr1, ttbr1_el1);
>  	isb();
>  
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 5d51bdbb2131..3eabcb194c87 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -205,7 +205,7 @@ alternative_else_nop_endif
>  
>  	.if	\el != 0
>  	mrs	x21, ttbr1_el1
> -	tst	x21, #0xffff << 48		// Check for the reserved ASID
> +	tst	x21, #TTBR_ASID_MASK		// Check for the reserved ASID
>  	orr	x23, x23, #PSR_PAN_BIT		// Set the emulated PAN in the saved SPSR
>  	b.eq	1f				// TTBR0 access already disabled
>  	and	x23, x23, #~PSR_PAN_BIT		// Clear the emulated PAN in the saved SPSR
> -- 
> 2.1.4
> 

WARNING: multiple messages have this Message-ID (diff)
From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 19/20] arm64: mm: Introduce TTBR_ASID_MASK for getting at the ASID in the TTBR
Date: Wed, 6 Dec 2017 14:12:47 +0000	[thread overview]
Message-ID: <20171206141247.jwcu3hgda4ieembr@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <1512563739-25239-20-git-send-email-will.deacon@arm.com>

On Wed, Dec 06, 2017 at 12:35:38PM +0000, Will Deacon wrote:
> There are now a handful of open-coded masks to extract the ASID from a
> TTBR value, so introduce a TTBR_ASID_MASK and use that instead.
> 
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>

Thanks!

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/include/asm/asm-uaccess.h | 3 ++-
>  arch/arm64/include/asm/mmu.h         | 1 +
>  arch/arm64/include/asm/uaccess.h     | 4 ++--
>  arch/arm64/kernel/entry.S            | 2 +-
>  4 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
> index 21b8cf304028..f4f234b6155e 100644
> --- a/arch/arm64/include/asm/asm-uaccess.h
> +++ b/arch/arm64/include/asm/asm-uaccess.h
> @@ -4,6 +4,7 @@
>  
>  #include <asm/alternative.h>
>  #include <asm/kernel-pgtable.h>
> +#include <asm/mmu.h>
>  #include <asm/sysreg.h>
>  #include <asm/assembler.h>
>  
> @@ -17,7 +18,7 @@
>  	msr	ttbr0_el1, \tmp1		// set reserved TTBR0_EL1
>  	isb
>  	sub	\tmp1, \tmp1, #SWAPPER_DIR_SIZE
> -	bic	\tmp1, \tmp1, #(0xffff << 48)
> +	bic	\tmp1, \tmp1, #TTBR_ASID_MASK
>  	msr	ttbr1_el1, \tmp1		// set reserved ASID
>  	isb
>  	.endm
> diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
> index da6f12e40714..6f7bdb89817f 100644
> --- a/arch/arm64/include/asm/mmu.h
> +++ b/arch/arm64/include/asm/mmu.h
> @@ -18,6 +18,7 @@
>  
>  #define MMCF_AARCH32	0x1	/* mm context flag for AArch32 executables */
>  #define USER_ASID_FLAG	(UL(1) << 48)
> +#define TTBR_ASID_MASK	(UL(0xffff) << 48)
>  
>  #ifndef __ASSEMBLY__
>  
> diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
> index 750a3b76a01c..6eadf55ebaf0 100644
> --- a/arch/arm64/include/asm/uaccess.h
> +++ b/arch/arm64/include/asm/uaccess.h
> @@ -112,7 +112,7 @@ static inline void __uaccess_ttbr0_disable(void)
>  	write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1);
>  	isb();
>  	/* Set reserved ASID */
> -	ttbr &= ~(0xffffUL << 48);
> +	ttbr &= ~TTBR_ASID_MASK;
>  	write_sysreg(ttbr, ttbr1_el1);
>  	isb();
>  }
> @@ -131,7 +131,7 @@ static inline void __uaccess_ttbr0_enable(void)
>  
>  	/* Restore active ASID */
>  	ttbr1 = read_sysreg(ttbr1_el1);
> -	ttbr1 |= ttbr0 & (0xffffUL << 48);
> +	ttbr1 |= ttbr0 & TTBR_ASID_MASK;
>  	write_sysreg(ttbr1, ttbr1_el1);
>  	isb();
>  
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 5d51bdbb2131..3eabcb194c87 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -205,7 +205,7 @@ alternative_else_nop_endif
>  
>  	.if	\el != 0
>  	mrs	x21, ttbr1_el1
> -	tst	x21, #0xffff << 48		// Check for the reserved ASID
> +	tst	x21, #TTBR_ASID_MASK		// Check for the reserved ASID
>  	orr	x23, x23, #PSR_PAN_BIT		// Set the emulated PAN in the saved SPSR
>  	b.eq	1f				// TTBR0 access already disabled
>  	and	x23, x23, #~PSR_PAN_BIT		// Clear the emulated PAN in the saved SPSR
> -- 
> 2.1.4
> 

  reply	other threads:[~2017-12-06 14:12 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-06 12:35 [PATCH v3 00/20] arm64: Unmap the kernel whilst running in userspace (KPTI) Will Deacon
2017-12-06 12:35 ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 01/20] arm64: mm: Use non-global mappings for kernel space Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 02/20] arm64: mm: Temporarily disable ARM64_SW_TTBR0_PAN Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 03/20] arm64: mm: Move ASID from TTBR0 to TTBR1 Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 04/20] arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003 Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 05/20] arm64: mm: Rename post_ttbr0_update_workaround Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 06/20] arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN Will Deacon
2017-12-06 12:35   ` Will Deacon
2018-01-17  2:58   ` Yisheng Xie
2018-01-17  2:58     ` Yisheng Xie
2017-12-06 12:35 ` [PATCH v3 07/20] arm64: mm: Allocate ASIDs in pairs Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 08/20] arm64: mm: Add arm64_kernel_unmapped_at_el0 helper Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 09/20] arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 10/20] arm64: entry: Add exception trampoline page for exceptions from EL0 Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 11/20] arm64: mm: Map entry trampoline into trampoline and kernel page tables Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 14:32   ` Mark Rutland
2017-12-06 14:32     ` Mark Rutland
2018-01-23  8:28   ` Yisheng Xie
2018-01-23  8:28     ` Yisheng Xie
2018-01-23 10:04     ` Will Deacon
2018-01-23 10:04       ` Will Deacon
2018-01-23 10:43       ` Yisheng Xie
2018-01-23 10:43         ` Yisheng Xie
2017-12-06 12:35 ` [PATCH v3 12/20] arm64: entry: Explicitly pass exception level to kernel_ventry macro Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 13/20] arm64: entry: Hook up entry trampoline to exception vectors Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 14/20] arm64: erratum: Work around Falkor erratum #E1003 in trampoline code Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 15/20] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 16/20] arm64: entry: Add fake CPU feature for unmapping the kernel at EL0 Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 14:11   ` Mark Rutland
2017-12-06 14:11     ` Mark Rutland
2017-12-06 12:35 ` [PATCH v3 17/20] arm64: Kconfig: Add CONFIG_UNMAP_KERNEL_AT_EL0 Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:35 ` [PATCH v3 18/20] perf: arm_spe: Fail device probe when arm64_kernel_unmapped_at_el0() Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 13:34   ` Mark Rutland
2017-12-06 13:34     ` Mark Rutland
2017-12-06 12:35 ` [PATCH v3 19/20] arm64: mm: Introduce TTBR_ASID_MASK for getting at the ASID in the TTBR Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 14:12   ` Mark Rutland [this message]
2017-12-06 14:12     ` Mark Rutland
2017-12-06 12:35 ` [PATCH v3 20/20] arm64: kaslr: Put kernel vectors address in separate data page Will Deacon
2017-12-06 12:35   ` Will Deacon
2017-12-06 12:59   ` Ard Biesheuvel
2017-12-06 12:59     ` Ard Biesheuvel
2017-12-06 13:27     ` Will Deacon
2017-12-06 13:27       ` Will Deacon
2017-12-06 14:03       ` Ard Biesheuvel
2017-12-06 14:03         ` Ard Biesheuvel
2017-12-08  0:40 ` [PATCH v3 00/20] arm64: Unmap the kernel whilst running in userspace (KPTI) Laura Abbott
2017-12-08  0:40   ` Laura Abbott
2017-12-11 13:23   ` Will Deacon
2017-12-11 13:23     ` Will Deacon
2017-12-11 17:59 ` Catalin Marinas
2017-12-11 17:59   ` Catalin Marinas
2018-01-04  5:17   ` Florian Fainelli
2018-01-04  5:17     ` Florian Fainelli
2018-01-04  6:50     ` Greg Kroah-Hartman
2018-01-04  6:50       ` Greg Kroah-Hartman
2018-01-04 18:23       ` Florian Fainelli
2018-01-04 18:23         ` Florian Fainelli
2018-01-04 23:27         ` Russell King - ARM Linux
2018-01-04 23:27           ` Russell King - ARM Linux
2018-01-05 16:06         ` Greg Kroah-Hartman
2018-01-05 16:06           ` Greg Kroah-Hartman
2018-01-05 16:12           ` Ard Biesheuvel
2018-01-05 16:12             ` Ard Biesheuvel

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