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* [PATCH] x86/mce: Do Deferred error check for CEC
@ 2017-12-12 16:51 ` Yazen Ghannam
  0 siblings, 0 replies; 5+ messages in thread
From: Yazen Ghannam @ 2017-12-12 16:51 UTC (permalink / raw)
  To: linux-edac; +Cc: Yazen Ghannam, Borislav Petkov, Tony Luck, x86, linux-kernel

From: Yazen Ghannam <yazen.ghannam@amd.com>

AMD systems may log Deferred errors. These are errors that are uncorrected
but which do not need immediate action. The MCA_STATUS[UC] bit may not be
set for Deferred errors.

Flag the error as not correctable when MCA_STATUS[Deferred] is set.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: stable@vger.kernel.org # 4.13.x
---
 arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 321c7a80be66..1b2c11473376 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -528,6 +528,17 @@ bool mce_is_memory_error(struct mce *m)
 }
 EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
+static bool mce_is_correctable(struct mce *m)
+{
+	if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
+		return false;
+
+	if (m->status & MCI_STATUS_UC)
+		return false;
+
+	return true;
+}
+
 static bool cec_add_mce(struct mce *m)
 {
 	if (!m)
@@ -535,7 +546,7 @@ static bool cec_add_mce(struct mce *m)
 
 	/* We eat only correctable DRAM errors with usable addresses. */
 	if (mce_is_memory_error(m) &&
-	    !(m->status & MCI_STATUS_UC) &&
+	    mce_is_correctable(m)  &&
 	    mce_usable_address(m))
 		if (!cec_add_elem(m->addr >> PAGE_SHIFT))
 			return true;
-- 
2.14.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* x86/mce: Do Deferred error check for CEC
@ 2017-12-12 16:51 ` Yazen Ghannam
  0 siblings, 0 replies; 5+ messages in thread
From: Yazen Ghannam @ 2017-12-12 16:51 UTC (permalink / raw)
  To: linux-edac; +Cc: Yazen Ghannam, Borislav Petkov, Tony Luck, x86, linux-kernel

From: Yazen Ghannam <yazen.ghannam@amd.com>

AMD systems may log Deferred errors. These are errors that are uncorrected
but which do not need immediate action. The MCA_STATUS[UC] bit may not be
set for Deferred errors.

Flag the error as not correctable when MCA_STATUS[Deferred] is set.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: stable@vger.kernel.org # 4.13.x
---
 arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 321c7a80be66..1b2c11473376 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -528,6 +528,17 @@ bool mce_is_memory_error(struct mce *m)
 }
 EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
+static bool mce_is_correctable(struct mce *m)
+{
+	if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
+		return false;
+
+	if (m->status & MCI_STATUS_UC)
+		return false;
+
+	return true;
+}
+
 static bool cec_add_mce(struct mce *m)
 {
 	if (!m)
@@ -535,7 +546,7 @@ static bool cec_add_mce(struct mce *m)
 
 	/* We eat only correctable DRAM errors with usable addresses. */
 	if (mce_is_memory_error(m) &&
-	    !(m->status & MCI_STATUS_UC) &&
+	    mce_is_correctable(m)  &&
 	    mce_usable_address(m))
 		if (!cec_add_elem(m->addr >> PAGE_SHIFT))
 			return true;

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] x86/mce: Do Deferred error check for CEC
@ 2017-12-13 22:15   ` Borislav Petkov
  0 siblings, 0 replies; 5+ messages in thread
From: Borislav Petkov @ 2017-12-13 22:15 UTC (permalink / raw)
  To: Yazen Ghannam; +Cc: linux-edac, Tony Luck, x86, linux-kernel

On Tue, Dec 12, 2017 at 10:51:43AM -0600, Yazen Ghannam wrote:
> From: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> AMD systems may log Deferred errors. These are errors that are uncorrected
> but which do not need immediate action. The MCA_STATUS[UC] bit may not be
> set for Deferred errors.
> 
> Flag the error as not correctable when MCA_STATUS[Deferred] is set.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Cc: stable@vger.kernel.org # 4.13.x
> ---
>  arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

^ permalink raw reply	[flat|nested] 5+ messages in thread
* x86/mce: Do Deferred error check for CEC
@ 2017-12-13 22:15   ` Borislav Petkov
  0 siblings, 0 replies; 5+ messages in thread
From: Borislav Petkov @ 2017-12-13 22:15 UTC (permalink / raw)
  To: Yazen Ghannam; +Cc: linux-edac, Tony Luck, x86, linux-kernel

On Tue, Dec 12, 2017 at 10:51:43AM -0600, Yazen Ghannam wrote:
> From: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> AMD systems may log Deferred errors. These are errors that are uncorrected
> but which do not need immediate action. The MCA_STATUS[UC] bit may not be
> set for Deferred errors.
> 
> Flag the error as not correctable when MCA_STATUS[Deferred] is set.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Cc: stable@vger.kernel.org # 4.13.x
> ---
>  arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)

Applied, thanks.

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [tip:ras/core] x86/MCE: Make correctable error detection look at the Deferred bit
  2017-12-12 16:51 ` Yazen Ghannam
  (?)
  (?)
@ 2017-12-18 12:01 ` tip-bot for Yazen Ghannam
  -1 siblings, 0 replies; 5+ messages in thread
From: tip-bot for Yazen Ghannam @ 2017-12-18 12:01 UTC (permalink / raw)
  To: linux-tip-commits; +Cc: mingo, tglx, bp, linux-kernel, yazen.ghannam, hpa

Commit-ID:  179eb850ac57c06edaed67fc744ba9d902172f96
Gitweb:     https://git.kernel.org/tip/179eb850ac57c06edaed67fc744ba9d902172f96
Author:     Yazen Ghannam <yazen.ghannam@amd.com>
AuthorDate: Mon, 18 Dec 2017 12:37:14 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 18 Dec 2017 12:58:29 +0100

x86/MCE: Make correctable error detection look at the Deferred bit

AMD systems may log Deferred errors. These are errors that are uncorrected
but which do not need immediate action. The MCA_STATUS[UC] bit may not be
set for Deferred errors.

Flag the error as not correctable when MCA_STATUS[Deferred] is set and
do not feed it into the Correctable Errors Collector.

[ bp: Massage commit message. ]

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20171212165143.27475-1-Yazen.Ghannam@amd.com

---
 arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 321c7a80..1b2c114 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -528,6 +528,17 @@ bool mce_is_memory_error(struct mce *m)
 }
 EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
+static bool mce_is_correctable(struct mce *m)
+{
+	if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
+		return false;
+
+	if (m->status & MCI_STATUS_UC)
+		return false;
+
+	return true;
+}
+
 static bool cec_add_mce(struct mce *m)
 {
 	if (!m)
@@ -535,7 +546,7 @@ static bool cec_add_mce(struct mce *m)
 
 	/* We eat only correctable DRAM errors with usable addresses. */
 	if (mce_is_memory_error(m) &&
-	    !(m->status & MCI_STATUS_UC) &&
+	    mce_is_correctable(m)  &&
 	    mce_usable_address(m))
 		if (!cec_add_elem(m->addr >> PAGE_SHIFT))
 			return true;

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-12-18 12:02 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-12 16:51 [PATCH] x86/mce: Do Deferred error check for CEC Yazen Ghannam
2017-12-12 16:51 ` Yazen Ghannam
2017-12-13 22:15 ` [PATCH] " Borislav Petkov
2017-12-13 22:15   ` Borislav Petkov
2017-12-18 12:01 ` [tip:ras/core] x86/MCE: Make correctable error detection look at the Deferred bit tip-bot for Yazen Ghannam

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