[PATCH i-g-t 1/3] lib/dummyload: Support returning output fence

[PATCH i-g-t 1/3] lib/dummyload: Support returning output fence

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Support creating spin batches which return an output fence using new
__igt_spin_batch_new_fence / igt_spin_batch_new_fence API.

This will be used fromthe perf_pmu@interrupts test to ensure user
interrupt generation from a batch with controlled duration.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_dummyload.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++-------
 lib/igt_dummyload.h | 10 +++++++++
 2 files changed, 67 insertions(+), 8 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index d19b4e5ea3d2..ef08ad580246 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -70,9 +70,9 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
 	reloc->write_domain = write_domains;
 }
 
-static void emit_recursive_batch(igt_spin_t *spin,
-				 int fd, uint32_t ctx, unsigned engine,
-				 uint32_t dep)
+static int emit_recursive_batch(igt_spin_t *spin,
+				int fd, uint32_t ctx, unsigned engine,
+				uint32_t dep, bool out_fence)
 {
 #define SCRATCH 0
 #define BATCH 1
@@ -87,6 +87,7 @@ static void emit_recursive_batch(igt_spin_t *spin,
 
 	nengine = 0;
 	if (engine == -1) {
+		igt_assert_eq(out_fence, false);
 		for_each_engine(fd, engine)
 			if (engine)
 				engines[nengine++] = engine;
@@ -165,22 +166,31 @@ static void emit_recursive_batch(igt_spin_t *spin,
 	execbuf.buffers_ptr = to_user_pointer(obj + (2 - execbuf.buffer_count));
 	execbuf.rsvd1 = ctx;
 
+	if (out_fence)
+		execbuf.flags = I915_EXEC_FENCE_OUT;
+	else
+		execbuf.flags = 0;
+
 	for (i = 0; i < nengine; i++) {
 		execbuf.flags &= ~ENGINE_MASK;
-		execbuf.flags = engines[i];
-		gem_execbuf(fd, &execbuf);
+		execbuf.flags |= engines[i];
+		gem_execbuf_wr(fd, &execbuf);
 	}
+
+	return out_fence ? (execbuf.rsvd2 >> 32) : -1;
 }
 
-igt_spin_t *
-__igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep)
+static igt_spin_t *
+___igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep,
+		      int out_fence)
 {
 	igt_spin_t *spin;
 
 	spin = calloc(1, sizeof(struct igt_spin));
 	igt_assert(spin);
 
-	emit_recursive_batch(spin, fd, ctx, engine, dep);
+	spin->out_fence = emit_recursive_batch(spin, fd, ctx, engine, dep,
+					       out_fence);
 	igt_assert(gem_bo_busy(fd, spin->handle));
 
 	pthread_mutex_lock(&list_lock);
@@ -190,6 +200,12 @@ __igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep)
 	return spin;
 }
 
+igt_spin_t *
+__igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep)
+{
+	return ___igt_spin_batch_new(fd, ctx, engine, dep, false);
+}
+
 /**
  * igt_spin_batch_new:
  * @fd: open i915 drm file descriptor
@@ -213,6 +229,35 @@ igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep)
 	return __igt_spin_batch_new(fd, ctx, engine, dep);
 }
 
+igt_spin_t *
+__igt_spin_batch_new_fence(int fd, uint32_t ctx, unsigned engine)
+{
+	return ___igt_spin_batch_new(fd, ctx, engine, 0, true);
+}
+
+/**
+ * igt_spin_batch_new_fence:
+ * @fd: open i915 drm file descriptor
+ * @engine: Ring to execute batch OR'd with execbuf flags. If value is less
+ *          than 0, execute on all available rings.
+ *
+ * Start a recursive batch on a ring. Immediately returns a #igt_spin_t that
+ * contains the batch's handle that can be waited upon. The returned structure
+ * must be passed to igt_spin_batch_free() for post-processing.
+ *
+ * igt_spin_t will contain an output fence associtated with this batch.
+ *
+ * Returns:
+ * Structure with helper internal state for igt_spin_batch_free().
+ */
+igt_spin_t *
+igt_spin_batch_new_fence(int fd, uint32_t ctx, unsigned engine)
+{
+	igt_require_gem(fd);
+
+	return __igt_spin_batch_new_fence(fd, ctx, engine);
+}
+
 static void notify(union sigval arg)
 {
 	igt_spin_t *spin = arg.sival_ptr;
@@ -295,6 +340,10 @@ void igt_spin_batch_free(int fd, igt_spin_t *spin)
 	gem_munmap(spin->batch, BATCH_SIZE);
 
 	gem_close(fd, spin->handle);
+
+	if (spin->out_fence >= 0)
+		close(spin->out_fence);
+
 	free(spin);
 }
 
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index 215425f7c6c0..ffa7e351dea3 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -35,6 +35,7 @@ typedef struct igt_spin {
 	timer_t timer;
 	struct igt_list link;
 	uint32_t *batch;
+	int out_fence;
 } igt_spin_t;
 
 igt_spin_t *__igt_spin_batch_new(int fd,
@@ -45,6 +46,15 @@ igt_spin_t *igt_spin_batch_new(int fd,
 			       uint32_t ctx,
 			       unsigned engine,
 			       uint32_t  dep);
+
+igt_spin_t *__igt_spin_batch_new_fence(int fd,
+				       uint32_t ctx,
+				       unsigned engine);
+
+igt_spin_t *igt_spin_batch_new_fence(int fd,
+				     uint32_t ctx,
+				     unsigned engine);
+
 void igt_spin_batch_set_timeout(igt_spin_t *spin, int64_t ns);
 void igt_spin_batch_end(igt_spin_t *spin);
 void igt_spin_batch_free(int fd, igt_spin_t *spin);
-- 
2.14.1

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[PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Rather than calibrate and emit nop batches, use a manually signalled chain
of spinners to generate the desired interrupts.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 94 ++++++++------------------------------------------------
 1 file changed, 13 insertions(+), 81 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index db7696115a7b..935fee03b253 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -799,94 +799,23 @@ static void cpu_hotplug(int gem_fd)
 	assert_within_epsilon(val, ref, tolerance);
 }
 
-static unsigned long calibrate_nop(int fd, const uint64_t calibration_us)
-{
-	const uint64_t cal_min_us = calibration_us * 3;
-	const unsigned int tolerance_pct = 10;
-	const uint32_t bbe = MI_BATCH_BUFFER_END;
-	const unsigned int loops = 17;
-	struct drm_i915_gem_exec_object2 obj = {};
-	struct drm_i915_gem_execbuffer2 eb = {
-		.buffer_count = 1, .buffers_ptr = to_user_pointer(&obj),
-	};
-	struct timespec t_begin = { };
-	uint64_t size, last_size, ns;
-
-	igt_nsec_elapsed(&t_begin);
-
-	size = 256 * 1024;
-	do {
-		struct timespec t_start = { };
-
-		obj.handle = gem_create(fd, size);
-		gem_write(fd, obj.handle, size - sizeof(bbe), &bbe,
-			  sizeof(bbe));
-		gem_execbuf(fd, &eb);
-		gem_sync(fd, obj.handle);
-
-		igt_nsec_elapsed(&t_start);
-
-		for (int loop = 0; loop < loops; loop++)
-			gem_execbuf(fd, &eb);
-		gem_sync(fd, obj.handle);
-
-		ns = igt_nsec_elapsed(&t_start);
-
-		gem_close(fd, obj.handle);
-
-		last_size = size;
-		size = calibration_us * 1000 * size * loops / ns;
-		size = ALIGN(size, sizeof(uint32_t));
-	} while (igt_nsec_elapsed(&t_begin) / 1000 < cal_min_us ||
-		 abs(size - last_size) > (size * tolerance_pct / 100));
-
-	return size;
-}
-
 static void
 test_interrupts(int gem_fd)
 {
-	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	const unsigned int test_duration_ms = 1000;
-	struct drm_i915_gem_exec_object2 obj = { };
-	struct drm_i915_gem_execbuffer2 eb = {
-		.buffers_ptr = to_user_pointer(&obj),
-		.buffer_count = 1,
-		.flags = I915_EXEC_FENCE_OUT,
-	};
-	unsigned long sz;
-	igt_spin_t *spin;
 	const int target = 30;
+	igt_spin_t *spin[target];
 	struct pollfd pfd;
 	uint64_t idle, busy;
 	int fd;
 
-	sz = calibrate_nop(gem_fd, test_duration_ms * 1000 / target);
 	gem_quiescent_gpu(gem_fd);
 
 	fd = open_pmu(I915_PMU_INTERRUPTS);
-	spin = igt_spin_batch_new(gem_fd, 0, 0, 0);
 
-	obj.handle = gem_create(gem_fd, sz);
-	gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe, sizeof(bbe));
-
-	pfd.events = POLLIN;
-	pfd.fd = -1;
-	for (int i = 0; i < target; i++) {
-		int new;
-
-		/* Merge all the fences together so we can wait on them all */
-		gem_execbuf_wr(gem_fd, &eb);
-		new = eb.rsvd2 >> 32;
-		if (pfd.fd == -1) {
-			pfd.fd = new;
-		} else {
-			int old = pfd.fd;
-			pfd.fd = sync_fence_merge(old, new);
-			close(old);
-			close(new);
-		}
-	}
+	/* Queue spinning batches. */
+	for (int i = 0; i < target; i++)
+		spin[i] = __igt_spin_batch_new_fence(gem_fd, 0, 0);
 
 	/* Wait for idle state. */
 	idle = pmu_read_single(fd);
@@ -896,13 +825,16 @@ test_interrupts(int gem_fd)
 		idle = pmu_read_single(fd);
 	} while (idle != busy);
 
-	/* Install the fences and enable signaling */
-	igt_assert_eq(poll(&pfd, 1, 10), 0);
+	/* Process the batch queue. */
+	pfd.events = POLLIN;
+	for (int i = 0; i < target; i++) {
+		const unsigned int timeout_ms = test_duration_ms / target;
 
-	/* Unplug the calibrated queue and wait for all the fences */
-	igt_spin_batch_free(gem_fd, spin);
-	igt_assert_eq(poll(&pfd, 1, 2 * test_duration_ms), 1);
-	close(pfd.fd);
+		pfd.fd = spin[i]->out_fence;
+		igt_spin_batch_set_timeout(spin[i], timeout_ms * 1e6);
+		igt_assert_eq(poll(&pfd, 1, 2 * timeout_ms), 1);
+		igt_spin_batch_free(gem_fd, spin[i]);
+	}
 
 	/* Check at least as many interrupts has been generated. */
 	busy = pmu_read_single(fd) - idle;
-- 
2.14.1

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[PATCH i-g-t 3/3] tests/perf_pmu: Verify engine busyness accuracy

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A subtest to verify that the engine busyness is reported with expected
accuracy on platforms where the feature is available.

We test three patterns: 2%, 50% and 98% load per engine.

v2:
 * Use spin batch instead of nop calibration.
 * Various tweaks.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 141 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 935fee03b253..3ca88bcc6976 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -35,6 +35,7 @@
 #include <dirent.h>
 #include <time.h>
 #include <poll.h>
+#include <sched.h>
 
 #include "igt.h"
 #include "igt_core.h"
@@ -983,6 +984,136 @@ test_rc6(int gem_fd)
 	assert_within_epsilon(busy - prev, 0.0, tolerance);
 }
 
+static uint64_t __pmu_read_single(int fd, uint64_t *ts)
+{
+	uint64_t data[2];
+
+	igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
+
+	*ts = data[1];
+
+	return data[0];
+}
+
+static double __error(double val, double ref)
+{
+	return (100.0 * val / ref) - 100.0;
+}
+
+static void debug_error(const char *str, double val, double ref)
+{
+	igt_debug("%s=%.2f%% (%.2f/%.2f)\n", str, __error(val, ref), val, ref);
+}
+
+static void log_error(const char *str, double val, double ref)
+{
+	debug_error(str, val, ref);
+	igt_info("%s=%.2f%%\n", str, __error(val, ref));
+}
+
+static void
+accuracy(int gem_fd, const struct intel_execution_engine2 *e,
+	 unsigned long target_busy_pct)
+{
+	const unsigned int test_us = 1e6;
+	unsigned long busy_us = 2500;
+	unsigned long idle_us = 100 * (busy_us - target_busy_pct *
+				busy_us / 100) / target_busy_pct;
+	double busy_r;
+	uint64_t val[2];
+	uint64_t ts[2];
+	int fd;
+
+	/* Sampling platforms cannot reach the high accuracy criteria. */
+	igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
+
+	while (idle_us < 2500) {
+		busy_us *= 2;
+		idle_us *= 2;
+	}
+
+	assert_within_epsilon((double)busy_us / (busy_us + idle_us),
+				(double)target_busy_pct / 100.0, tolerance);
+
+	/* Emit PWM pattern on the engine from a child. */
+	igt_fork(child, 1) {
+		struct sched_param rt = { .sched_priority = 99 };
+		unsigned long overhead_ns = 0;
+		unsigned long loops;
+		unsigned long i;
+
+		/* We need the best sleep accuracy we can get. */
+		igt_require(sched_setscheduler(0,
+					       SCHED_FIFO | SCHED_RESET_ON_FORK,
+					       &rt) == 0);
+
+		/* Measure setup overhead. */
+		loops = test_us / 8000;
+		for (i = 0; i < loops; i++) {
+			struct timespec start = { };
+			igt_spin_t *spin;
+			unsigned int ns;
+
+			igt_nsec_elapsed(&start);
+			spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e),
+						  0);
+			igt_spin_batch_end(spin);
+			ns = igt_nsec_elapsed(&start);
+			gem_sync(gem_fd, spin->handle);
+			igt_spin_batch_free(gem_fd, spin);
+			overhead_ns += ns;
+			usleep(1000);
+		}
+
+		overhead_ns /= test_us / loops;
+		igt_debug("spin setup overhead = %luus\n", overhead_ns / 1000);
+		igt_assert(overhead_ns < busy_us * 1000);
+
+		/* Emit PWM busy signal. */
+		loops = test_us / (busy_us + idle_us);
+		for (i = 0; i < loops; i++) {
+			struct timespec start = { };
+			igt_spin_t *spin;
+			unsigned int ns;
+
+			spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e),
+						  0);
+			ns = measured_usleep(busy_us - overhead_ns / 1000);
+			igt_spin_batch_end(spin);
+			gem_sync(gem_fd, spin->handle);
+			igt_nsec_elapsed(&start);
+			igt_spin_batch_free(gem_fd, spin);
+			debug_error("busy error", ns, busy_us * 1000);
+			ns = igt_nsec_elapsed(&start);
+
+			if (ns > idle_us * 1000)
+				ns = 0;
+			else
+				ns = idle_us;
+			ns = measured_usleep(ns);
+			debug_error("idle error", ns, idle_us * 1000);
+		}
+	}
+
+	/* Let the child run. */
+	usleep(test_us / 4);
+
+	/* Collect engine busyness for a subset of child runtime. */
+	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+	val[0] = __pmu_read_single(fd, &ts[0]);
+	usleep(test_us / 2);
+	val[1] = __pmu_read_single(fd, &ts[1]);
+	close(fd);
+
+	igt_waitchildren();
+
+	busy_r = (double)(val[1] - val[0]) / (ts[1] - ts[0]);
+
+	log_error("error", busy_r, target_busy_pct / 100.0);
+
+	assert_within_epsilon(busy_r, (double)target_busy_pct / 100.0, 0.15);
+}
+
 igt_main
 {
 	const unsigned int num_other_metrics =
@@ -1011,6 +1142,8 @@ igt_main
 		invalid_init();
 
 	for_each_engine_class_instance(fd, e) {
+		const unsigned int pct[] = { 2, 50, 98 };
+
 		/**
 		 * Test that a single engine metric can be initialized.
 		 */
@@ -1077,6 +1210,14 @@ igt_main
 		 */
 		igt_subtest_f("multi-client-%s", e->name)
 			multi_client(fd, e);
+
+		/**
+		* Check engine busyness accuracy is as expected.
+		*/
+		for (i = 0; i < ARRAY_SIZE(pct); i++) {
+			igt_subtest_f("busy-accuracy-%u-%s", pct[i], e->name)
+				accuracy(fd, e, pct[i]);
+		}
 	}
 
 	/**
-- 
2.14.1

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✓ Fi.CI.BAT: success for series starting with [1/3] lib/dummyload: Support returning output fence

[Patchwork]

== Series Details ==

Series: series starting with [1/3] lib/dummyload: Support returning output fence
URL   : https://patchwork.freedesktop.org/series/35589/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
da0889bfacff106fb3ecb7049a7a21f78b4b301b igt/kms_frontbuffer_tracking: Access via GGTT is not guaranteed to be tracked

with latest DRM-Tip kernel build CI_DRM_3549
cd7e14499b1d drm-tip: 2017y-12m-19d-15h-09m-52s UTC integration manifest

Testlist changes:
+igt@perf_pmu@busy-accuracy-2-bcs0
+igt@perf_pmu@busy-accuracy-2-rcs0
+igt@perf_pmu@busy-accuracy-2-vcs0
+igt@perf_pmu@busy-accuracy-2-vcs1
+igt@perf_pmu@busy-accuracy-2-vecs0
+igt@perf_pmu@busy-accuracy-50-bcs0
+igt@perf_pmu@busy-accuracy-50-rcs0
+igt@perf_pmu@busy-accuracy-50-vcs0
+igt@perf_pmu@busy-accuracy-50-vcs1
+igt@perf_pmu@busy-accuracy-50-vecs0
+igt@perf_pmu@busy-accuracy-98-bcs0
+igt@perf_pmu@busy-accuracy-98-rcs0
+igt@perf_pmu@busy-accuracy-98-vcs0
+igt@perf_pmu@busy-accuracy-98-vcs1
+igt@perf_pmu@busy-accuracy-98-vecs0

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-warn -> PASS       (fi-elk-e7500) fdo#103989 +1
Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                dmesg-warn -> PASS       (fi-skl-6700hq) fdo#101144

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:437s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:442s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:393s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:502s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:276s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:498s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:497s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:485s
fi-elk-e7500     total:224  pass:163  dwarn:15  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:178  dwarn:1   dfail:0   fail:1   skip:108 time:262s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:532s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:404s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:420s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:397s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:480s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:425s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:479s
fi-kbl-7560u     total:288  pass:268  dwarn:1   dfail:0   fail:0   skip:19  time:517s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:467s
fi-kbl-r         total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:526s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:587s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:447s
fi-skl-6600u     total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  time:530s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:559s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:509s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:503s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:444s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:547s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:413s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:598s
fi-cnl-y         total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:655s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_706/issues.html
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✗ Fi.CI.IGT: warning for series starting with [1/3] lib/dummyload: Support returning output fence

[Patchwork]

== Series Details ==

Series: series starting with [1/3] lib/dummyload: Support returning output fence
URL   : https://patchwork.freedesktop.org/series/35589/
State : warning

== Summary ==

Test pm_rpm:
        Subgroup system-suspend-modeset:
                pass       -> SKIP       (shard-hsw)
Test kms_draw_crc:
        Subgroup draw-method-xrgb2101010-mmap-gtt-untiled:
                skip       -> PASS       (shard-snb)
Test perf:
        Subgroup blocking:
                fail       -> PASS       (shard-hsw) fdo#102252
Test kms_atomic_transition:
        Subgroup 1x-modeset-transitions-nonblocking:
                skip       -> PASS       (shard-snb)
Test kms_busy:
        Subgroup extended-pageflip-hang-oldfb-render-b:
                skip       -> PASS       (shard-snb)
Test kms_rotation_crc:
        Subgroup sprite-rotation-180:
                pass       -> SKIP       (shard-snb)
Test kms_flip:
        Subgroup vblank-vs-modeset-suspend:
                skip       -> PASS       (shard-snb) fdo#102365

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365

shard-hsw        total:2727 pass:1536 dwarn:1   dfail:0   fail:10  skip:1180 time:9422s
shard-snb        total:2727 pass:1309 dwarn:1   dfail:0   fail:10  skip:1407 time:8096s
Blacklisted hosts:
shard-apl        total:2727 pass:1690 dwarn:1   dfail:0   fail:31  skip:1004 time:13803s
shard-kbl        total:2709 pass:1803 dwarn:4   dfail:0   fail:28  skip:873 time:10895s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_706/shards.html
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Re: [PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-19 15:45:42)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Rather than calibrate and emit nop batches, use a manually signalled chain
> of spinners to generate the desired interrupts.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>         } while (idle != busy);
>  
> -       /* Install the fences and enable signaling */
> -       igt_assert_eq(poll(&pfd, 1, 10), 0);
> +       /* Process the batch queue. */
> +       pfd.events = POLLIN;
> +       for (int i = 0; i < target; i++) {
> +               const unsigned int timeout_ms = test_duration_ms / target;

I think you want
	timeout_ms = (i + 1) * test_duration_ms / target;
? Otherwise all the batches have the same relative-to-now timeout (not
relative to the start of the batch).
-Chris
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Re: [PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-19 15:45:42)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Rather than calibrate and emit nop batches, use a manually signalled chain
> of spinners to generate the desired interrupts.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> -       /* Unplug the calibrated queue and wait for all the fences */
> -       igt_spin_batch_free(gem_fd, spin);
> -       igt_assert_eq(poll(&pfd, 1, 2 * test_duration_ms), 1);
> -       close(pfd.fd);
> +               pfd.fd = spin[i]->out_fence;
> +               igt_spin_batch_set_timeout(spin[i], timeout_ms * 1e6);
> +               igt_assert_eq(poll(&pfd, 1, 2 * timeout_ms), 1);

Oh, still with the synchronous behaviour, bleurgh.
-Chris
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Re: [PATCH i-g-t 1/3] lib/dummyload: Support returning output fence

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-19 15:45:41)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Support creating spin batches which return an output fence using new
> __igt_spin_batch_new_fence / igt_spin_batch_new_fence API.
> 
> This will be used fromthe perf_pmu@interrupts test to ensure user
> interrupt generation from a batch with controlled duration.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  lib/igt_dummyload.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++-------
>  lib/igt_dummyload.h | 10 +++++++++
>  2 files changed, 67 insertions(+), 8 deletions(-)
> 
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index d19b4e5ea3d2..ef08ad580246 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -70,9 +70,9 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
>         reloc->write_domain = write_domains;
>  }
>  
> -static void emit_recursive_batch(igt_spin_t *spin,
> -                                int fd, uint32_t ctx, unsigned engine,
> -                                uint32_t dep)
> +static int emit_recursive_batch(igt_spin_t *spin,
> +                               int fd, uint32_t ctx, unsigned engine,
> +                               uint32_t dep, bool out_fence)
>  {
>  #define SCRATCH 0
>  #define BATCH 1
> @@ -87,6 +87,7 @@ static void emit_recursive_batch(igt_spin_t *spin,
>  
>         nengine = 0;
>         if (engine == -1) {
> +               igt_assert_eq(out_fence, false);

Didn't fancy merging the fences together to return a composite out_fence?

>                 for_each_engine(fd, engine)
>                         if (engine)
>                                 engines[nengine++] = engine;
> @@ -165,22 +166,31 @@ static void emit_recursive_batch(igt_spin_t *spin,
>         execbuf.buffers_ptr = to_user_pointer(obj + (2 - execbuf.buffer_count));
>         execbuf.rsvd1 = ctx;
>  
> +       if (out_fence)
> +               execbuf.flags = I915_EXEC_FENCE_OUT;

if (out_fence)
	execbuf.flags |= I915_EXEC_FENCE_OUT;

Just to make future changes easier?

Might also be good to insert a igt_require(gem_has_exec_fence(fd)) here
as well. (Or earlier?)

> +igt_spin_t *__igt_spin_batch_new_fence(int fd,
> +                                      uint32_t ctx,
> +                                      unsigned engine);
> +
> +igt_spin_t *igt_spin_batch_new_fence(int fd,
> +                                    uint32_t ctx,
> +                                    unsigned engine);

Ok for now, I expect these will mangled into a new spin-batch factory
later on.

With an igt_require(),
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

If you want to merge the N engines' out_fences into one, that would save
me a task.
-Chris

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Re: [PATCH i-g-t 3/3] tests/perf_pmu: Verify engine busyness accuracy

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-19 15:45:43)
> +static void debug_error(const char *str, double val, double ref)
> +{
> +       igt_debug("%s=%.2f%% (%.2f/%.2f)\n", str, __error(val, ref), val, ref);
> +}
> +
> +static void log_error(const char *str, double val, double ref)
> +{
> +       debug_error(str, val, ref);
> +       igt_info("%s=%.2f%%\n", str, __error(val, ref));
> +}

Looking at the CI output, these could really do with some explanation.
-Chris
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Re: [PATCH i-g-t 1/3] lib/dummyload: Support returning output fence

[Tvrtko Ursulin]

On 19/12/2017 22:42, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-12-19 15:45:41)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Support creating spin batches which return an output fence using new
>> __igt_spin_batch_new_fence / igt_spin_batch_new_fence API.
>>
>> This will be used fromthe perf_pmu@interrupts test to ensure user
>> interrupt generation from a batch with controlled duration.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   lib/igt_dummyload.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++-------
>>   lib/igt_dummyload.h | 10 +++++++++
>>   2 files changed, 67 insertions(+), 8 deletions(-)
>>
>> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
>> index d19b4e5ea3d2..ef08ad580246 100644
>> --- a/lib/igt_dummyload.c
>> +++ b/lib/igt_dummyload.c
>> @@ -70,9 +70,9 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
>>          reloc->write_domain = write_domains;
>>   }
>>   
>> -static void emit_recursive_batch(igt_spin_t *spin,
>> -                                int fd, uint32_t ctx, unsigned engine,
>> -                                uint32_t dep)
>> +static int emit_recursive_batch(igt_spin_t *spin,
>> +                               int fd, uint32_t ctx, unsigned engine,
>> +                               uint32_t dep, bool out_fence)
>>   {
>>   #define SCRATCH 0
>>   #define BATCH 1
>> @@ -87,6 +87,7 @@ static void emit_recursive_batch(igt_spin_t *spin,
>>   
>>          nengine = 0;
>>          if (engine == -1) {
>> +               igt_assert_eq(out_fence, false);
> 
> Didn't fancy merging the fences together to return a composite out_fence?

No, just did not think of it. Will do that.

> 
>>                  for_each_engine(fd, engine)
>>                          if (engine)
>>                                  engines[nengine++] = engine;
>> @@ -165,22 +166,31 @@ static void emit_recursive_batch(igt_spin_t *spin,
>>          execbuf.buffers_ptr = to_user_pointer(obj + (2 - execbuf.buffer_count));
>>          execbuf.rsvd1 = ctx;
>>   
>> +       if (out_fence)
>> +               execbuf.flags = I915_EXEC_FENCE_OUT;
> 
> if (out_fence)
> 	execbuf.flags |= I915_EXEC_FENCE_OUT;
> 
> Just to make future changes easier?
> 
> Might also be good to insert a igt_require(gem_has_exec_fence(fd)) here
> as well. (Or earlier?)

Ack.

>> +igt_spin_t *__igt_spin_batch_new_fence(int fd,
>> +                                      uint32_t ctx,
>> +                                      unsigned engine);
>> +
>> +igt_spin_t *igt_spin_batch_new_fence(int fd,
>> +                                    uint32_t ctx,
>> +                                    unsigned engine);
> 
> Ok for now, I expect these will mangled into a new spin-batch factory
> later on.

Yeah, I was thinking whether a more generic constructor would be better, 
but then decided against sprinkling changes all over the place.

> With an igt_require(),
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> If you want to merge the N engines' out_fences into one, that would save
> me a task.

Thanks, will do.

Regards,

Tvrtko
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Re: [PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Tvrtko Ursulin]

On 19/12/2017 21:45, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-12-19 15:45:42)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Rather than calibrate and emit nop batches, use a manually signalled chain
>> of spinners to generate the desired interrupts.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>> -       /* Unplug the calibrated queue and wait for all the fences */
>> -       igt_spin_batch_free(gem_fd, spin);
>> -       igt_assert_eq(poll(&pfd, 1, 2 * test_duration_ms), 1);
>> -       close(pfd.fd);
>> +               pfd.fd = spin[i]->out_fence;
>> +               igt_spin_batch_set_timeout(spin[i], timeout_ms * 1e6);
>> +               igt_assert_eq(poll(&pfd, 1, 2 * timeout_ms), 1);
> 
> Oh, still with the synchronous behaviour, bleurgh.

I was attracted by the simplicity of this approach, but I can change to 
set incremental timeouts and keep the merged fence if you think that's 
better?

Regards,

Tvrtko


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Re: [PATCH i-g-t 3/3] tests/perf_pmu: Verify engine busyness accuracy

[Tvrtko Ursulin]

On 19/12/2017 22:45, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-12-19 15:45:43)
>> +static void debug_error(const char *str, double val, double ref)
>> +{
>> +       igt_debug("%s=%.2f%% (%.2f/%.2f)\n", str, __error(val, ref), val, ref);
>> +}
>> +
>> +static void log_error(const char *str, double val, double ref)
>> +{
>> +       debug_error(str, val, ref);
>> +       igt_info("%s=%.2f%%\n", str, __error(val, ref));
>> +}
> 
> Looking at the CI output, these could really do with some explanation.

Yes a very disappointing think to look at in the morning. Much worse 
than the previous version which used calibrated batches. While at the 
same time new version is much better on my SKL..

Regards,

Tvrtko
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Re: [PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-20 09:45:41)
> 
> On 19/12/2017 21:45, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-12-19 15:45:42)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Rather than calibrate and emit nop batches, use a manually signalled chain
> >> of spinners to generate the desired interrupts.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> ---
> >> -       /* Unplug the calibrated queue and wait for all the fences */
> >> -       igt_spin_batch_free(gem_fd, spin);
> >> -       igt_assert_eq(poll(&pfd, 1, 2 * test_duration_ms), 1);
> >> -       close(pfd.fd);
> >> +               pfd.fd = spin[i]->out_fence;
> >> +               igt_spin_batch_set_timeout(spin[i], timeout_ms * 1e6);
> >> +               igt_assert_eq(poll(&pfd, 1, 2 * timeout_ms), 1);
> > 
> > Oh, still with the synchronous behaviour, bleurgh.
> 
> I was attracted by the simplicity of this approach, but I can change to 
> set incremental timeouts and keep the merged fence if you think that's 
> better?

It was mostly surprise as I just have a preference for setting up
everything and then letting it go; fire-and-forget style. So that was
what I was expecting to see. It should basically be the difference of
adding a single function to merge the fences (albeit you have to write
that function). Shall we say both patterns have merit / analogues to the
real world?
-Chris
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Re: [PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Tvrtko Ursulin]

On 20/12/2017 10:49, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-12-20 09:45:41)
>>
>> On 19/12/2017 21:45, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2017-12-19 15:45:42)
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Rather than calibrate and emit nop batches, use a manually signalled chain
>>>> of spinners to generate the desired interrupts.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> ---
>>>> -       /* Unplug the calibrated queue and wait for all the fences */
>>>> -       igt_spin_batch_free(gem_fd, spin);
>>>> -       igt_assert_eq(poll(&pfd, 1, 2 * test_duration_ms), 1);
>>>> -       close(pfd.fd);
>>>> +               pfd.fd = spin[i]->out_fence;
>>>> +               igt_spin_batch_set_timeout(spin[i], timeout_ms * 1e6);
>>>> +               igt_assert_eq(poll(&pfd, 1, 2 * timeout_ms), 1);
>>>
>>> Oh, still with the synchronous behaviour, bleurgh.
>>
>> I was attracted by the simplicity of this approach, but I can change to
>> set incremental timeouts and keep the merged fence if you think that's
>> better?
> 
> It was mostly surprise as I just have a preference for setting up
> everything and then letting it go; fire-and-forget style. So that was
> what I was expecting to see. It should basically be the difference of
> adding a single function to merge the fences (albeit you have to write
> that function). Shall we say both patterns have merit / analogues to the
> real world?

It is using fence merging approach so it won't be a problem to keep 
that, just with the spin batches. I mostly wanted to remove calibration 
since you were nudging me in that direction. Don't mind really of the 
specific mechanics of emitting interrupts so I am happy to go back a step.

Regards,

Tvrtko
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Re: [PATCH i-g-t 2/3] tests/perf_pmu: Simplify interrupt testing

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-20 12:35:31)
> 
> On 20/12/2017 10:49, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-12-20 09:45:41)
> >>
> >> On 19/12/2017 21:45, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2017-12-19 15:45:42)
> >>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>
> >>>> Rather than calibrate and emit nop batches, use a manually signalled chain
> >>>> of spinners to generate the desired interrupts.
> >>>>
> >>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>> ---
> >>>> -       /* Unplug the calibrated queue and wait for all the fences */
> >>>> -       igt_spin_batch_free(gem_fd, spin);
> >>>> -       igt_assert_eq(poll(&pfd, 1, 2 * test_duration_ms), 1);
> >>>> -       close(pfd.fd);
> >>>> +               pfd.fd = spin[i]->out_fence;
> >>>> +               igt_spin_batch_set_timeout(spin[i], timeout_ms * 1e6);
> >>>> +               igt_assert_eq(poll(&pfd, 1, 2 * timeout_ms), 1);
> >>>
> >>> Oh, still with the synchronous behaviour, bleurgh.
> >>
> >> I was attracted by the simplicity of this approach, but I can change to
> >> set incremental timeouts and keep the merged fence if you think that's
> >> better?
> > 
> > It was mostly surprise as I just have a preference for setting up
> > everything and then letting it go; fire-and-forget style. So that was
> > what I was expecting to see. It should basically be the difference of
> > adding a single function to merge the fences (albeit you have to write
> > that function). Shall we say both patterns have merit / analogues to the
> > real world?
> 
> It is using fence merging approach so it won't be a problem to keep 
> that, just with the spin batches. I mostly wanted to remove calibration 
> since you were nudging me in that direction. Don't mind really of the 
> specific mechanics of emitting interrupts so I am happy to go back a step.

I was thinking how difficult would it be to run twice; once batched and
once sync? We're more likely to catch discrepancies in our interrupt
generation that way, which may or may not help improve the test in
future.
-Chris
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