* [PATCH] drm/i915/psr: Don't name status or debug registers like control registers.
@ 2017-12-20 20:10 Dhinakaran Pandiyan
2017-12-20 20:32 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Dhinakaran Pandiyan @ 2017-12-20 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Dhinakaran Pandiyan
Avoids some typo pitfalls.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
drivers/gpu/drm/i915/intel_psr.c | 24 ++++++++++++------------
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c4780f085428..81ca9433fc9e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2578,9 +2578,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
seq_printf(m, "Performance_Counter: %u\n", psrperf);
}
if (dev_priv->psr.psr2_support) {
- u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
+ u32 psr2 = I915_READ(EDP_PSR2_STATUS);
- seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
+ seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
psr2, psr2_live_status(psr2));
}
mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 268bbd0eaaa4..db7757a04720 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4060,7 +4060,7 @@ enum {
#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
-#define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40)
+#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
#define EDP_PSR_STATUS_STATE_MASK (7<<29)
#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
@@ -4087,7 +4087,7 @@ enum {
#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
#define EDP_PSR_PERF_CNT_MASK 0xffffff
-#define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60)
+#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
@@ -4110,7 +4110,7 @@ enum {
#define EDP_PSR2_IDLE_MASK 0xf
#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
-#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
+#define EDP_PSR2_STATUS _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
#define EDP_PSR2_STATUS_STATE_SHIFT 28
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e32615eeada..403256ad871d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -476,7 +476,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
- I915_WRITE(EDP_PSR_DEBUG_CTL,
+ I915_WRITE(EDP_PSR_DEBUG,
EDP_PSR_DEBUG_MASK_MEMUP |
EDP_PSR_DEBUG_MASK_HPD |
EDP_PSR_DEBUG_MASK_LPSP |
@@ -490,7 +490,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
* preventing other hw tracking issues now we can rely
* on frontbuffer tracking.
*/
- I915_WRITE(EDP_PSR_DEBUG_CTL,
+ I915_WRITE(EDP_PSR_DEBUG,
EDP_PSR_DEBUG_MASK_MEMUP |
EDP_PSR_DEBUG_MASK_HPD |
EDP_PSR_DEBUG_MASK_LPSP);
@@ -599,7 +599,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
0);
if (dev_priv->psr.psr2_support) {
- psr_status = EDP_PSR2_STATUS_CTL;
+ psr_status = EDP_PSR2_STATUS;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
I915_WRITE(EDP_PSR2_CTL,
@@ -607,7 +607,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
} else {
- psr_status = EDP_PSR_STATUS_CTL;
+ psr_status = EDP_PSR_STATUS;
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
I915_WRITE(EDP_PSR_CTL,
@@ -679,19 +679,19 @@ static void intel_psr_work(struct work_struct *work)
if (HAS_DDI(dev_priv)) {
if (dev_priv->psr.psr2_support) {
if (intel_wait_for_register(dev_priv,
- EDP_PSR2_STATUS_CTL,
- EDP_PSR2_STATUS_STATE_MASK,
- 0,
- 50)) {
+ EDP_PSR2_STATUS,
+ EDP_PSR2_STATUS_STATE_MASK,
+ 0,
+ 50)) {
DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
return;
}
} else {
if (intel_wait_for_register(dev_priv,
- EDP_PSR_STATUS_CTL,
- EDP_PSR_STATUS_STATE_MASK,
- 0,
- 50)) {
+ EDP_PSR_STATUS,
+ EDP_PSR_STATUS_STATE_MASK,
+ 0,
+ 50)) {
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
return;
}
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Don't name status or debug registers like control registers.
2017-12-20 20:10 [PATCH] drm/i915/psr: Don't name status or debug registers like control registers Dhinakaran Pandiyan
@ 2017-12-20 20:32 ` Patchwork
2017-12-20 21:57 ` ✓ Fi.CI.IGT: " Patchwork
2017-12-20 22:11 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-12-20 20:32 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Don't name status or debug registers like control registers.
URL : https://patchwork.freedesktop.org/series/35644/
State : success
== Summary ==
Series 35644v1 drm/i915/psr: Don't name status or debug registers like control registers.
https://patchwork.freedesktop.org/api/1.0/series/35644/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:436s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:382s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:495s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:500s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:496s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:475s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:464s
fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:264s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:531s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:410s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:387s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:476s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:426s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:479s
fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:513s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:465s
fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:528s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:575s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:444s
fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:532s
fi-skl-6700hq total:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:552s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:505s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:501s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:446s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:551s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:418s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:588s
fi-cnl-y total:245 pass:220 dwarn:0 dfail:0 fail:0 skip:24
fi-bdw-gvtdvm failed to collect. IGT log at Patchwork_7551/fi-bdw-gvtdvm/igt.log
16c40c33a5ea1777e50496fd6e19c7011a939c01 drm-tip: 2017y-12m-20d-19h-24m-38s UTC integration manifest
45dcaada0ac0 drm/i915/psr: Don't name status or debug registers like control registers.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7551/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Don't name status or debug registers like control registers.
2017-12-20 20:10 [PATCH] drm/i915/psr: Don't name status or debug registers like control registers Dhinakaran Pandiyan
2017-12-20 20:32 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-12-20 21:57 ` Patchwork
2017-12-20 22:11 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-12-20 21:57 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Don't name status or debug registers like control registers.
URL : https://patchwork.freedesktop.org/series/35644/
State : success
== Summary ==
Test kms_flip:
Subgroup plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368
Subgroup wf_vblank-vs-modeset:
dmesg-warn -> PASS (shard-hsw) fdo#102614
Test gem_softpin:
Subgroup noreloc-s3:
skip -> PASS (shard-hsw) fdo#103540
Subgroup noreloc-s4:
fail -> SKIP (shard-snb) fdo#103375
Test kms_universal_plane:
Subgroup universal-plane-pipe-c-sanity:
skip -> PASS (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass -> FAIL (shard-snb) fdo#101623
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
shard-hsw total:2712 pass:1536 dwarn:1 dfail:0 fail:11 skip:1164 time:9362s
shard-snb total:2712 pass:1307 dwarn:1 dfail:0 fail:11 skip:1393 time:8035s
Blacklisted hosts:
shard-apl total:2712 pass:1686 dwarn:1 dfail:0 fail:23 skip:1001 time:13659s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7551/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/psr: Don't name status or debug registers like control registers.
2017-12-20 20:10 [PATCH] drm/i915/psr: Don't name status or debug registers like control registers Dhinakaran Pandiyan
2017-12-20 20:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-20 21:57 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-12-20 22:11 ` Rodrigo Vivi
2 siblings, 0 replies; 4+ messages in thread
From: Rodrigo Vivi @ 2017-12-20 22:11 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
On Wed, Dec 20, 2017 at 08:10:21PM +0000, Dhinakaran Pandiyan wrote:
> Avoids some typo pitfalls.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 6 +++---
> drivers/gpu/drm/i915/intel_psr.c | 24 ++++++++++++------------
> 3 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c4780f085428..81ca9433fc9e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2578,9 +2578,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> seq_printf(m, "Performance_Counter: %u\n", psrperf);
> }
> if (dev_priv->psr.psr2_support) {
> - u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
> + u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>
> - seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
> + seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> psr2, psr2_live_status(psr2));
> }
> mutex_unlock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 268bbd0eaaa4..db7757a04720 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4060,7 +4060,7 @@ enum {
> #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
> #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>
> -#define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40)
> +#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
> #define EDP_PSR_STATUS_STATE_MASK (7<<29)
> #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
> #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
> @@ -4087,7 +4087,7 @@ enum {
> #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
> #define EDP_PSR_PERF_CNT_MASK 0xffffff
>
> -#define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60)
> +#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
> #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
> #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
> #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
> @@ -4110,7 +4110,7 @@ enum {
> #define EDP_PSR2_IDLE_MASK 0xf
> #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
>
> -#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
> +#define EDP_PSR2_STATUS _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> #define EDP_PSR2_STATUS_STATE_SHIFT 28
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2e32615eeada..403256ad871d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -476,7 +476,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
> I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>
> - I915_WRITE(EDP_PSR_DEBUG_CTL,
> + I915_WRITE(EDP_PSR_DEBUG,
> EDP_PSR_DEBUG_MASK_MEMUP |
> EDP_PSR_DEBUG_MASK_HPD |
> EDP_PSR_DEBUG_MASK_LPSP |
> @@ -490,7 +490,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> * preventing other hw tracking issues now we can rely
> * on frontbuffer tracking.
> */
> - I915_WRITE(EDP_PSR_DEBUG_CTL,
> + I915_WRITE(EDP_PSR_DEBUG,
> EDP_PSR_DEBUG_MASK_MEMUP |
> EDP_PSR_DEBUG_MASK_HPD |
> EDP_PSR_DEBUG_MASK_LPSP);
> @@ -599,7 +599,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
> 0);
>
> if (dev_priv->psr.psr2_support) {
> - psr_status = EDP_PSR2_STATUS_CTL;
> + psr_status = EDP_PSR2_STATUS;
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
>
> I915_WRITE(EDP_PSR2_CTL,
> @@ -607,7 +607,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
> ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
>
> } else {
> - psr_status = EDP_PSR_STATUS_CTL;
> + psr_status = EDP_PSR_STATUS;
> psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
>
> I915_WRITE(EDP_PSR_CTL,
> @@ -679,19 +679,19 @@ static void intel_psr_work(struct work_struct *work)
> if (HAS_DDI(dev_priv)) {
> if (dev_priv->psr.psr2_support) {
> if (intel_wait_for_register(dev_priv,
> - EDP_PSR2_STATUS_CTL,
> - EDP_PSR2_STATUS_STATE_MASK,
> - 0,
> - 50)) {
> + EDP_PSR2_STATUS,
> + EDP_PSR2_STATUS_STATE_MASK,
> + 0,
> + 50)) {
> DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
> return;
> }
> } else {
> if (intel_wait_for_register(dev_priv,
> - EDP_PSR_STATUS_CTL,
> - EDP_PSR_STATUS_STATE_MASK,
> - 0,
> - 50)) {
> + EDP_PSR_STATUS,
> + EDP_PSR_STATUS_STATE_MASK,
> + 0,
> + 50)) {
> DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
> return;
> }
> --
> 2.11.0
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-12-20 22:11 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-20 20:10 [PATCH] drm/i915/psr: Don't name status or debug registers like control registers Dhinakaran Pandiyan
2017-12-20 20:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-20 21:57 ` ✓ Fi.CI.IGT: " Patchwork
2017-12-20 22:11 ` [PATCH] " Rodrigo Vivi
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