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* [PATCH v2] clk: qoriq: add more divider clocks support
@ 2017-11-22  1:40 Andy.tang
  2017-12-21 23:57 ` Stephen Boyd
  0 siblings, 1 reply; 5+ messages in thread
From: Andy.tang @ 2017-11-22  1:40 UTC (permalink / raw)
  To: mturquette, sboyd, robh+dt
  Cc: mark.rutland, linux-clk, evicetree, Yuantian Tang

From: Yuantian Tang <andy.tang@nxp.com>

More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
resend with ack added
v2:
  - fix a logical error

 Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
 drivers/clk/clk-qoriq.c                                 | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 6498e1fdbb33..97f46adac85f 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -78,6 +78,7 @@ second cell is the clock index for the specified type.
 	2	hwaccel		index (n in CLKCGnHWACSR)
 	3	fman		0 for fm1, 1 for fm2
 	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
 	5	coreclk		must be 0
 
 3. Example
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index b0ea753b8709..3a1812f65e5d 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
 };
 
 struct clockgen_pll {
-	struct clockgen_pll_div div[4];
+	struct clockgen_pll_div div[8];
 };
 
 #define CLKSEL_VALID	1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
 		struct clk *clk;
 		int ret;
 
+		/*
+		 * For platform PLL, there are 8 divider clocks.
+		 * For core PLL, there are 4 divider clocks at most.
+		 */
+		if (idx != PLATFORM_PLL && i >= 4)
+			break;
+
 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
 			 "cg-pll%d-div%d", idx, i + 1);
 
-- 
2.14.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] clk: qoriq: add more divider clocks support
  2017-11-22  1:40 [PATCH v2] clk: qoriq: add more divider clocks support Andy.tang
@ 2017-12-21 23:57 ` Stephen Boyd
  0 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2017-12-21 23:57 UTC (permalink / raw)
  To: Andy.tang; +Cc: mturquette, robh+dt, mark.rutland, linux-clk, evicetree

On 11/22, Andy.tang@nxp.com wrote:
> From: Yuantian Tang <andy.tang@nxp.com>
> 
> More divider clocks are needed by IP. So enlarge the PLL divider
> array to accommodate more divider clocks.
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] clk: qoriq: add more divider clocks support
  2017-11-21  6:13 ` andy.tang
  (?)
@ 2017-11-21 18:30 ` Rob Herring
  -1 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2017-11-21 18:30 UTC (permalink / raw)
  To: andy.tang; +Cc: mturquette, sboyd, mark.rutland, linux-clk, devicetree

On Tue, Nov 21, 2017 at 02:13:00PM +0800, andy.tang@nxp.com wrote:
> From: Yuantian Tang <andy.tang@nxp.com>
> 
> More divider clocks are needed by IP. So enlarge the PLL divider
> array to accommodate more divider clocks.
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> ---
> v2:
>   - fix a logical error
> 
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +

Please add acks when posting new versions.

>  drivers/clk/clk-qoriq.c                                 | 9 ++++++++-
>  2 files changed, 9 insertions(+), 1 deletion(-)

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2] clk: qoriq: add more divider clocks support
@ 2017-11-21  6:13 ` andy.tang
  0 siblings, 0 replies; 5+ messages in thread
From: andy.tang @ 2017-11-21  6:13 UTC (permalink / raw)
  To: mturquette, sboyd, robh+dt
  Cc: mark.rutland, linux-clk, devicetree, Yuantian Tang

From: Yuantian Tang <andy.tang@nxp.com>

More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v2:
  - fix a logical error

 Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
 drivers/clk/clk-qoriq.c                                 | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 6498e1fdbb33..97f46adac85f 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -78,6 +78,7 @@ second cell is the clock index for the specified type.
 	2	hwaccel		index (n in CLKCGnHWACSR)
 	3	fman		0 for fm1, 1 for fm2
 	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
 	5	coreclk		must be 0
 
 3. Example
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index b0ea753b8709..3a1812f65e5d 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
 };
 
 struct clockgen_pll {
-	struct clockgen_pll_div div[4];
+	struct clockgen_pll_div div[8];
 };
 
 #define CLKSEL_VALID	1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
 		struct clk *clk;
 		int ret;
 
+		/*
+		 * For platform PLL, there are 8 divider clocks.
+		 * For core PLL, there are 4 divider clocks at most.
+		 */
+		if (idx != PLATFORM_PLL && i >= 4)
+			break;
+
 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
 			 "cg-pll%d-div%d", idx, i + 1);
 
-- 
2.14.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH v2] clk: qoriq: add more divider clocks support
@ 2017-11-21  6:13 ` andy.tang
  0 siblings, 0 replies; 5+ messages in thread
From: andy.tang @ 2017-11-21  6:13 UTC (permalink / raw)
  To: mturquette, sboyd, robh+dt
  Cc: mark.rutland, linux-clk, devicetree, Yuantian Tang

From: Yuantian Tang <andy.tang@nxp.com>

More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v2:
  - fix a logical error

 Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
 drivers/clk/clk-qoriq.c                                 | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 6498e1fdbb33..97f46adac85f 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -78,6 +78,7 @@ second cell is the clock index for the specified type.
 	2	hwaccel		index (n in CLKCGnHWACSR)
 	3	fman		0 for fm1, 1 for fm2
 	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
 	5	coreclk		must be 0
 
 3. Example
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index b0ea753b8709..3a1812f65e5d 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
 };
 
 struct clockgen_pll {
-	struct clockgen_pll_div div[4];
+	struct clockgen_pll_div div[8];
 };
 
 #define CLKSEL_VALID	1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
 		struct clk *clk;
 		int ret;
 
+		/*
+		 * For platform PLL, there are 8 divider clocks.
+		 * For core PLL, there are 4 divider clocks at most.
+		 */
+		if (idx != PLATFORM_PLL && i >= 4)
+			break;
+
 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
 			 "cg-pll%d-div%d", idx, i + 1);
 
-- 
2.14.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-12-21 23:57 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-22  1:40 [PATCH v2] clk: qoriq: add more divider clocks support Andy.tang
2017-12-21 23:57 ` Stephen Boyd
  -- strict thread matches above, loose matches on Subject: below --
2017-11-21  6:13 andy.tang
2017-11-21  6:13 ` andy.tang
2017-11-21 18:30 ` Rob Herring

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