* [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
@ 2017-12-22 22:23 Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
` (10 more replies)
0 siblings, 11 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
By the Spec all CNL skus are GT2.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
v6: Unify in a way that we don't break early-quirks.c
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 +--
include/drm/i915_pciids.h | 18 +++++++-----------
2 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 36d48422b475..cc87d741135d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -636,8 +636,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
- INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
- INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
+ INTEL_CNL_IDS(&intel_cannonlake_gt2_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 5db0458dd832..9e1fe6634424 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -414,24 +414,20 @@
INTEL_CFL_U_GT2_IDS(info), \
INTEL_CFL_U_GT3_IDS(info)
-/* CNL U 2+2 */
-#define INTEL_CNL_U_GT2_IDS(info) \
+/* CNL */
+#define INTEL_CNL_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
INTEL_VGA_DEVICE(0x5A5A, info), \
INTEL_VGA_DEVICE(0x5A42, info), \
- INTEL_VGA_DEVICE(0x5A4A, info)
-
-/* CNL Y 2+2 */
-#define INTEL_CNL_Y_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
INTEL_VGA_DEVICE(0x5A49, info), \
INTEL_VGA_DEVICE(0x5A71, info), \
- INTEL_VGA_DEVICE(0x5A79, info)
-
-#define INTEL_CNL_IDS(info) \
- INTEL_CNL_U_GT2_IDS(info), \
- INTEL_CNL_Y_GT2_IDS(info)
+ INTEL_VGA_DEVICE(0x5A79, info), \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info), \
+ INTEL_VGA_DEVICE(0x5A44, info)
#endif /* _I915_PCIIDS_H */
--
2.13.6
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 02/11] drm/i915/cnl: Add Port F definition.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 03/11] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
` (9 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Some Cannonlake SKUs will come with a full split between
port A and port E. This will be called port F although it
is not a 6th port, but only a split.
v2: Fix size of dvo_ports found by Ander.
v3: Adding missing cases from intel_bios.c for Port_F
v4: Adding other missing cases and fix the commit message.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 9 +++++++++
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_vbt_defs.h | 2 ++
include/drm/i915_component.h | 3 +--
5 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca2a61966a23..56c81e20b2f3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -346,6 +346,7 @@ enum port {
PORT_C,
PORT_D,
PORT_E,
+ PORT_F,
I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 51108ffc28d1..59a150e2adce 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1140,6 +1140,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
{DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
{DVO_PORT_HDMID, DVO_PORT_DPD, -1},
{DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
+ {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
};
/*
@@ -1688,6 +1689,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
[PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+ [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
int i;
@@ -1726,6 +1728,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
[PORT_C] = DVO_PORT_DPC,
[PORT_D] = DVO_PORT_DPD,
[PORT_E] = DVO_PORT_DPE,
+ [PORT_F] = DVO_PORT_DPF,
};
int i;
@@ -1761,6 +1764,7 @@ static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
[PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+ [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
@@ -1927,6 +1931,11 @@ intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
if (port == PORT_D)
return true;
break;
+ case DVO_PORT_DPF:
+ case DVO_PORT_HDMIF:
+ if (port == PORT_F)
+ return true;
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 35c5299feab6..71721de39e6b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1378,6 +1378,7 @@ static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1393,6 +1394,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index e3d7745a9151..8713e8295957 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -299,6 +299,8 @@ struct bdb_general_features {
#define DVO_PORT_DPA 10
#define DVO_PORT_DPE 11 /* 193 */
#define DVO_PORT_HDMIE 12 /* 193 */
+#define DVO_PORT_DPF 13
+#define DVO_PORT_HDMIF 14
#define DVO_PORT_MIPIA 21 /* 171 */
#define DVO_PORT_MIPIB 22 /* 171 */
#define DVO_PORT_MIPIC 23 /* 171 */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 545c6e0fea7d..346b1f5cb180 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -26,9 +26,8 @@
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
- * 5 should be enough as only HSW, BDW, SKL need such fix.
*/
-#define MAX_PORTS 5
+#define MAX_PORTS 6
/**
* struct i915_audio_component_ops - Ops implemented by i915 driver, called by hda driver
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 03/11] drm/i915/cnl: Add AUX-F support
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 04/11] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
` (8 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Rebase and fix commit message.
v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
5 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56c81e20b2f3..2fc028fdfed9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -397,6 +397,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_AUX_F,
+
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
@@ -1702,6 +1704,7 @@ enum modeset_restore {
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
+#define DP_AUX_F 0x50
#define DDC_PIN_B 0x05
#define DDC_PIN_C 0x04
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..8b8df5b8b8a7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
+ if (IS_CANNONLAKE(dev_priv))
+ tmp_mask |= CNL_AUX_CHANNEL_F;
+
if (iir & tmp_mask) {
dp_aux_irq_handler(dev_priv);
found = true;
@@ -3611,6 +3614,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+ if (IS_CANNONLAKE(dev_priv))
+ de_port_masked |= CNL_AUX_CHANNEL_F;
+
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 268bbd0eaaa4..1fd46b63f283 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1312,6 +1312,7 @@ enum i915_power_well_id {
CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
CNL_DISP_PW_AUX_D,
+ CNL_DISP_PW_AUX_F = 13,
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
@@ -5272,6 +5273,13 @@ enum {
#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
+
#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
@@ -6927,6 +6935,7 @@ enum {
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
#define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define CNL_AUX_CHANNEL_F (1 << 28)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define GEN9_AUX_CHANNEL_C (1 << 26)
#define GEN9_AUX_CHANNEL_B (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 71721de39e6b..91e02a35c036 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1298,6 +1298,9 @@ static enum port intel_aux_port(struct drm_i915_private *dev_priv,
case DP_AUX_D:
aux_port = PORT_D;
break;
+ case DP_AUX_F:
+ aux_port = PORT_F;
+ break;
default:
MISSING_CASE(info->alternate_aux_channel);
aux_port = PORT_A;
@@ -1317,6 +1320,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1331,6 +1335,7 @@ static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
@@ -5992,6 +5997,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
/* FIXME: Check VBT for actual wiring of PORT E */
intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
break;
+ case PORT_F:
+ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
+ break;
default:
MISSING_CASE(encoder->port);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 96ab74f3d101..335832b46f86 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_C";
case POWER_DOMAIN_AUX_D:
return "AUX_D";
+ case POWER_DOMAIN_AUX_F:
+ return "AUX_F";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1835,6 +1837,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2384,6 +2389,12 @@ static struct i915_power_well cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
+ {
+ .name = "AUX F",
+ .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_AUX_F,
+ },
};
static int
--
2.13.6
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 04/11] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 03/11] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 05/11] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
` (7 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fd46b63f283..da7c00282bfb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1964,7 +1964,7 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_DW2_LN0_B 0x162648
#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
-#define _CNL_PORT_TX_DW2_LN0_F 0x162A48
+#define _CNL_PORT_TX_DW2_LN0_F 0x162848
#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW2_GRP_AE, \
_CNL_PORT_TX_DW2_GRP_B, \
--
2.13.6
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 05/11] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (2 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 04/11] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 06/11] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
` (6 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da7c00282bfb..a69d52f9fec5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8661,10 +8661,14 @@ enum skl_power_gate {
* CNL Clocks
*/
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
-#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
-#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
+#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
+ (port)+10))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port) == PORT_F ? 21 : \
+ (port)*2))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
+ (port)*2)
+#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port) == PORT_F ? 21 : \
+ (port)*2))
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 06/11] drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (3 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 05/11] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 07/11] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
` (5 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index bced7b954d93..6f460c4534fa 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1924,6 +1924,9 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
case PORT_D:
ddc_pin = GMBUS_PIN_4_CNP;
break;
+ case PORT_F:
+ ddc_pin = GMBUS_PIN_3_BXT;
+ break;
default:
MISSING_CASE(port);
ddc_pin = GMBUS_PIN_1_BXT;
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 07/11] drm/i915: For HPD connected port use hpd_pin instead of port.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (4 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 06/11] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 08/11] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
` (4 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 144 ++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_lspcon.c | 3 +-
3 files changed, 72 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91e02a35c036..6db0b6b25f61 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4462,173 +4462,170 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ibx_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = SDE_PORTB_HOTPLUG;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = SDE_PORTC_HOTPLUG;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = SDE_PORTD_HOTPLUG;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(SDEISR) & bit;
}
-static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool cpt_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = SDE_PORTB_HOTPLUG_CPT;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = SDE_PORTC_HOTPLUG_CPT;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(SDEISR) & bit;
}
-static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool spt_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_A:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
bit = SDE_PORTA_HOTPLUG_SPT;
break;
- case PORT_E:
+ case HPD_PORT_E:
bit = SDE_PORTE_HOTPLUG_SPT;
break;
default:
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
return I915_READ(SDEISR) & bit;
}
-static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool g4x_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool gm45_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ilk_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
else
- return ibx_digital_port_connected(dev_priv, port);
+ return ibx_digital_port_connected(encoder);
}
-static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool snb_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ivb_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *intel_dig_port)
+static bool bxt_digital_port_connected(struct intel_encoder *encoder)
{
- struct intel_encoder *intel_encoder = &intel_dig_port->base;
- enum port port;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
- switch (port) {
- case PORT_A:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
bit = BXT_DE_PORT_HP_DDIA;
break;
- case PORT_B:
+ case HPD_PORT_B:
bit = BXT_DE_PORT_HP_DDIB;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = BXT_DE_PORT_HP_DDIC;
break;
default:
- MISSING_CASE(port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
@@ -4637,33 +4634,33 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
/*
* intel_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
+ * @encoder: intel_encoder
*
* Return %true if @port is connected, %false otherwise.
*/
-bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+bool intel_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (HAS_GMCH_DISPLAY(dev_priv)) {
if (IS_GM45(dev_priv))
- return gm45_digital_port_connected(dev_priv, port);
+ return gm45_digital_port_connected(encoder);
else
- return g4x_digital_port_connected(dev_priv, port);
+ return g4x_digital_port_connected(encoder);
}
if (IS_GEN5(dev_priv))
- return ilk_digital_port_connected(dev_priv, port);
+ return ilk_digital_port_connected(encoder);
else if (IS_GEN6(dev_priv))
- return snb_digital_port_connected(dev_priv, port);
+ return snb_digital_port_connected(encoder);
else if (IS_GEN7(dev_priv))
- return ivb_digital_port_connected(dev_priv, port);
+ return ivb_digital_port_connected(encoder);
else if (IS_GEN8(dev_priv))
- return bdw_digital_port_connected(dev_priv, port);
+ return bdw_digital_port_connected(encoder);
else if (IS_GEN9_LP(dev_priv))
- return bxt_digital_port_connected(dev_priv, port);
+ return bxt_digital_port_connected(encoder);
else
- return spt_digital_port_connected(dev_priv, port);
+ return spt_digital_port_connected(encoder);
}
static struct edid *
@@ -4722,8 +4719,7 @@ intel_dp_long_pulse(struct intel_connector *connector)
/* Can't disconnect eDP, but you can close the lid... */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
- else if (intel_digital_port_connected(dev_priv,
- dp_to_dig_port(intel_dp)))
+ else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
status = intel_dp_detect_dpcd(intel_dp);
else
status = connector_status_disconnected;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f89d64..2d21a54a504b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1590,8 +1590,7 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
-bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port);
+bool intel_digital_port_connected(struct intel_encoder *encoder);
/* intel_dp_aux_backlight.c */
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c
index dcbc786479f9..8ae8f42f430a 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -167,11 +167,10 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
unsigned long start = jiffies;
while (1) {
- if (intel_digital_port_connected(dev_priv, dig_port)) {
+ if (intel_digital_port_connected(&dig_port->base)) {
DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
jiffies_to_msecs(jiffies - start));
return;
--
2.13.6
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 08/11] drm/i915/cnl: Add HPD support for Port F.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (5 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 07/11] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 09/11] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
` (3 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so we can start upstreaming
this right now. If that SKU ever get a proper name
we come back and update it.
v4: Rebase on top of digital connected port using encoder
instead of port.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++++++--
drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_hotplug.c | 19 +++++++++++++++----
5 files changed, 44 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2fc028fdfed9..4dbc10e12d85 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3093,6 +3093,8 @@ intel_info(const struct drm_i915_private *dev_priv)
(dev_priv)->info.gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(dev_priv)->info.gt == 3)
+#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
@@ -3397,8 +3399,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
-enum port intel_hpd_pin_to_port(enum hpd_pin pin);
-enum hpd_pin intel_hpd_pin(enum port port);
+enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
+ enum hpd_pin pin);
+enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
+ enum port port);
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8b8df5b8b8a7..98951eca0367 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1568,10 +1568,11 @@ static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
*
* Note that the caller is expected to zero out the masks initially.
*/
-static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
- u32 hotplug_trigger, u32 dig_hotplug_reg,
- const u32 hpd[HPD_NUM_PINS],
- bool long_pulse_detect(enum port port, u32 val))
+static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
+ u32 *pin_mask, u32 *long_mask,
+ u32 hotplug_trigger, u32 dig_hotplug_reg,
+ const u32 hpd[HPD_NUM_PINS],
+ bool long_pulse_detect(enum port port, u32 val))
{
enum port port;
int i;
@@ -1582,7 +1583,7 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
*pin_mask |= BIT(i);
- port = intel_hpd_pin_to_port(i);
+ port = intel_hpd_pin_to_port(dev_priv, i);
if (port == PORT_NONE)
continue;
@@ -1970,8 +1971,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
if (hotplug_trigger) {
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- hotplug_trigger, hpd_status_g4x,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, hotplug_trigger,
+ hpd_status_g4x,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1983,8 +1985,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
if (hotplug_trigger) {
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- hotplug_trigger, hpd_status_i915,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, hotplug_trigger,
+ hpd_status_i915,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
@@ -2185,7 +2188,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!hotplug_trigger)
return;
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
pch_port_hotplug_long_detect);
@@ -2327,8 +2330,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd_spt,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, dig_hotplug_reg, hpd_spt,
spt_port_hotplug_long_detect);
}
@@ -2338,8 +2341,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
- dig_hotplug_reg, hpd_spt,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug2_trigger, dig_hotplug_reg, hpd_spt,
spt_port_hotplug2_long_detect);
}
@@ -2359,7 +2362,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
ilk_port_hotplug_long_detect);
@@ -2536,7 +2539,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
bxt_port_hotplug_long_detect);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6db0b6b25f61..377a9770bae5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5973,8 +5973,10 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
{
struct intel_encoder *encoder = &intel_dig_port->base;
struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct intel_encoder *intel_encoder = &intel_dig_port->base;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
- encoder->hpd_pin = intel_hpd_pin(encoder->port);
+ encoder->hpd_pin = intel_hpd_pin_default(dev_priv, encoder->port);
switch (encoder->port) {
case PORT_A:
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6f460c4534fa..cc76938cafc2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2047,7 +2047,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
if (WARN_ON(port == PORT_A))
return;
- intel_encoder->hpd_pin = intel_hpd_pin(port);
+ intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
if (HAS_DDI(dev_priv))
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 875d5d218d5c..fe28c1ea84a5 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -78,12 +78,14 @@
/**
* intel_hpd_port - return port hard associated with certain pin.
+ * @dev_priv: private driver data pointer
* @pin: the hpd pin to get associated port
*
* Return port that is associatade with @pin and PORT_NONE if no port is
* hard associated with that @pin.
*/
-enum port intel_hpd_pin_to_port(enum hpd_pin pin)
+enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
+ enum hpd_pin pin)
{
switch (pin) {
case HPD_PORT_A:
@@ -95,6 +97,8 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
case HPD_PORT_D:
return PORT_D;
case HPD_PORT_E:
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ return PORT_F;
return PORT_E;
default:
return PORT_NONE; /* no port for this pin */
@@ -102,13 +106,17 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
}
/**
- * intel_hpd_pin - return pin hard associated with certain port.
+ * intel_hpd_pin_default - return default pin associated with certain port.
+ * @dev_priv: private driver data pointer
* @port: the hpd port to get associated pin
*
+ * It is only valid and used by digital port encoder.
+ *
* Return pin that is associatade with @port and HDP_NONE if no pin is
* hard associated with that @port.
*/
-enum hpd_pin intel_hpd_pin(enum port port)
+enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
+ enum port port)
{
switch (port) {
case PORT_A:
@@ -121,6 +129,9 @@ enum hpd_pin intel_hpd_pin(enum port port)
return HPD_PORT_D;
case PORT_E:
return HPD_PORT_E;
+ case PORT_F:
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ return HPD_PORT_E;
default:
MISSING_CASE(port);
return HPD_NONE;
@@ -417,7 +428,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!(BIT(i) & pin_mask))
continue;
- port = intel_hpd_pin_to_port(i);
+ port = intel_hpd_pin_to_port(dev_priv, i);
is_dig_port = port != PORT_NONE &&
dev_priv->hotplug.irq_port[port];
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 09/11] drm/i915/cnl: Enable DDI-F on Cannonlake.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (6 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 08/11] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 10/11] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
` (2 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
drivers/gpu/drm/i915/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
5 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dbc10e12d85..7ded5c7147ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -382,11 +382,13 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_C_LANES,
POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_E_LANES,
+ POWER_DOMAIN_PORT_DDI_F_LANES,
POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO,
POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_E_IO,
+ POWER_DOMAIN_PORT_DDI_F_IO,
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a69d52f9fec5..68368988343a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1304,6 +1304,7 @@ enum i915_power_well_id {
SKL_DISP_PW_DDI_B,
SKL_DISP_PW_DDI_C,
SKL_DISP_PW_DDI_D,
+ CNL_DISP_PW_DDI_F = 6,
GLK_DISP_PW_AUX_A = 8,
GLK_DISP_PW_AUX_B,
@@ -8764,6 +8765,7 @@ enum skl_power_gate {
#define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
#define SFUSE_STRAP_CRT_DISABLED (1<<6)
+#define SFUSE_STRAP_DDIF_DETECTED (1<<3)
#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
#define SFUSE_STRAP_DDID_DETECTED (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f51645a08dca..5944592536a1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2868,6 +2868,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_E_IO;
break;
+ case PORT_F:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_F_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b3bde2211128..aef09372e30e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5641,6 +5641,8 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port)
return POWER_DOMAIN_PORT_DDI_D_LANES;
case PORT_E:
return POWER_DOMAIN_PORT_DDI_E_LANES;
+ case PORT_F:
+ return POWER_DOMAIN_PORT_DDI_F_LANES;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -13593,7 +13595,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (found || IS_GEN9_BC(dev_priv))
intel_ddi_init(dev_priv, PORT_A);
- /* DDI B, C and D detection is indicated by the SFUSE_STRAP
+ /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
* register */
found = I915_READ(SFUSE_STRAP);
@@ -13603,6 +13605,8 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_C);
if (found & SFUSE_STRAP_DDID_DETECTED)
intel_ddi_init(dev_priv, PORT_D);
+ if (found & SFUSE_STRAP_DDIF_DETECTED)
+ intel_ddi_init(dev_priv, PORT_F);
/*
* On SKL we don't have a way to detect DDI-E so we rely on VBT.
*/
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 335832b46f86..d5e8f01cc0ff 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -94,6 +94,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
return "PORT_DDI_E_LANES";
+ case POWER_DOMAIN_PORT_DDI_F_LANES:
+ return "PORT_DDI_F_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -104,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_D_IO";
case POWER_DOMAIN_PORT_DDI_E_IO:
return "PORT_DDI_E_IO";
+ case POWER_DOMAIN_PORT_DDI_F_IO:
+ return "PORT_DDI_F_IO";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -1840,6 +1844,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2390,6 +2397,12 @@ static struct i915_power_well cnl_power_wells[] = {
.id = SKL_DISP_PW_DDI_D,
},
{
+ .name = "DDI F IO power well",
+ .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_DDI_F,
+ },
+ {
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 10/11] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (7 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 09/11] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 11/11] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
2017-12-22 22:58 ` ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage.
v2: Make commit message more generic.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 377a9770bae5..1b80a0ac4fd9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -238,8 +238,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
- if (port == PORT_A || port == PORT_D ||
- voltage == VOLTAGE_INFO_0_85V)
+ if (voltage == VOLTAGE_INFO_0_85V ||
+ (!IS_CNL_WITH_PORT_F(dev_priv) && (port == PORT_A ||
+ port == PORT_D)))
size -= 2;
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 11/11] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (8 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 10/11] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
@ 2017-12-22 22:23 ` Rodrigo Vivi
2017-12-22 22:58 ` ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
10 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 22:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.
This macro style is a deviation from the original definition in use
for other platforms, but it at least avoid code duplication.
Other smart alternatives like providing a joint list was also considered
but it would require some extra memory handling that would be
a deviation from the original simplistic definitions here anyways,
plus requiring extra tests and possibly creating some corner cases
for one single platform. So let's move with the simplest and safest
approach.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 177 +++++++++++++++++---------------
1 file changed, 94 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d5e8f01cc0ff..edc9c3ce7fd0 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2313,89 +2313,96 @@ static struct i915_power_well glk_power_wells[] = {
},
};
+#define basic_cnl_power_wells \
+ { \
+ .name = "always-on", \
+ .always_on = 1, \
+ .domains = POWER_DOMAIN_MASK, \
+ .ops = &i9xx_always_on_power_well_ops, \
+ .id = I915_DISP_PW_ALWAYS_ON, \
+ }, \
+ { \
+ .name = "power well 1", \
+ /* Handled by the DMC firmware */ \
+ .domains = 0, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_1, \
+ { \
+ .hsw.has_fuses = true, \
+ }, \
+ }, \
+ { \
+ .name = "AUX A", \
+ .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_A, \
+ }, \
+ { \
+ .name = "AUX B", \
+ .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_B, \
+ }, \
+ { \
+ .name = "AUX C", \
+ .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_C, \
+ }, \
+ { \
+ .name = "AUX D", \
+ .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_D, \
+ }, \
+ { \
+ .name = "DC off", \
+ .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, \
+ .ops = &gen9_dc_off_power_well_ops, \
+ .id = SKL_DISP_PW_DC_OFF, \
+ }, \
+ { \
+ .name = "power well 2", \
+ .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_2, \
+ { \
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), \
+ .hsw.has_vga = true, \
+ .hsw.has_fuses = true, \
+ }, \
+ }, \
+ { \
+ .name = "DDI A IO power well", \
+ .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_DDI_A, \
+ }, \
+ { \
+ .name = "DDI B IO power well", \
+ .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_DDI_B, \
+ }, \
+ { \
+ .name = "DDI C IO power well", \
+ .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_DDI_C, \
+ }, \
+ { \
+ .name = "DDI D IO power well", \
+ .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_DDI_D, \
+ }
+
static struct i915_power_well cnl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = 1,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "AUX A",
- .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_A,
- },
- {
- .name = "AUX B",
- .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_B,
- },
- {
- .name = "AUX C",
- .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_C,
- },
- {
- .name = "AUX D",
- .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_D,
- },
- {
- .name = "DC off",
- .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO power well",
- .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_DDI_A,
- },
- {
- .name = "DDI B IO power well",
- .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
- },
- {
- .name = "DDI C IO power well",
- .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
- },
- {
- .name = "DDI D IO power well",
- .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_D,
- },
+ basic_cnl_power_wells,
+};
+
+static struct i915_power_well cnl_power_wells_with_port_f[] = {
+ basic_cnl_power_wells,
{
.name = "DDI F IO power well",
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
@@ -2522,7 +2529,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
} else if (IS_GEN9_BC(dev_priv)) {
set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
- set_power_wells(power_domains, cnl_power_wells);
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ set_power_wells(power_domains,
+ cnl_power_wells_with_port_f);
+ else
+ set_power_wells(power_domains, cnl_power_wells);
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
--
2.13.6
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (9 preceding siblings ...)
2017-12-22 22:23 ` [PATCH 11/11] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
@ 2017-12-22 22:58 ` Patchwork
2017-12-22 23:06 ` Rodrigo Vivi
10 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2017-12-22 22:58 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
URL : https://patchwork.freedesktop.org/series/35744/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Add Port F definition.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_drv.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_drv.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.h
Patch failed at 0002 drm/i915/cnl: Add Port F definition.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2017-12-22 22:58 ` ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
@ 2017-12-22 23:06 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 23:06 UTC (permalink / raw)
To: intel-gfx
On Fri, Dec 22, 2017 at 10:58:03PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
> URL : https://patchwork.freedesktop.org/series/35744/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
> Applying: drm/i915/cnl: Add Port F definition.
> error: Failed to merge in the changes.
> Using index info to reconstruct a base tree...
> M drivers/gpu/drm/i915/i915_drv.h
Duh! I knew this conflict was comming,
I acked the header changes, I tagged it this morning,
but I forgot to rebase my patches from yesterday to today's drm-tip :/
> Falling back to patching base and 3-way merge...
> Auto-merging drivers/gpu/drm/i915/i915_drv.h
> CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.h
> Patch failed at 0002 drm/i915/cnl: Add Port F definition.
> The copy of the patch that failed is found in: .git/rebase-apply/patch
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".
>
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 02/11] drm/i915/cnl: Add Port F definition.
2017-12-22 23:18 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
2017-12-26 20:50 ` Pandiyan, Dhinakaran
@ 2018-01-11 14:22 ` Paulo Zanoni
1 sibling, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-01-11 14:22 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Lucas De Marchi
Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu:
> Some Cannonlake SKUs will come with a full split between
> port A and port E. This will be called port F although it
> is not a 6th port, but only a split.
I think that a small comment explaining that port F support is still
not complete even with this patch would help.
One more comment below.
>
> v2: Fix size of dvo_ports found by Ander.
> v3: Adding missing cases from intel_bios.c for Port_F
> v4: Adding other missing cases and fix the commit message.
> v5: Rebase on top of display headers rework.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_bios.c | 9 +++++++++
> drivers/gpu/drm/i915/intel_display.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 2 ++
> drivers/gpu/drm/i915/intel_vbt_defs.h | 2 ++
> include/drm/i915_component.h | 3 +--
> 5 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 51108ffc28d1..59a150e2adce 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1140,6 +1140,7 @@ static void parse_ddi_port(struct
> drm_i915_private *dev_priv, enum port port,
> {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> + {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> };
>
> /*
> @@ -1688,6 +1689,7 @@ bool intel_bios_is_port_present(struct
> drm_i915_private *dev_priv, enum port por
> [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
> [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
> [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
> + [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
> };
> int i;
>
> @@ -1726,6 +1728,7 @@ bool intel_bios_is_port_edp(struct
> drm_i915_private *dev_priv, enum port port)
> [PORT_C] = DVO_PORT_DPC,
> [PORT_D] = DVO_PORT_DPD,
> [PORT_E] = DVO_PORT_DPE,
> + [PORT_F] = DVO_PORT_DPF,
> };
> int i;
>
> @@ -1761,6 +1764,7 @@ static bool child_dev_is_dp_dual_mode(const
> struct child_device_config *child,
> [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
> [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
> [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
> + [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
> };
>
> if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
> @@ -1927,6 +1931,11 @@ intel_bios_is_lspcon_present(struct
> drm_i915_private *dev_priv,
> if (port == PORT_D)
> return true;
> break;
> + case DVO_PORT_DPF:
> + case DVO_PORT_HDMIF:
> + if (port == PORT_F)
> + return true;
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index a0d2b6169361..e47638931b51 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -119,6 +119,7 @@ enum port {
> PORT_C,
> PORT_D,
> PORT_E,
> + PORT_F,
>
> I915_MAX_PORTS
> };
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 35c5299feab6..71721de39e6b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1378,6 +1378,7 @@ static i915_reg_t skl_aux_ctl_reg(struct
> drm_i915_private *dev_priv,
> case PORT_B:
> case PORT_C:
> case PORT_D:
> + case PORT_F:
> return DP_AUX_CH_CTL(port);
> default:
> MISSING_CASE(port);
> @@ -1393,6 +1394,7 @@ static i915_reg_t skl_aux_data_reg(struct
> drm_i915_private *dev_priv,
> case PORT_B:
> case PORT_C:
> case PORT_D:
> + case PORT_F:
> return DP_AUX_CH_DATA(port, index);
> default:
> MISSING_CASE(port);
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index e3d7745a9151..8713e8295957 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -299,6 +299,8 @@ struct bdb_general_features {
> #define DVO_PORT_DPA 10
> #define DVO_PORT_DPE 11
> /* 193 */
> #define DVO_PORT_HDMIE 12
> /* 193 */
> +#define DVO_PORT_DPF 13
> +#define DVO_PORT_HDMIF 14
Needs ones more tab before the number. Besides, I suppose we could "/*
N/A */" or /* Missing from spec */ or something that clarifies that
it's not that our code is missing the version, it's the spec that
doesn't have it.
With those two things addressed:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> #define DVO_PORT_MIPIA 21
> /* 171 */
> #define DVO_PORT_MIPIB 22
> /* 171 */
> #define DVO_PORT_MIPIC 23
> /* 171 */
> diff --git a/include/drm/i915_component.h
> b/include/drm/i915_component.h
> index 545c6e0fea7d..346b1f5cb180 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -26,9 +26,8 @@
>
> /* MAX_PORT is the number of port
> * It must be sync with I915_MAX_PORTS defined i915_drv.h
> - * 5 should be enough as only HSW, BDW, SKL need such fix.
> */
> -#define MAX_PORTS 5
> +#define MAX_PORTS 6
>
> /**
> * struct i915_audio_component_ops - Ops implemented by i915 driver,
> called by hda driver
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 02/11] drm/i915/cnl: Add Port F definition.
2017-12-26 20:50 ` Pandiyan, Dhinakaran
@ 2017-12-28 16:45 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-28 16:45 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, De Marchi, Lucas
On Tue, Dec 26, 2017 at 08:50:57PM +0000, Pandiyan, Dhinakaran wrote:
>
> On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> > Some Cannonlake SKUs will come with a full split between
> > port A and port E. This will be called port F although it
> > is not a 6th port, but only a split.
>
> I am not sure if this is said in this spec.
Yeap... I fully understand you.
I could only read like this after Art pin point me the info.
Cannonlake Display Connections
SKU Differences
Display PHY
1 eDP + 4 DDI = (A, B, C, D, F)
And previous SKUs are maximum
1 eDP + 3 DDI = (A, B, C, D)
Plus the fact that port F interrupts re-use bits from portE
making DDI-E totally useless when DDI-F is present.
>
> From to what I can read and understand -
> 1) port A and port E can share lanes.
There is no E in any CNL SKU.
> 2) port F and port E mutually exclusive usage.
Right.
>
> So, you could have port A(x4) and port F(x4)
> or port A(x2) and port E(x2)
This is exactly why Port F was created for. A Full split
so you don't have to reduce eDP lanes when the "4th DDI" is in use.
In HW engineer words: "Full port split".
My understanding is that nowadays eDPs are requesting more
data bandwidth so 2 lanes approach was useless. Hence the port split.
> but doesn't really say port F is not a different port from port E.
Exactly. but port E was never a full port... it was just stealing 2 lanes
from port A. So now port F comes to the picture to avoid that, but reusing
a lot from port E.
> Secondly, I also see that port F and port E have separate DDI_BUF_CTL
> and DDI_AUX_CTL registers.
Oh yeah... This is indeed confusing in the current design.
Really strange that the registers for port E weren't fully removed
from spec. But everything else makes clear that these registers for port E
are useless for all current SKUs. Maybe at some point they considered
the A(x2), E(x2), F(x2) and changed their minds later, maybe they just forgot
to remove from there, maybe it was just easier to add a new range that
really don't touch nor interact with port A in any ways....
Thanks,
Rodrigo.
>
> >
> > v2: Fix size of dvo_ports found by Ander.
> > v3: Adding missing cases from intel_bios.c for Port_F
> > v4: Adding other missing cases and fix the commit message.
> > v5: Rebase on top of display headers rework.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_bios.c | 9 +++++++++
> > drivers/gpu/drm/i915/intel_display.h | 1 +
> > drivers/gpu/drm/i915/intel_dp.c | 2 ++
> > drivers/gpu/drm/i915/intel_vbt_defs.h | 2 ++
> > include/drm/i915_component.h | 3 +--
> > 5 files changed, 15 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> > index 51108ffc28d1..59a150e2adce 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -1140,6 +1140,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
> > {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> > {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> > {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> > + {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> > };
> >
> > /*
> > @@ -1688,6 +1689,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
> > [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
> > [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
> > [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
> > + [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
> > };
> > int i;
> >
> > @@ -1726,6 +1728,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
> > [PORT_C] = DVO_PORT_DPC,
> > [PORT_D] = DVO_PORT_DPD,
> > [PORT_E] = DVO_PORT_DPE,
> > + [PORT_F] = DVO_PORT_DPF,
> > };
> > int i;
> >
> > @@ -1761,6 +1764,7 @@ static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
> > [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
> > [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
> > [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
> > + [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
> > };
> >
> > if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
> > @@ -1927,6 +1931,11 @@ intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
> > if (port == PORT_D)
> > return true;
> > break;
> > + case DVO_PORT_DPF:
> > + case DVO_PORT_HDMIF:
> > + if (port == PORT_F)
> > + return true;
> > + break;
> > default:
> > break;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> > index a0d2b6169361..e47638931b51 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -119,6 +119,7 @@ enum port {
> > PORT_C,
> > PORT_D,
> > PORT_E,
> > + PORT_F,
> >
> > I915_MAX_PORTS
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 35c5299feab6..71721de39e6b 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1378,6 +1378,7 @@ static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > case PORT_B:
> > case PORT_C:
> > case PORT_D:
> > + case PORT_F:
> > return DP_AUX_CH_CTL(port);
> > default:
> > MISSING_CASE(port);
> > @@ -1393,6 +1394,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
> > case PORT_B:
> > case PORT_C:
> > case PORT_D:
> > + case PORT_F:
> > return DP_AUX_CH_DATA(port, index);
> > default:
> > MISSING_CASE(port);
> > diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> > index e3d7745a9151..8713e8295957 100644
> > --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> > @@ -299,6 +299,8 @@ struct bdb_general_features {
> > #define DVO_PORT_DPA 10
> > #define DVO_PORT_DPE 11 /* 193 */
> > #define DVO_PORT_HDMIE 12 /* 193 */
> > +#define DVO_PORT_DPF 13
> > +#define DVO_PORT_HDMIF 14
> > #define DVO_PORT_MIPIA 21 /* 171 */
> > #define DVO_PORT_MIPIB 22 /* 171 */
> > #define DVO_PORT_MIPIC 23 /* 171 */
> > diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> > index 545c6e0fea7d..346b1f5cb180 100644
> > --- a/include/drm/i915_component.h
> > +++ b/include/drm/i915_component.h
> > @@ -26,9 +26,8 @@
> >
> > /* MAX_PORT is the number of port
> > * It must be sync with I915_MAX_PORTS defined i915_drv.h
> > - * 5 should be enough as only HSW, BDW, SKL need such fix.
> > */
> > -#define MAX_PORTS 5
> > +#define MAX_PORTS 6
> >
> > /**
> > * struct i915_audio_component_ops - Ops implemented by i915 driver, called by hda driver
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 02/11] drm/i915/cnl: Add Port F definition.
2017-12-22 23:18 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
@ 2017-12-26 20:50 ` Pandiyan, Dhinakaran
2017-12-28 16:45 ` Rodrigo Vivi
2018-01-11 14:22 ` Paulo Zanoni
1 sibling, 1 reply; 17+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-12-26 20:50 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> Some Cannonlake SKUs will come with a full split between
> port A and port E. This will be called port F although it
> is not a 6th port, but only a split.
I am not sure if this is said in this spec.
From to what I can read and understand -
1) port A and port E can share lanes.
2) port F and port E mutually exclusive usage.
So, you could have port A(x4) and port F(x4)
or port A(x2) and port E(x2)
but doesn't really say port F is not a different port from port E.
Secondly, I also see that port F and port E have separate DDI_BUF_CTL
and DDI_AUX_CTL registers.
>
> v2: Fix size of dvo_ports found by Ander.
> v3: Adding missing cases from intel_bios.c for Port_F
> v4: Adding other missing cases and fix the commit message.
> v5: Rebase on top of display headers rework.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_bios.c | 9 +++++++++
> drivers/gpu/drm/i915/intel_display.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 2 ++
> drivers/gpu/drm/i915/intel_vbt_defs.h | 2 ++
> include/drm/i915_component.h | 3 +--
> 5 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 51108ffc28d1..59a150e2adce 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1140,6 +1140,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
> {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> + {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> };
>
> /*
> @@ -1688,6 +1689,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
> [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
> [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
> [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
> + [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
> };
> int i;
>
> @@ -1726,6 +1728,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
> [PORT_C] = DVO_PORT_DPC,
> [PORT_D] = DVO_PORT_DPD,
> [PORT_E] = DVO_PORT_DPE,
> + [PORT_F] = DVO_PORT_DPF,
> };
> int i;
>
> @@ -1761,6 +1764,7 @@ static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
> [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
> [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
> [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
> + [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
> };
>
> if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
> @@ -1927,6 +1931,11 @@ intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
> if (port == PORT_D)
> return true;
> break;
> + case DVO_PORT_DPF:
> + case DVO_PORT_HDMIF:
> + if (port == PORT_F)
> + return true;
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index a0d2b6169361..e47638931b51 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -119,6 +119,7 @@ enum port {
> PORT_C,
> PORT_D,
> PORT_E,
> + PORT_F,
>
> I915_MAX_PORTS
> };
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 35c5299feab6..71721de39e6b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1378,6 +1378,7 @@ static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
> case PORT_B:
> case PORT_C:
> case PORT_D:
> + case PORT_F:
> return DP_AUX_CH_CTL(port);
> default:
> MISSING_CASE(port);
> @@ -1393,6 +1394,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
> case PORT_B:
> case PORT_C:
> case PORT_D:
> + case PORT_F:
> return DP_AUX_CH_DATA(port, index);
> default:
> MISSING_CASE(port);
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index e3d7745a9151..8713e8295957 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -299,6 +299,8 @@ struct bdb_general_features {
> #define DVO_PORT_DPA 10
> #define DVO_PORT_DPE 11 /* 193 */
> #define DVO_PORT_HDMIE 12 /* 193 */
> +#define DVO_PORT_DPF 13
> +#define DVO_PORT_HDMIF 14
> #define DVO_PORT_MIPIA 21 /* 171 */
> #define DVO_PORT_MIPIB 22 /* 171 */
> #define DVO_PORT_MIPIC 23 /* 171 */
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index 545c6e0fea7d..346b1f5cb180 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -26,9 +26,8 @@
>
> /* MAX_PORT is the number of port
> * It must be sync with I915_MAX_PORTS defined i915_drv.h
> - * 5 should be enough as only HSW, BDW, SKL need such fix.
> */
> -#define MAX_PORTS 5
> +#define MAX_PORTS 6
>
> /**
> * struct i915_audio_component_ops - Ops implemented by i915 driver, called by hda driver
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 02/11] drm/i915/cnl: Add Port F definition.
2017-12-22 23:18 [PATCH 01/11] " Rodrigo Vivi
@ 2017-12-22 23:18 ` Rodrigo Vivi
2017-12-26 20:50 ` Pandiyan, Dhinakaran
2018-01-11 14:22 ` Paulo Zanoni
0 siblings, 2 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-12-22 23:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Some Cannonlake SKUs will come with a full split between
port A and port E. This will be called port F although it
is not a 6th port, but only a split.
v2: Fix size of dvo_ports found by Ander.
v3: Adding missing cases from intel_bios.c for Port_F
v4: Adding other missing cases and fix the commit message.
v5: Rebase on top of display headers rework.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 9 +++++++++
drivers/gpu/drm/i915/intel_display.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_vbt_defs.h | 2 ++
include/drm/i915_component.h | 3 +--
5 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 51108ffc28d1..59a150e2adce 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1140,6 +1140,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
{DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
{DVO_PORT_HDMID, DVO_PORT_DPD, -1},
{DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
+ {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
};
/*
@@ -1688,6 +1689,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por
[PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+ [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
int i;
@@ -1726,6 +1728,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
[PORT_C] = DVO_PORT_DPC,
[PORT_D] = DVO_PORT_DPD,
[PORT_E] = DVO_PORT_DPE,
+ [PORT_F] = DVO_PORT_DPF,
};
int i;
@@ -1761,6 +1764,7 @@ static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
[PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
[PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
+ [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
@@ -1927,6 +1931,11 @@ intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
if (port == PORT_D)
return true;
break;
+ case DVO_PORT_DPF:
+ case DVO_PORT_HDMIF:
+ if (port == PORT_F)
+ return true;
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index a0d2b6169361..e47638931b51 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -119,6 +119,7 @@ enum port {
PORT_C,
PORT_D,
PORT_E,
+ PORT_F,
I915_MAX_PORTS
};
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 35c5299feab6..71721de39e6b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1378,6 +1378,7 @@ static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1393,6 +1394,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index e3d7745a9151..8713e8295957 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -299,6 +299,8 @@ struct bdb_general_features {
#define DVO_PORT_DPA 10
#define DVO_PORT_DPE 11 /* 193 */
#define DVO_PORT_HDMIE 12 /* 193 */
+#define DVO_PORT_DPF 13
+#define DVO_PORT_HDMIF 14
#define DVO_PORT_MIPIA 21 /* 171 */
#define DVO_PORT_MIPIB 22 /* 171 */
#define DVO_PORT_MIPIC 23 /* 171 */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 545c6e0fea7d..346b1f5cb180 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -26,9 +26,8 @@
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
- * 5 should be enough as only HSW, BDW, SKL need such fix.
*/
-#define MAX_PORTS 5
+#define MAX_PORTS 6
/**
* struct i915_audio_component_ops - Ops implemented by i915 driver, called by hda driver
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-01-11 14:22 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-22 22:23 [PATCH 01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 03/11] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 04/11] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 05/11] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 06/11] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 07/11] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 08/11] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 09/11] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 10/11] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
2017-12-22 22:23 ` [PATCH 11/11] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
2017-12-22 22:58 ` ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
2017-12-22 23:06 ` Rodrigo Vivi
2017-12-22 23:18 [PATCH 01/11] " Rodrigo Vivi
2017-12-22 23:18 ` [PATCH 02/11] drm/i915/cnl: Add Port F definition Rodrigo Vivi
2017-12-26 20:50 ` Pandiyan, Dhinakaran
2017-12-28 16:45 ` Rodrigo Vivi
2018-01-11 14:22 ` Paulo Zanoni
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