From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> To: davem@davemloft.net, netdev@vger.kernel.org, ingrassia@epigenesys.com Cc: linus.luessing@c0d3.blue, khilman@baylibre.com, linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, Martin Blumenstingl <martin.blumenstingl@googlemail.com> Subject: [PATCH net-next v5 4/4] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock Date: Mon, 15 Jan 2018 18:10:15 +0100 [thread overview] Message-ID: <20180115171015.1118-5-martin.blumenstingl@googlemail.com> (raw) In-Reply-To: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> On Meson8b the only valid input clock is MPLL2. The bootloader configures that to run at 500002394Hz which cannot be divided evenly down to 125MHz using the m250_div clock. Currently the common clock framework chooses a m250_div of 2 - with the internal fixed "divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz above the requested 125MHz). Letting the common clock framework propagate the rate changes up to the parent of m250_mux allows us to get the best possible clock rate. With this patch the common clock framework calculates a rate of very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock (which is the mux input). Dividing that by 2 (which is an internal, fixed divider for the RGMII TX clock) gives us an RGMII TX clock of 124999850Hz (which is only 150Hz off the requested 125MHz, compared to 1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel sources). SoCs from the Meson GX series are not affected by this change because the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine since it's running at 1GHz, so it's already a multiple of 250MHz and 125MHz). Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index de01ce75a1b1..5270d26f0bc6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -112,7 +112,7 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev)); init.name = clk_name; init.ops = &clk_mux_ops; - init.flags = 0; + init.flags = CLK_SET_RATE_PARENT; init.parent_names = mux_parent_names; init.num_parents = MUX_CLK_NUM_PARENTS; -- 2.15.1
WARNING: multiple messages have this Message-ID (diff)
From: martin.blumenstingl@googlemail.com (Martin Blumenstingl) To: linus-amlogic@lists.infradead.org Subject: [PATCH net-next v5 4/4] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock Date: Mon, 15 Jan 2018 18:10:15 +0100 [thread overview] Message-ID: <20180115171015.1118-5-martin.blumenstingl@googlemail.com> (raw) In-Reply-To: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> On Meson8b the only valid input clock is MPLL2. The bootloader configures that to run at 500002394Hz which cannot be divided evenly down to 125MHz using the m250_div clock. Currently the common clock framework chooses a m250_div of 2 - with the internal fixed "divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz above the requested 125MHz). Letting the common clock framework propagate the rate changes up to the parent of m250_mux allows us to get the best possible clock rate. With this patch the common clock framework calculates a rate of very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock (which is the mux input). Dividing that by 2 (which is an internal, fixed divider for the RGMII TX clock) gives us an RGMII TX clock of 124999850Hz (which is only 150Hz off the requested 125MHz, compared to 1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel sources). SoCs from the Meson GX series are not affected by this change because the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine since it's running at 1GHz, so it's already a multiple of 250MHz and 125MHz). Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index de01ce75a1b1..5270d26f0bc6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -112,7 +112,7 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev)); init.name = clk_name; init.ops = &clk_mux_ops; - init.flags = 0; + init.flags = CLK_SET_RATE_PARENT; init.parent_names = mux_parent_names; init.num_parents = MUX_CLK_NUM_PARENTS; -- 2.15.1
next prev parent reply other threads:[~2018-01-15 17:10 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-01-15 17:10 [PATCH net-next v5 0/4] dwmac-meson8b: clock fixes for Meson8b Martin Blumenstingl 2018-01-15 17:10 ` Martin Blumenstingl 2018-01-15 17:10 ` [PATCH net-next v5 1/4] net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode Martin Blumenstingl 2018-01-15 17:10 ` Martin Blumenstingl 2018-01-15 17:10 ` [PATCH net-next v5 2/4] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration Martin Blumenstingl 2018-01-15 17:10 ` Martin Blumenstingl 2018-01-15 17:10 ` [PATCH net-next v5 3/4] net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b Martin Blumenstingl 2018-01-15 17:10 ` Martin Blumenstingl 2018-01-15 17:10 ` Martin Blumenstingl [this message] 2018-01-15 17:10 ` [PATCH net-next v5 4/4] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock Martin Blumenstingl 2018-01-15 22:06 ` [PATCH net-next v5 0/4] dwmac-meson8b: clock fixes for Meson8b Emiliano Ingrassia 2018-01-15 22:06 ` Emiliano Ingrassia 2018-01-16 8:25 ` Yixun Lan 2018-01-16 9:37 ` Jerome Brunet 2018-01-16 11:17 ` Martin Blumenstingl 2018-01-16 17:19 ` Jerome Brunet 2018-01-18 10:27 ` Yixun Lan 2018-01-18 10:27 ` Yixun Lan 2018-01-18 20:03 ` Martin Blumenstingl 2018-01-18 20:03 ` Martin Blumenstingl 2018-01-17 19:41 ` David Miller 2018-01-17 19:41 ` David Miller
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