* [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
@ 2018-01-20 0:05 Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
` (18 more replies)
0 siblings, 19 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx
Cc: Paulo Zanoni, Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
The only difference is that this SKUs has the full
Port A/E split named as Port F.
But since SKUs differences don't matter on the platform
definition group and ids, let's merge all off them together.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
v6: Unify in a way that we don't break early-quirks.c
v7: Remove GT reference since it doesn't matter here (Paulo)
Also move IS_CNL_WITH_PORT_F macro to this patch to
make it easier for review this part and also to get
used sooner.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 5 ++---
include/drm/i915_pciids.h | 18 +++++++-----------
3 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8333692dac5a..3d3727829ac7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2647,6 +2647,8 @@ intel_info(const struct drm_i915_private *dev_priv)
(dev_priv)->info.gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
(dev_priv)->info.gt == 3)
+#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f28c165fc49d..7eb3d5e4350e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -571,7 +571,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
.ddb_size = 1024, \
GLK_COLORS
-static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
+static const struct intel_device_info intel_cannonlake_info __initconst = {
GEN10_FEATURES,
.is_alpha_support = 1,
.platform = INTEL_CANNONLAKE,
@@ -649,8 +649,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
- INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
- INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
+ INTEL_CNL_IDS(&intel_cannonlake_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 5db0458dd832..9e1fe6634424 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -414,24 +414,20 @@
INTEL_CFL_U_GT2_IDS(info), \
INTEL_CFL_U_GT3_IDS(info)
-/* CNL U 2+2 */
-#define INTEL_CNL_U_GT2_IDS(info) \
+/* CNL */
+#define INTEL_CNL_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
INTEL_VGA_DEVICE(0x5A5A, info), \
INTEL_VGA_DEVICE(0x5A42, info), \
- INTEL_VGA_DEVICE(0x5A4A, info)
-
-/* CNL Y 2+2 */
-#define INTEL_CNL_Y_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
INTEL_VGA_DEVICE(0x5A49, info), \
INTEL_VGA_DEVICE(0x5A71, info), \
- INTEL_VGA_DEVICE(0x5A79, info)
-
-#define INTEL_CNL_IDS(info) \
- INTEL_CNL_U_GT2_IDS(info), \
- INTEL_CNL_Y_GT2_IDS(info)
+ INTEL_VGA_DEVICE(0x5A79, info), \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info), \
+ INTEL_VGA_DEVICE(0x5A44, info)
#endif /* _I915_PCIIDS_H */
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 02/10] drm/i915/cnl: Add AUX-F support
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-22 23:42 ` Pandiyan, Dhinakaran
2018-01-20 0:05 ` [PATCH 03/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
` (17 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Rebase and fix commit message.
v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
v6: Rebase on top of display headers rework.
v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_display.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
6 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d3727829ac7..7206c7c5f81c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1255,6 +1255,7 @@ enum modeset_restore {
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
+#define DP_AUX_F 0x50
#define DDC_PIN_B 0x05
#define DDC_PIN_C 0x04
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index db3466ec6faa..0af970d4b3cf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ tmp_mask |= CNL_AUX_CHANNEL_F;
+
if (iir & tmp_mask) {
dp_aux_irq_handler(dev_priv);
found = true;
@@ -3617,6 +3620,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ de_port_masked |= CNL_AUX_CHANNEL_F;
+
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 83b3f02d33b7..381c6758f3a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1312,6 +1312,7 @@ enum i915_power_well_id {
CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
CNL_DISP_PW_AUX_D,
+ CNL_DISP_PW_AUX_F = 13,
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
@@ -5284,6 +5285,13 @@ enum {
#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
+
#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
@@ -6939,6 +6947,7 @@ enum {
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
#define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define CNL_AUX_CHANNEL_F (1 << 28)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define GEN9_AUX_CHANNEL_C (1 << 26)
#define GEN9_AUX_CHANNEL_B (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index e47638931b51..30fa2041a45f 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -172,6 +172,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_AUX_F,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2e887999915..ae3b0b030177 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1323,6 +1323,9 @@ static enum port intel_aux_port(struct drm_i915_private *dev_priv,
case DP_AUX_D:
aux_port = PORT_D;
break;
+ case DP_AUX_F:
+ aux_port = PORT_F;
+ break;
default:
MISSING_CASE(info->alternate_aux_channel);
aux_port = PORT_A;
@@ -1342,6 +1345,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1356,6 +1360,7 @@ static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
@@ -6224,6 +6229,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
/* FIXME: Check VBT for actual wiring of PORT E */
intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
break;
+ case PORT_F:
+ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
+ break;
default:
MISSING_CASE(encoder->port);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5b1aa4b9c72c..27174d49a529 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_C";
case POWER_DOMAIN_AUX_D:
return "AUX_D";
+ case POWER_DOMAIN_AUX_F:
+ return "AUX_F";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1855,6 +1857,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
@@ -2405,6 +2410,12 @@ static struct i915_power_well cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
+ {
+ .name = "AUX F",
+ .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_AUX_F,
+ },
};
static int
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 03/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
` (16 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 381c6758f3a6..3ad9ad4a7918 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1964,7 +1964,7 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_DW2_LN0_B 0x162648
#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
-#define _CNL_PORT_TX_DW2_LN0_F 0x162A48
+#define _CNL_PORT_TX_DW2_LN0_F 0x162848
#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
_CNL_PORT_TX_DW2_GRP_AE, \
_CNL_PORT_TX_DW2_GRP_B, \
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 03/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-22 21:44 ` Pandiyan, Dhinakaran
2018-01-20 0:05 ` [PATCH 05/10] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
` (15 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
v2: Reuse _SHIFT definition to avoid complicated duplication (DK).
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ad9ad4a7918..861a7d5a27af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8838,10 +8838,12 @@ enum skl_power_gate {
* CNL Clocks
*/
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
-#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
-#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
+#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
+ (port)+10))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
+ (port)*2)
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 05/10] drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (2 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
` (14 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 978f22bb96c2..0d924ba42075 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2178,6 +2178,9 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
case PORT_D:
ddc_pin = GMBUS_PIN_4_CNP;
break;
+ case PORT_F:
+ ddc_pin = GMBUS_PIN_3_BXT;
+ break;
default:
MISSING_CASE(port);
ddc_pin = GMBUS_PIN_1_BXT;
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (3 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 05/10] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-22 16:40 ` Ville Syrjälä
2018-01-20 0:05 ` [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
` (13 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 144 ++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_lspcon.c | 3 +-
3 files changed, 72 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ae3b0b030177..4ff6fcf542e9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4487,173 +4487,170 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ibx_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = SDE_PORTB_HOTPLUG;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = SDE_PORTC_HOTPLUG;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = SDE_PORTD_HOTPLUG;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(SDEISR) & bit;
}
-static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool cpt_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = SDE_PORTB_HOTPLUG_CPT;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = SDE_PORTC_HOTPLUG_CPT;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(SDEISR) & bit;
}
-static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool spt_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_A:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
bit = SDE_PORTA_HOTPLUG_SPT;
break;
- case PORT_E:
+ case HPD_PORT_E:
bit = SDE_PORTE_HOTPLUG_SPT;
break;
default:
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
return I915_READ(SDEISR) & bit;
}
-static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool g4x_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool gm45_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ilk_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
else
- return ibx_digital_port_connected(dev_priv, port);
+ return ibx_digital_port_connected(encoder);
}
-static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool snb_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ivb_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *intel_dig_port)
+static bool bxt_digital_port_connected(struct intel_encoder *encoder)
{
- struct intel_encoder *intel_encoder = &intel_dig_port->base;
- enum port port;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
- switch (port) {
- case PORT_A:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
bit = BXT_DE_PORT_HP_DDIA;
break;
- case PORT_B:
+ case HPD_PORT_B:
bit = BXT_DE_PORT_HP_DDIB;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = BXT_DE_PORT_HP_DDIC;
break;
default:
- MISSING_CASE(port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
@@ -4662,33 +4659,33 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
/*
* intel_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
+ * @encoder: intel_encoder
*
* Return %true if @port is connected, %false otherwise.
*/
-bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+bool intel_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (HAS_GMCH_DISPLAY(dev_priv)) {
if (IS_GM45(dev_priv))
- return gm45_digital_port_connected(dev_priv, port);
+ return gm45_digital_port_connected(encoder);
else
- return g4x_digital_port_connected(dev_priv, port);
+ return g4x_digital_port_connected(encoder);
}
if (IS_GEN5(dev_priv))
- return ilk_digital_port_connected(dev_priv, port);
+ return ilk_digital_port_connected(encoder);
else if (IS_GEN6(dev_priv))
- return snb_digital_port_connected(dev_priv, port);
+ return snb_digital_port_connected(encoder);
else if (IS_GEN7(dev_priv))
- return ivb_digital_port_connected(dev_priv, port);
+ return ivb_digital_port_connected(encoder);
else if (IS_GEN8(dev_priv))
- return bdw_digital_port_connected(dev_priv, port);
+ return bdw_digital_port_connected(encoder);
else if (IS_GEN9_LP(dev_priv))
- return bxt_digital_port_connected(dev_priv, port);
+ return bxt_digital_port_connected(encoder);
else
- return spt_digital_port_connected(dev_priv, port);
+ return spt_digital_port_connected(encoder);
}
static struct edid *
@@ -4747,8 +4744,7 @@ intel_dp_long_pulse(struct intel_connector *connector)
/* Can't disconnect eDP, but you can close the lid... */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
- else if (intel_digital_port_connected(dev_priv,
- dp_to_dig_port(intel_dp)))
+ else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
status = intel_dp_detect_dpcd(intel_dp);
else
status = connector_status_disconnected;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a73a9f0d790f..9ae820f82235 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1671,8 +1671,7 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
-bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port);
+bool intel_digital_port_connected(struct intel_encoder *encoder);
/* intel_dp_aux_backlight.c */
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c
index dcbc786479f9..8ae8f42f430a 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -167,11 +167,10 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
unsigned long start = jiffies;
while (1) {
- if (intel_digital_port_connected(dev_priv, dig_port)) {
+ if (intel_digital_port_connected(&dig_port->base)) {
DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
jiffies_to_msecs(jiffies - start));
return;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (4 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-22 16:51 ` Ville Syrjälä
2018-01-20 0:05 ` [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
` (12 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so we can start upstreaming
this right now. If that SKU ever get a proper name
we come back and update it.
v4: Rebase on top of digital connected port using encoder
instead of port.
v5: Moved IS_CNL_WITH_PORT_F definition to the PCI IDs patch.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++--
drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_hotplug.c | 19 +++++++++++++++----
5 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7206c7c5f81c..0b5f8d887bfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2957,8 +2957,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
-enum port intel_hpd_pin_to_port(enum hpd_pin pin);
-enum hpd_pin intel_hpd_pin(enum port port);
+enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
+ enum hpd_pin pin);
+enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
+ enum port port);
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0af970d4b3cf..78af4594eb38 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1568,10 +1568,11 @@ static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
*
* Note that the caller is expected to zero out the masks initially.
*/
-static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
- u32 hotplug_trigger, u32 dig_hotplug_reg,
- const u32 hpd[HPD_NUM_PINS],
- bool long_pulse_detect(enum port port, u32 val))
+static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
+ u32 *pin_mask, u32 *long_mask,
+ u32 hotplug_trigger, u32 dig_hotplug_reg,
+ const u32 hpd[HPD_NUM_PINS],
+ bool long_pulse_detect(enum port port, u32 val))
{
enum port port;
int i;
@@ -1582,7 +1583,7 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
*pin_mask |= BIT(i);
- port = intel_hpd_pin_to_port(i);
+ port = intel_hpd_pin_to_port(dev_priv, i);
if (port == PORT_NONE)
continue;
@@ -1970,8 +1971,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
if (hotplug_trigger) {
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- hotplug_trigger, hpd_status_g4x,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, hotplug_trigger,
+ hpd_status_g4x,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1983,8 +1985,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
if (hotplug_trigger) {
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- hotplug_trigger, hpd_status_i915,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, hotplug_trigger,
+ hpd_status_i915,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
@@ -2185,7 +2188,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!hotplug_trigger)
return;
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
pch_port_hotplug_long_detect);
@@ -2327,8 +2330,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd_spt,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug_trigger, dig_hotplug_reg, hpd_spt,
spt_port_hotplug_long_detect);
}
@@ -2338,8 +2341,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
- dig_hotplug_reg, hpd_spt,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hotplug2_trigger, dig_hotplug_reg, hpd_spt,
spt_port_hotplug2_long_detect);
}
@@ -2359,7 +2362,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
ilk_port_hotplug_long_detect);
@@ -2536,7 +2539,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
dig_hotplug_reg, hpd,
bxt_port_hotplug_long_detect);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4ff6fcf542e9..4b963732454d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6205,8 +6205,10 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
{
struct intel_encoder *encoder = &intel_dig_port->base;
struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct intel_encoder *intel_encoder = &intel_dig_port->base;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
- encoder->hpd_pin = intel_hpd_pin(encoder->port);
+ encoder->hpd_pin = intel_hpd_pin_default(dev_priv, encoder->port);
switch (encoder->port) {
case PORT_A:
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0d924ba42075..f9a1a32fd272 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2334,7 +2334,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
if (WARN_ON(port == PORT_A))
return;
- intel_encoder->hpd_pin = intel_hpd_pin(port);
+ intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
if (HAS_DDI(dev_priv))
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 875d5d218d5c..fe28c1ea84a5 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -78,12 +78,14 @@
/**
* intel_hpd_port - return port hard associated with certain pin.
+ * @dev_priv: private driver data pointer
* @pin: the hpd pin to get associated port
*
* Return port that is associatade with @pin and PORT_NONE if no port is
* hard associated with that @pin.
*/
-enum port intel_hpd_pin_to_port(enum hpd_pin pin)
+enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
+ enum hpd_pin pin)
{
switch (pin) {
case HPD_PORT_A:
@@ -95,6 +97,8 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
case HPD_PORT_D:
return PORT_D;
case HPD_PORT_E:
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ return PORT_F;
return PORT_E;
default:
return PORT_NONE; /* no port for this pin */
@@ -102,13 +106,17 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
}
/**
- * intel_hpd_pin - return pin hard associated with certain port.
+ * intel_hpd_pin_default - return default pin associated with certain port.
+ * @dev_priv: private driver data pointer
* @port: the hpd port to get associated pin
*
+ * It is only valid and used by digital port encoder.
+ *
* Return pin that is associatade with @port and HDP_NONE if no pin is
* hard associated with that @port.
*/
-enum hpd_pin intel_hpd_pin(enum port port)
+enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
+ enum port port)
{
switch (port) {
case PORT_A:
@@ -121,6 +129,9 @@ enum hpd_pin intel_hpd_pin(enum port port)
return HPD_PORT_D;
case PORT_E:
return HPD_PORT_E;
+ case PORT_F:
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ return HPD_PORT_E;
default:
MISSING_CASE(port);
return HPD_NONE;
@@ -417,7 +428,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!(BIT(i) & pin_mask))
continue;
- port = intel_hpd_pin_to_port(i);
+ port = intel_hpd_pin_to_port(dev_priv, i);
is_dig_port = port != PORT_NONE &&
dev_priv->hotplug.irq_port[port];
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (5 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-23 3:12 ` Pandiyan, Dhinakaran
2018-01-20 0:05 ` [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
` (11 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
v6: Rebase on top of display headers rework.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
drivers/gpu/drm/i915/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/intel_display.h | 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
5 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 861a7d5a27af..32ec64eb2c5a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1304,6 +1304,7 @@ enum i915_power_well_id {
SKL_DISP_PW_DDI_B,
SKL_DISP_PW_DDI_C,
SKL_DISP_PW_DDI_D,
+ CNL_DISP_PW_DDI_F = 6,
GLK_DISP_PW_AUX_A = 8,
GLK_DISP_PW_AUX_B,
@@ -8939,6 +8940,7 @@ enum skl_power_gate {
#define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
#define SFUSE_STRAP_CRT_DISABLED (1<<6)
+#define SFUSE_STRAP_DDIF_DETECTED (1<<3)
#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
#define SFUSE_STRAP_DDID_DETECTED (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6260a882fbe4..ba56eea826d5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2904,6 +2904,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_E_IO;
break;
+ case PORT_F:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_F_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91f3c0a64596..d4942a5e23f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5633,6 +5633,8 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port)
return POWER_DOMAIN_PORT_DDI_D_LANES;
case PORT_E:
return POWER_DOMAIN_PORT_DDI_E_LANES;
+ case PORT_F:
+ return POWER_DOMAIN_PORT_DDI_F_LANES;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -13586,7 +13588,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (found || IS_GEN9_BC(dev_priv))
intel_ddi_init(dev_priv, PORT_A);
- /* DDI B, C and D detection is indicated by the SFUSE_STRAP
+ /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
* register */
found = I915_READ(SFUSE_STRAP);
@@ -13596,6 +13598,8 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_C);
if (found & SFUSE_STRAP_DDID_DETECTED)
intel_ddi_init(dev_priv, PORT_D);
+ if (found & SFUSE_STRAP_DDIF_DETECTED)
+ intel_ddi_init(dev_priv, PORT_F);
/*
* On SKL we don't have a way to detect DDI-E so we rely on VBT.
*/
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 30fa2041a45f..c4042e342f50 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -157,11 +157,13 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_C_LANES,
POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_E_LANES,
+ POWER_DOMAIN_PORT_DDI_F_LANES,
POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO,
POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_E_IO,
+ POWER_DOMAIN_PORT_DDI_F_IO,
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27174d49a529..433048ffa5c6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -94,6 +94,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
return "PORT_DDI_E_LANES";
+ case POWER_DOMAIN_PORT_DDI_F_LANES:
+ return "PORT_DDI_F_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -104,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_D_IO";
case POWER_DOMAIN_PORT_DDI_E_IO:
return "PORT_DDI_E_IO";
+ case POWER_DOMAIN_PORT_DDI_F_IO:
+ return "PORT_DDI_F_IO";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -1860,6 +1864,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
@@ -2411,6 +2418,12 @@ static struct i915_power_well cnl_power_wells[] = {
.id = SKL_DISP_PW_DDI_D,
},
{
+ .name = "DDI F IO power well",
+ .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_DDI_F,
+ },
+ {
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (6 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-22 16:46 ` Ville Syrjälä
2018-01-20 0:05 ` [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
` (10 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage.
v2: Make commit message more generic.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4b963732454d..36826460d8fb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -240,8 +240,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
- if (port == PORT_A || port == PORT_D ||
- voltage == VOLTAGE_INFO_0_85V)
+ if (voltage == VOLTAGE_INFO_0_85V ||
+ (!IS_CNL_WITH_PORT_F(dev_priv) && (port == PORT_A ||
+ port == PORT_D)))
size -= 2;
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (7 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
@ 2018-01-20 0:05 ` Rodrigo Vivi
2018-01-22 12:12 ` Imre Deak
2018-01-20 0:30 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
` (9 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-20 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.
This macro style is a deviation from the original definition in use
for other platforms, but it at least avoid code duplication.
Other smart alternatives like providing a joint list was also considered
but it would require some extra memory handling that would be
a deviation from the original simplistic definitions here anyways,
plus requiring extra tests and possibly creating some corner cases
for one single platform. So let's move with the simplest and safest
approach.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 177 +++++++++++++++++---------------
1 file changed, 94 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 433048ffa5c6..8dbc9b138ffd 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2334,89 +2334,96 @@ static struct i915_power_well glk_power_wells[] = {
},
};
+#define basic_cnl_power_wells \
+ { \
+ .name = "always-on", \
+ .always_on = 1, \
+ .domains = POWER_DOMAIN_MASK, \
+ .ops = &i9xx_always_on_power_well_ops, \
+ .id = I915_DISP_PW_ALWAYS_ON, \
+ }, \
+ { \
+ .name = "power well 1", \
+ /* Handled by the DMC firmware */ \
+ .domains = 0, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_1, \
+ { \
+ .hsw.has_fuses = true, \
+ }, \
+ }, \
+ { \
+ .name = "AUX A", \
+ .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_A, \
+ }, \
+ { \
+ .name = "AUX B", \
+ .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_B, \
+ }, \
+ { \
+ .name = "AUX C", \
+ .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_C, \
+ }, \
+ { \
+ .name = "AUX D", \
+ .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_AUX_D, \
+ }, \
+ { \
+ .name = "DC off", \
+ .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, \
+ .ops = &gen9_dc_off_power_well_ops, \
+ .id = SKL_DISP_PW_DC_OFF, \
+ }, \
+ { \
+ .name = "power well 2", \
+ .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_2, \
+ { \
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), \
+ .hsw.has_vga = true, \
+ .hsw.has_fuses = true, \
+ }, \
+ }, \
+ { \
+ .name = "DDI A IO power well", \
+ .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = CNL_DISP_PW_DDI_A, \
+ }, \
+ { \
+ .name = "DDI B IO power well", \
+ .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_DDI_B, \
+ }, \
+ { \
+ .name = "DDI C IO power well", \
+ .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_DDI_C, \
+ }, \
+ { \
+ .name = "DDI D IO power well", \
+ .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, \
+ .ops = &hsw_power_well_ops, \
+ .id = SKL_DISP_PW_DDI_D, \
+ }
+
static struct i915_power_well cnl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = 1,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "AUX A",
- .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_A,
- },
- {
- .name = "AUX B",
- .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_B,
- },
- {
- .name = "AUX C",
- .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_C,
- },
- {
- .name = "AUX D",
- .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_D,
- },
- {
- .name = "DC off",
- .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO power well",
- .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_DDI_A,
- },
- {
- .name = "DDI B IO power well",
- .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
- },
- {
- .name = "DDI C IO power well",
- .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
- },
- {
- .name = "DDI D IO power well",
- .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_D,
- },
+ basic_cnl_power_wells,
+};
+
+static struct i915_power_well cnl_power_wells_with_port_f[] = {
+ basic_cnl_power_wells,
{
.name = "DDI F IO power well",
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
@@ -2543,7 +2550,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
} else if (IS_GEN9_BC(dev_priv)) {
set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
- set_power_wells(power_domains, cnl_power_wells);
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ set_power_wells(power_domains,
+ cnl_power_wells_with_port_f);
+ else
+ set_power_wells(power_domains, cnl_power_wells);
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (8 preceding siblings ...)
2018-01-20 0:05 ` [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
@ 2018-01-20 0:30 ` Patchwork
2018-01-20 8:40 ` ✗ Fi.CI.IGT: warning " Patchwork
` (8 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-20 0:30 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
URL : https://patchwork.freedesktop.org/series/36828/
State : success
== Summary ==
Series 36828v1 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
https://patchwork.freedesktop.org/api/1.0/series/36828/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
pass -> DMESG-WARN (fi-elk-e7500) fdo#103989 +1
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:430s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:435s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:384s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:515s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:294s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:503s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:503s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:504s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:485s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:307s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:528s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:398s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:407s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:421s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:421s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:466s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:508s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:469s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:514s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:633s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:443s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:521s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:536s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:500s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:502s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:444s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:405s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:26 time:570s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:421s
85f8773e7d771137795eed8a9f1f5ed3e7f725b7 drm-tip: 2018y-01m-19d-21h-19m-11s UTC integration manifest
8d3779f6394b drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
a2551962c25b drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
0d02b4b199c6 drm/i915/cnl: Enable DDI-F on Cannonlake.
d5ade4a3d893 drm/i915/cnl: Add HPD support for Port F.
5e733bf5da5f drm/i915: For HPD connected port use hpd_pin instead of port.
1c5bff32da8d drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
97aa34aa3a96 drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
5b141965257f drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
e87eb870d82b drm/i915/cnl: Add AUX-F support
74b2dea2d2cf drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7729/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✗ Fi.CI.IGT: warning for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (9 preceding siblings ...)
2018-01-20 0:30 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
@ 2018-01-20 8:40 ` Patchwork
2018-01-22 16:56 ` [PATCH 01/10] " Ville Syrjälä
` (7 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-20 8:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
URL : https://patchwork.freedesktop.org/series/36828/
State : warning
== Summary ==
Test kms_flip:
Subgroup vblank-vs-dpms-suspend-interruptible:
fail -> PASS (shard-hsw) fdo#103540 +2
Subgroup vblank-vs-suspend:
skip -> PASS (shard-snb) fdo#102365 +1
Subgroup plain-flip-fb-recreate:
pass -> FAIL (shard-snb) fdo#100368 +1
Subgroup 2x-vblank-vs-dpms-suspend:
skip -> PASS (shard-hsw)
Subgroup 2x-vblank-vs-suspend-interruptible:
pass -> SKIP (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass -> FAIL (shard-snb) fdo#101623
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-apl) fdo#99912
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-toggle:
pass -> FAIL (shard-hsw) fdo#102670
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-apl total:2780 pass:1717 dwarn:1 dfail:0 fail:22 skip:1040 time:14656s
shard-hsw total:2707 pass:1672 dwarn:1 dfail:0 fail:11 skip:1021 time:14868s
shard-snb total:2780 pass:1314 dwarn:1 dfail:0 fail:14 skip:1451 time:7997s
Blacklisted hosts:
shard-kbl total:2780 pass:1813 dwarn:23 dfail:0 fail:25 skip:919 time:10916s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7729/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2018-01-20 0:05 ` [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
@ 2018-01-22 12:12 ` Imre Deak
2018-01-22 23:48 ` [PATCH] " Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2018-01-22 12:12 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi
On Fri, Jan 19, 2018 at 04:05:24PM -0800, Rodrigo Vivi wrote:
> SKUs that lacks on the full port F split will just time out
> when touching this power well bits, causing a noisy warn.
>
> This macro style is a deviation from the original definition in use
> for other platforms, but it at least avoid code duplication.
> Other smart alternatives like providing a joint list was also considered
> but it would require some extra memory handling that would be
> a deviation from the original simplistic definitions here anyways,
> plus requiring extra tests and possibly creating some corner cases
> for one single platform. So let's move with the simplest and safest
> approach.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 177 +++++++++++++++++---------------
> 1 file changed, 94 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 433048ffa5c6..8dbc9b138ffd 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2334,89 +2334,96 @@ static struct i915_power_well glk_power_wells[] = {
> },
> };
>
> +#define basic_cnl_power_wells \
> + { \
> + .name = "always-on", \
> + .always_on = 1, \
> + .domains = POWER_DOMAIN_MASK, \
> + .ops = &i9xx_always_on_power_well_ops, \
> + .id = I915_DISP_PW_ALWAYS_ON, \
> + }, \
> + { \
> + .name = "power well 1", \
> + /* Handled by the DMC firmware */ \
> + .domains = 0, \
> + .ops = &hsw_power_well_ops, \
> + .id = SKL_DISP_PW_1, \
> + { \
> + .hsw.has_fuses = true, \
> + }, \
> + }, \
> + { \
> + .name = "AUX A", \
> + .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = CNL_DISP_PW_AUX_A, \
> + }, \
> + { \
> + .name = "AUX B", \
> + .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = CNL_DISP_PW_AUX_B, \
> + }, \
> + { \
> + .name = "AUX C", \
> + .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = CNL_DISP_PW_AUX_C, \
> + }, \
> + { \
> + .name = "AUX D", \
> + .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = CNL_DISP_PW_AUX_D, \
> + }, \
> + { \
> + .name = "DC off", \
> + .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, \
> + .ops = &gen9_dc_off_power_well_ops, \
> + .id = SKL_DISP_PW_DC_OFF, \
> + }, \
> + { \
> + .name = "power well 2", \
> + .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = SKL_DISP_PW_2, \
> + { \
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), \
> + .hsw.has_vga = true, \
> + .hsw.has_fuses = true, \
> + }, \
> + }, \
> + { \
> + .name = "DDI A IO power well", \
> + .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = CNL_DISP_PW_DDI_A, \
> + }, \
> + { \
> + .name = "DDI B IO power well", \
> + .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = SKL_DISP_PW_DDI_B, \
> + }, \
> + { \
> + .name = "DDI C IO power well", \
> + .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = SKL_DISP_PW_DDI_C, \
> + }, \
> + { \
> + .name = "DDI D IO power well", \
> + .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, \
> + .ops = &hsw_power_well_ops, \
> + .id = SKL_DISP_PW_DDI_D, \
> + }
> +
> static struct i915_power_well cnl_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = 1,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "AUX A",
> - .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_A,
> - },
> - {
> - .name = "AUX B",
> - .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_B,
> - },
> - {
> - .name = "AUX C",
> - .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_C,
> - },
> - {
> - .name = "AUX D",
> - .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_D,
> - },
> - {
> - .name = "DC off",
> - .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_PW_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DDI A IO power well",
> - .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_DDI_A,
> - },
> - {
> - .name = "DDI B IO power well",
> - .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_B,
> - },
> - {
> - .name = "DDI C IO power well",
> - .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_C,
> - },
> - {
> - .name = "DDI D IO power well",
> - .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_D,
> - },
> + basic_cnl_power_wells,
> +};
> +
> +static struct i915_power_well cnl_power_wells_with_port_f[] = {
> + basic_cnl_power_wells,
> {
> .name = "DDI F IO power well",
> .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
> @@ -2543,7 +2550,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> } else if (IS_GEN9_BC(dev_priv)) {
> set_power_wells(power_domains, skl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> - set_power_wells(power_domains, cnl_power_wells);
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + set_power_wells(power_domains,
> + cnl_power_wells_with_port_f);
> + else
> + set_power_wells(power_domains, cnl_power_wells);
I guess it's the AUX power well timing out during driver loading where
we enable all the power wells. I plan to change that so we don't enable
those during init similarly to DDI IO power wells. Until that could we
just remove the port F power wells like the following?:
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2410,6 +2410,8 @@ static struct i915_power_well cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
+/* Power wells for CNL with port F after this */
+#define CNL_FIRST_PORT_F_PW CNL_DISP_PW_AUX_F
{
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
@@ -2531,6 +2533,16 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
set_power_wells(power_domains, cnl_power_wells);
+ if (IS_CNL_WITH_PORT_F(dev_priv)) {
+ int i;
+
+ for (i = 0; i < power_domains->power_well_count; i++)
+ if (power_domains->power_wells[i].id ==
+ CNL_FIRST_PORT_F_PW)
+ break;
+ WARN_ON(i == power_domains->power_well_count);
+ power_domains->power_well_count = i;
+ }
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
> } else if (IS_BROXTON(dev_priv)) {
> set_power_wells(power_domains, bxt_power_wells);
> } else if (IS_GEMINILAKE(dev_priv)) {
> --
> 2.13.6
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port.
2018-01-20 0:05 ` [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
@ 2018-01-22 16:40 ` Ville Syrjälä
2018-01-22 23:05 ` [PATCH] " Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2018-01-22 16:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi
On Fri, Jan 19, 2018 at 04:05:20PM -0800, Rodrigo Vivi wrote:
> Let's try to simplify this mapping to hpd_pin -> bit
> instead using port.
> So for CNL with port F where we have this port using
> hdp_pin and bits of other ports we don't need to duplicated
> the mapping.
>
> But for now this is only a re-org with no functional change
> expected.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 144 ++++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_lspcon.c | 3 +-
> 3 files changed, 72 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ae3b0b030177..4ff6fcf542e9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4487,173 +4487,170 @@ edp_detect(struct intel_dp *intel_dp)
> return status;
> }
>
> -static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool ibx_digital_port_connected(struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 bit;
>
> - switch (port->base.port) {
> - case PORT_B:
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_B:
> bit = SDE_PORTB_HOTPLUG;
> break;
> - case PORT_C:
> + case HPD_PORT_C:
> bit = SDE_PORTC_HOTPLUG;
> break;
> - case PORT_D:
> + case HPD_PORT_D:
> bit = SDE_PORTD_HOTPLUG;
> break;
> default:
> - MISSING_CASE(port->base.port);
> + MISSING_CASE(encoder->hpd_pin);
> return false;
> }
>
> return I915_READ(SDEISR) & bit;
> }
>
> -static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool cpt_digital_port_connected(struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 bit;
>
> - switch (port->base.port) {
> - case PORT_B:
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_B:
> bit = SDE_PORTB_HOTPLUG_CPT;
> break;
> - case PORT_C:
> + case HPD_PORT_C:
> bit = SDE_PORTC_HOTPLUG_CPT;
> break;
> - case PORT_D:
> + case HPD_PORT_D:
> bit = SDE_PORTD_HOTPLUG_CPT;
> break;
> default:
> - MISSING_CASE(port->base.port);
> + MISSING_CASE(encoder->hpd_pin);
> return false;
> }
>
> return I915_READ(SDEISR) & bit;
> }
>
> -static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool spt_digital_port_connected(struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 bit;
>
> - switch (port->base.port) {
> - case PORT_A:
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_A:
> bit = SDE_PORTA_HOTPLUG_SPT;
> break;
> - case PORT_E:
> + case HPD_PORT_E:
> bit = SDE_PORTE_HOTPLUG_SPT;
> break;
> default:
> - return cpt_digital_port_connected(dev_priv, port);
> + return cpt_digital_port_connected(encoder);
> }
>
> return I915_READ(SDEISR) & bit;
> }
>
> -static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool g4x_digital_port_connected(struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 bit;
>
> - switch (port->base.port) {
> - case PORT_B:
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_B:
> bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
> break;
> - case PORT_C:
> + case HPD_PORT_C:
> bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
> break;
> - case PORT_D:
> + case HPD_PORT_D:
> bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
> break;
> default:
> - MISSING_CASE(port->base.port);
> + MISSING_CASE(encoder->hpd_pin);
> return false;
> }
>
> return I915_READ(PORT_HOTPLUG_STAT) & bit;
> }
>
> -static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool gm45_digital_port_connected(struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 bit;
>
> - switch (port->base.port) {
> - case PORT_B:
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_B:
> bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
> break;
> - case PORT_C:
> + case HPD_PORT_C:
> bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
> break;
> - case PORT_D:
> + case HPD_PORT_D:
> bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
> break;
> default:
> - MISSING_CASE(port->base.port);
> + MISSING_CASE(encoder->hpd_pin);
> return false;
> }
>
> return I915_READ(PORT_HOTPLUG_STAT) & bit;
> }
>
> -static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool ilk_digital_port_connected(struct intel_encoder *encoder)
> {
> - if (port->base.port == PORT_A)
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Style nit: missing newline here, and in several other functions.
> + if (encoder->hpd_pin == HPD_PORT_A)
> return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
> else
> - return ibx_digital_port_connected(dev_priv, port);
> + return ibx_digital_port_connected(encoder);
> }
>
> -static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool snb_digital_port_connected(struct intel_encoder *encoder)
> {
> - if (port->base.port == PORT_A)
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + if (encoder->hpd_pin == HPD_PORT_A)
> return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
> else
> - return cpt_digital_port_connected(dev_priv, port);
> + return cpt_digital_port_connected(encoder);
> }
>
> -static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool ivb_digital_port_connected(struct intel_encoder *encoder)
> {
> - if (port->base.port == PORT_A)
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + if (encoder->hpd_pin == HPD_PORT_A)
> return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
> else
> - return cpt_digital_port_connected(dev_priv, port);
> + return cpt_digital_port_connected(encoder);
> }
>
> -static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +static bool bdw_digital_port_connected(struct intel_encoder *encoder)
> {
> - if (port->base.port == PORT_A)
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + if (encoder->hpd_pin == HPD_PORT_A)
> return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
> else
> - return cpt_digital_port_connected(dev_priv, port);
> + return cpt_digital_port_connected(encoder);
> }
>
> -static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *intel_dig_port)
> +static bool bxt_digital_port_connected(struct intel_encoder *encoder)
> {
> - struct intel_encoder *intel_encoder = &intel_dig_port->base;
> - enum port port;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 bit;
>
> - port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
> - switch (port) {
> - case PORT_A:
> + switch (encoder->hpd_pin) {
> + case HPD_PORT_A:
> bit = BXT_DE_PORT_HP_DDIA;
> break;
> - case PORT_B:
> + case HPD_PORT_B:
> bit = BXT_DE_PORT_HP_DDIB;
> break;
> - case PORT_C:
> + case HPD_PORT_C:
> bit = BXT_DE_PORT_HP_DDIC;
> break;
> default:
> - MISSING_CASE(port);
> + MISSING_CASE(encoder->hpd_pin);
> return false;
> }
>
> @@ -4662,33 +4659,33 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
>
> /*
> * intel_digital_port_connected - is the specified port connected?
> - * @dev_priv: i915 private structure
> - * @port: the port to test
> + * @encoder: intel_encoder
> *
> * Return %true if @port is connected, %false otherwise.
^^^^^
Needs to be updated, assuming this kernel doc comment is actually
used. And if it's not used we should just nuke it.
Apart from those this looks good, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> */
> -bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port)
> +bool intel_digital_port_connected(struct intel_encoder *encoder)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> if (HAS_GMCH_DISPLAY(dev_priv)) {
> if (IS_GM45(dev_priv))
> - return gm45_digital_port_connected(dev_priv, port);
> + return gm45_digital_port_connected(encoder);
> else
> - return g4x_digital_port_connected(dev_priv, port);
> + return g4x_digital_port_connected(encoder);
> }
>
> if (IS_GEN5(dev_priv))
> - return ilk_digital_port_connected(dev_priv, port);
> + return ilk_digital_port_connected(encoder);
> else if (IS_GEN6(dev_priv))
> - return snb_digital_port_connected(dev_priv, port);
> + return snb_digital_port_connected(encoder);
> else if (IS_GEN7(dev_priv))
> - return ivb_digital_port_connected(dev_priv, port);
> + return ivb_digital_port_connected(encoder);
> else if (IS_GEN8(dev_priv))
> - return bdw_digital_port_connected(dev_priv, port);
> + return bdw_digital_port_connected(encoder);
> else if (IS_GEN9_LP(dev_priv))
> - return bxt_digital_port_connected(dev_priv, port);
> + return bxt_digital_port_connected(encoder);
> else
> - return spt_digital_port_connected(dev_priv, port);
> + return spt_digital_port_connected(encoder);
> }
>
> static struct edid *
> @@ -4747,8 +4744,7 @@ intel_dp_long_pulse(struct intel_connector *connector)
> /* Can't disconnect eDP, but you can close the lid... */
> if (intel_dp_is_edp(intel_dp))
> status = edp_detect(intel_dp);
> - else if (intel_digital_port_connected(dev_priv,
> - dp_to_dig_port(intel_dp)))
> + else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
> status = intel_dp_detect_dpcd(intel_dp);
> else
> status = connector_status_disconnected;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a73a9f0d790f..9ae820f82235 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1671,8 +1671,7 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
> int intel_dp_link_required(int pixel_clock, int bpp);
> int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> -bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
> - struct intel_digital_port *port);
> +bool intel_digital_port_connected(struct intel_encoder *encoder);
>
> /* intel_dp_aux_backlight.c */
> int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
> diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c
> index dcbc786479f9..8ae8f42f430a 100644
> --- a/drivers/gpu/drm/i915/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/intel_lspcon.c
> @@ -167,11 +167,10 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
> {
> struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> unsigned long start = jiffies;
>
> while (1) {
> - if (intel_digital_port_connected(dev_priv, dig_port)) {
> + if (intel_digital_port_connected(&dig_port->base)) {
> DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
> jiffies_to_msecs(jiffies - start));
> return;
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
2018-01-20 0:05 ` [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
@ 2018-01-22 16:46 ` Ville Syrjälä
2018-01-23 22:32 ` [PATCH] " Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2018-01-22 16:46 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi
On Fri, Jan 19, 2018 at 04:05:23PM -0800, Rodrigo Vivi wrote:
> On CNL SKUs that uses port F, max DP rate is 8.1G for all
> ports when we have the elevated voltage.
>
> v2: Make commit message more generic.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4b963732454d..36826460d8fb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -240,8 +240,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> - if (port == PORT_A || port == PORT_D ||
> - voltage == VOLTAGE_INFO_0_85V)
> + if (voltage == VOLTAGE_INFO_0_85V ||
> + (!IS_CNL_WITH_PORT_F(dev_priv) && (port == PORT_A ||
> + port == PORT_D)))
This is getting a bit hard to parse. Maybe move all these checks to a
small helper that is easier to read?
> size -= 2;
> } else if (IS_GEN9_BC(dev_priv)) {
> source_rates = skl_rates;
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F.
2018-01-20 0:05 ` [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
@ 2018-01-22 16:51 ` Ville Syrjälä
2018-01-22 23:20 ` Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2018-01-22 16:51 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi, Dhinakaran Pandiyan
On Fri, Jan 19, 2018 at 04:05:21PM -0800, Rodrigo Vivi wrote:
> On CNP boards that are using DDI F,
> bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
> the Digital Port F hotplug line when the Digital
> Port F hotplug detect input is enabled.
>
> v2: Reuse all existent structure instead of adding a
> new HPD_PORT_F pointing to pin of port E.
> v3: Use IS_CNL_WITH_PORT_F so we can start upstreaming
> this right now. If that SKU ever get a proper name
> we come back and update it.
> v4: Rebase on top of digital connected port using encoder
> instead of port.
> v5: Moved IS_CNL_WITH_PORT_F definition to the PCI IDs patch.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++--
> drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_hotplug.c | 19 +++++++++++++++----
> 5 files changed, 42 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7206c7c5f81c..0b5f8d887bfd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2957,8 +2957,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> void intel_hpd_init(struct drm_i915_private *dev_priv);
> void intel_hpd_init_work(struct drm_i915_private *dev_priv);
> void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
> -enum port intel_hpd_pin_to_port(enum hpd_pin pin);
> -enum hpd_pin intel_hpd_pin(enum port port);
> +enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
> + enum hpd_pin pin);
> +enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> + enum port port);
> bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
> void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0af970d4b3cf..78af4594eb38 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1568,10 +1568,11 @@ static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
> *
> * Note that the caller is expected to zero out the masks initially.
> */
> -static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
> - u32 hotplug_trigger, u32 dig_hotplug_reg,
> - const u32 hpd[HPD_NUM_PINS],
> - bool long_pulse_detect(enum port port, u32 val))
> +static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> + u32 *pin_mask, u32 *long_mask,
> + u32 hotplug_trigger, u32 dig_hotplug_reg,
> + const u32 hpd[HPD_NUM_PINS],
> + bool long_pulse_detect(enum port port, u32 val))
> {
> enum port port;
> int i;
> @@ -1582,7 +1583,7 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
>
> *pin_mask |= BIT(i);
>
> - port = intel_hpd_pin_to_port(i);
> + port = intel_hpd_pin_to_port(dev_priv, i);
> if (port == PORT_NONE)
> continue;
>
> @@ -1970,8 +1971,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
>
> if (hotplug_trigger) {
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> - hotplug_trigger, hpd_status_g4x,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug_trigger, hotplug_trigger,
> + hpd_status_g4x,
> i9xx_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> @@ -1983,8 +1985,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
>
> if (hotplug_trigger) {
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> - hotplug_trigger, hpd_status_i915,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug_trigger, hotplug_trigger,
> + hpd_status_i915,
> i9xx_port_hotplug_long_detect);
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> }
> @@ -2185,7 +2188,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (!hotplug_trigger)
> return;
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> dig_hotplug_reg, hpd,
> pch_port_hotplug_long_detect);
>
> @@ -2327,8 +2330,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
> I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> - dig_hotplug_reg, hpd_spt,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug_trigger, dig_hotplug_reg, hpd_spt,
> spt_port_hotplug_long_detect);
> }
>
> @@ -2338,8 +2341,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
> I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
> - dig_hotplug_reg, hpd_spt,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> + hotplug2_trigger, dig_hotplug_reg, hpd_spt,
> spt_port_hotplug2_long_detect);
> }
>
> @@ -2359,7 +2362,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
> dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
> I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> dig_hotplug_reg, hpd,
> ilk_port_hotplug_long_detect);
>
> @@ -2536,7 +2539,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
> dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
> I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
>
> - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> dig_hotplug_reg, hpd,
> bxt_port_hotplug_long_detect);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4ff6fcf542e9..4b963732454d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6205,8 +6205,10 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
> {
> struct intel_encoder *encoder = &intel_dig_port->base;
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> + struct intel_encoder *intel_encoder = &intel_dig_port->base;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
>
> - encoder->hpd_pin = intel_hpd_pin(encoder->port);
> + encoder->hpd_pin = intel_hpd_pin_default(dev_priv, encoder->port);
>
> switch (encoder->port) {
> case PORT_A:
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 0d924ba42075..f9a1a32fd272 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2334,7 +2334,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>
> if (WARN_ON(port == PORT_A))
> return;
> - intel_encoder->hpd_pin = intel_hpd_pin(port);
> + intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
>
> if (HAS_DDI(dev_priv))
> intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index 875d5d218d5c..fe28c1ea84a5 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -78,12 +78,14 @@
>
> /**
> * intel_hpd_port - return port hard associated with certain pin.
> + * @dev_priv: private driver data pointer
> * @pin: the hpd pin to get associated port
> *
> * Return port that is associatade with @pin and PORT_NONE if no port is
> * hard associated with that @pin.
> */
> -enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> +enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
> + enum hpd_pin pin)
> {
> switch (pin) {
> case HPD_PORT_A:
> @@ -95,6 +97,8 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> case HPD_PORT_D:
> return PORT_D;
> case HPD_PORT_E:
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + return PORT_F;
> return PORT_E;
> default:
> return PORT_NONE; /* no port for this pin */
I'm thinking we could rewrite this function as
for_each_intel_encoder(...) {
if (encoder->hpd_pin == pin)
return encoder->port;
}
That way we have no hardcoded mapping anywhere but
intel_hpd_pin_default().
But this could be a followup patch.
Everything in this patch looks reasonable to me so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> @@ -102,13 +106,17 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> }
>
> /**
> - * intel_hpd_pin - return pin hard associated with certain port.
> + * intel_hpd_pin_default - return default pin associated with certain port.
> + * @dev_priv: private driver data pointer
> * @port: the hpd port to get associated pin
> *
> + * It is only valid and used by digital port encoder.
> + *
> * Return pin that is associatade with @port and HDP_NONE if no pin is
> * hard associated with that @port.
> */
> -enum hpd_pin intel_hpd_pin(enum port port)
> +enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> + enum port port)
> {
> switch (port) {
> case PORT_A:
> @@ -121,6 +129,9 @@ enum hpd_pin intel_hpd_pin(enum port port)
> return HPD_PORT_D;
> case PORT_E:
> return HPD_PORT_E;
> + case PORT_F:
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + return HPD_PORT_E;
> default:
> MISSING_CASE(port);
> return HPD_NONE;
> @@ -417,7 +428,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (!(BIT(i) & pin_mask))
> continue;
>
> - port = intel_hpd_pin_to_port(i);
> + port = intel_hpd_pin_to_port(dev_priv, i);
> is_dig_port = port != PORT_NONE &&
> dev_priv->hotplug.irq_port[port];
>
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (10 preceding siblings ...)
2018-01-20 8:40 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2018-01-22 16:56 ` Ville Syrjälä
2018-01-22 23:00 ` Rodrigo Vivi
2018-01-23 0:11 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) Patchwork
` (6 subsequent siblings)
18 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2018-01-22 16:56 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni, Dhinakaran Pandiyan
On Fri, Jan 19, 2018 at 04:05:15PM -0800, Rodrigo Vivi wrote:
> The only difference is that this SKUs has the full
> Port A/E split named as Port F.
>
> But since SKUs differences don't matter on the platform
> definition group and ids, let's merge all off them together.
>
> v2: Really include the PCI IDs to the picidlist[];
> v3: Add the PCI Id for another SKU (Anusha).
> v4: Update IDs, really include to pciidlists again.
> v5: Unify all GT2 IDs.
> v6: Unify in a way that we don't break early-quirks.c
> v7: Remove GT reference since it doesn't matter here (Paulo)
> Also move IS_CNL_WITH_PORT_F macro to this patch to
> make it easier for review this part and also to get
> used sooner.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 5 ++---
> include/drm/i915_pciids.h | 18 +++++++-----------
> 3 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..3d3727829ac7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2647,6 +2647,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> (dev_priv)->info.gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> (dev_priv)->info.gt == 3)
> +#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
I wonder if we should generalize this sort of thing into some kind of
device info port_mask. Though our port namespace currently only covers
the various digital port type, so listing all possible ports there
wouldn't currently be possible.
Perhaps not worth the hassle right now.
>
> #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f28c165fc49d..7eb3d5e4350e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -571,7 +571,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
> .ddb_size = 1024, \
> GLK_COLORS
>
> -static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
> +static const struct intel_device_info intel_cannonlake_info __initconst = {
> GEN10_FEATURES,
> .is_alpha_support = 1,
> .platform = INTEL_CANNONLAKE,
> @@ -649,8 +649,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
> INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> - INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
> - INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
> + INTEL_CNL_IDS(&intel_cannonlake_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 5db0458dd832..9e1fe6634424 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -414,24 +414,20 @@
> INTEL_CFL_U_GT2_IDS(info), \
> INTEL_CFL_U_GT3_IDS(info)
>
> -/* CNL U 2+2 */
> -#define INTEL_CNL_U_GT2_IDS(info) \
> +/* CNL */
> +#define INTEL_CNL_IDS(info) \
> INTEL_VGA_DEVICE(0x5A52, info), \
> INTEL_VGA_DEVICE(0x5A5A, info), \
> INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info)
> -
> -/* CNL Y 2+2 */
> -#define INTEL_CNL_Y_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x5A4A, info), \
> INTEL_VGA_DEVICE(0x5A51, info), \
> INTEL_VGA_DEVICE(0x5A59, info), \
> INTEL_VGA_DEVICE(0x5A41, info), \
> INTEL_VGA_DEVICE(0x5A49, info), \
> INTEL_VGA_DEVICE(0x5A71, info), \
> - INTEL_VGA_DEVICE(0x5A79, info)
> -
> -#define INTEL_CNL_IDS(info) \
> - INTEL_CNL_U_GT2_IDS(info), \
> - INTEL_CNL_Y_GT2_IDS(info)
> + INTEL_VGA_DEVICE(0x5A79, info), \
> + INTEL_VGA_DEVICE(0x5A54, info), \
> + INTEL_VGA_DEVICE(0x5A5C, info), \
> + INTEL_VGA_DEVICE(0x5A44, info)
>
> #endif /* _I915_PCIIDS_H */
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
2018-01-20 0:05 ` [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
@ 2018-01-22 21:44 ` Pandiyan, Dhinakaran
2018-01-22 23:08 ` Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-01-22 21:44 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> Since when it got introduced with commit '555e38d27317
> ("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
> was wrong, because Port F bits are far from bits used
> for A to E.
>
> Since Port F is not used so far we don't need to propagate
> Fixes back there.
>
> v2: Reuse _SHIFT definition to avoid complicated duplication (DK).
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ad9ad4a7918..861a7d5a27af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8838,10 +8838,12 @@ enum skl_power_gate {
> * CNL Clocks
> */
> #define DPCLKA_CFGCR0 _MMIO(0x6C200)
> -#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
> -#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
> -#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
> -#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
> +#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
> + (port)+10))
> +#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
> + (port)*2)
nit: I wouldn't bother with the new line, more readable without it. And
there seems to be plenty of places in that file where the 80 char limit
is exceeded.
Either way, patch looks correct.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> +#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> +#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
>
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2018-01-22 16:56 ` [PATCH 01/10] " Ville Syrjälä
@ 2018-01-22 23:00 ` Rodrigo Vivi
0 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 23:00 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni, Dhinakaran Pandiyan
On Mon, Jan 22, 2018 at 04:56:10PM +0000, Ville Syrjälä wrote:
> On Fri, Jan 19, 2018 at 04:05:15PM -0800, Rodrigo Vivi wrote:
> > The only difference is that this SKUs has the full
> > Port A/E split named as Port F.
> >
> > But since SKUs differences don't matter on the platform
> > definition group and ids, let's merge all off them together.
> >
> > v2: Really include the PCI IDs to the picidlist[];
> > v3: Add the PCI Id for another SKU (Anusha).
> > v4: Update IDs, really include to pciidlists again.
> > v5: Unify all GT2 IDs.
> > v6: Unify in a way that we don't break early-quirks.c
> > v7: Remove GT reference since it doesn't matter here (Paulo)
> > Also move IS_CNL_WITH_PORT_F macro to this patch to
> > make it easier for review this part and also to get
> > used sooner.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 5 ++---
> > include/drm/i915_pciids.h | 18 +++++++-----------
> > 3 files changed, 11 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 8333692dac5a..3d3727829ac7 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2647,6 +2647,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> > (dev_priv)->info.gt == 2)
> > #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> > (dev_priv)->info.gt == 3)
> > +#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> > + (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>
> I wonder if we should generalize this sort of thing into some kind of
> device info port_mask. Though our port namespace currently only covers
> the various digital port type, so listing all possible ports there
> wouldn't currently be possible.
well... the right way actually would be having a proper name for this SKU,
but unfortunately we don't :/
>
> Perhaps not worth the hassle right now.
yeap... I don't feel it is worth right now.
>
> >
> > #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index f28c165fc49d..7eb3d5e4350e 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -571,7 +571,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
> > .ddb_size = 1024, \
> > GLK_COLORS
> >
> > -static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
> > +static const struct intel_device_info intel_cannonlake_info __initconst = {
> > GEN10_FEATURES,
> > .is_alpha_support = 1,
> > .platform = INTEL_CANNONLAKE,
> > @@ -649,8 +649,7 @@ static const struct pci_device_id pciidlist[] = {
> > INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
> > INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> > INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> > - INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
> > - INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
> > + INTEL_CNL_IDS(&intel_cannonlake_info),
> > {0, 0, 0}
> > };
> > MODULE_DEVICE_TABLE(pci, pciidlist);
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 5db0458dd832..9e1fe6634424 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -414,24 +414,20 @@
> > INTEL_CFL_U_GT2_IDS(info), \
> > INTEL_CFL_U_GT3_IDS(info)
> >
> > -/* CNL U 2+2 */
> > -#define INTEL_CNL_U_GT2_IDS(info) \
> > +/* CNL */
> > +#define INTEL_CNL_IDS(info) \
> > INTEL_VGA_DEVICE(0x5A52, info), \
> > INTEL_VGA_DEVICE(0x5A5A, info), \
> > INTEL_VGA_DEVICE(0x5A42, info), \
> > - INTEL_VGA_DEVICE(0x5A4A, info)
> > -
> > -/* CNL Y 2+2 */
> > -#define INTEL_CNL_Y_GT2_IDS(info) \
> > + INTEL_VGA_DEVICE(0x5A4A, info), \
> > INTEL_VGA_DEVICE(0x5A51, info), \
> > INTEL_VGA_DEVICE(0x5A59, info), \
> > INTEL_VGA_DEVICE(0x5A41, info), \
> > INTEL_VGA_DEVICE(0x5A49, info), \
> > INTEL_VGA_DEVICE(0x5A71, info), \
> > - INTEL_VGA_DEVICE(0x5A79, info)
> > -
> > -#define INTEL_CNL_IDS(info) \
> > - INTEL_CNL_U_GT2_IDS(info), \
> > - INTEL_CNL_Y_GT2_IDS(info)
> > + INTEL_VGA_DEVICE(0x5A79, info), \
> > + INTEL_VGA_DEVICE(0x5A54, info), \
> > + INTEL_VGA_DEVICE(0x5A5C, info), \
> > + INTEL_VGA_DEVICE(0x5A44, info)
> >
> > #endif /* _I915_PCIIDS_H */
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915: For HPD connected port use hpd_pin instead of port.
2018-01-22 16:40 ` Ville Syrjälä
@ 2018-01-22 23:05 ` Rodrigo Vivi
0 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 23:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
v2: Add missing lines and nuke @port reference from code
documentation. (Ville)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 150 ++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_lspcon.c | 3 +-
3 files changed, 77 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ae3b0b030177..8579d2d09231 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4487,173 +4487,174 @@ edp_detect(struct intel_dp *intel_dp)
return status;
}
-static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ibx_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = SDE_PORTB_HOTPLUG;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = SDE_PORTC_HOTPLUG;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = SDE_PORTD_HOTPLUG;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(SDEISR) & bit;
}
-static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool cpt_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = SDE_PORTB_HOTPLUG_CPT;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = SDE_PORTC_HOTPLUG_CPT;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = SDE_PORTD_HOTPLUG_CPT;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(SDEISR) & bit;
}
-static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool spt_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_A:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
bit = SDE_PORTA_HOTPLUG_SPT;
break;
- case PORT_E:
+ case HPD_PORT_E:
bit = SDE_PORTE_HOTPLUG_SPT;
break;
default:
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
return I915_READ(SDEISR) & bit;
}
-static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool g4x_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool gm45_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- switch (port->base.port) {
- case PORT_B:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
break;
- case PORT_D:
+ case HPD_PORT_D:
bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
break;
default:
- MISSING_CASE(port->base.port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
return I915_READ(PORT_HOTPLUG_STAT) & bit;
}
-static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ilk_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
else
- return ibx_digital_port_connected(dev_priv, port);
+ return ibx_digital_port_connected(encoder);
}
-static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool snb_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool ivb_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
- if (port->base.port == PORT_A)
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (encoder->hpd_pin == HPD_PORT_A)
return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
else
- return cpt_digital_port_connected(dev_priv, port);
+ return cpt_digital_port_connected(encoder);
}
-static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *intel_dig_port)
+static bool bxt_digital_port_connected(struct intel_encoder *encoder)
{
- struct intel_encoder *intel_encoder = &intel_dig_port->base;
- enum port port;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 bit;
- port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
- switch (port) {
- case PORT_A:
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
bit = BXT_DE_PORT_HP_DDIA;
break;
- case PORT_B:
+ case HPD_PORT_B:
bit = BXT_DE_PORT_HP_DDIB;
break;
- case PORT_C:
+ case HPD_PORT_C:
bit = BXT_DE_PORT_HP_DDIC;
break;
default:
- MISSING_CASE(port);
+ MISSING_CASE(encoder->hpd_pin);
return false;
}
@@ -4662,33 +4663,33 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
/*
* intel_digital_port_connected - is the specified port connected?
- * @dev_priv: i915 private structure
- * @port: the port to test
+ * @encoder: intel_encoder
*
- * Return %true if @port is connected, %false otherwise.
+ * Return %true if port is connected, %false otherwise.
*/
-bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port)
+bool intel_digital_port_connected(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
if (HAS_GMCH_DISPLAY(dev_priv)) {
if (IS_GM45(dev_priv))
- return gm45_digital_port_connected(dev_priv, port);
+ return gm45_digital_port_connected(encoder);
else
- return g4x_digital_port_connected(dev_priv, port);
+ return g4x_digital_port_connected(encoder);
}
if (IS_GEN5(dev_priv))
- return ilk_digital_port_connected(dev_priv, port);
+ return ilk_digital_port_connected(encoder);
else if (IS_GEN6(dev_priv))
- return snb_digital_port_connected(dev_priv, port);
+ return snb_digital_port_connected(encoder);
else if (IS_GEN7(dev_priv))
- return ivb_digital_port_connected(dev_priv, port);
+ return ivb_digital_port_connected(encoder);
else if (IS_GEN8(dev_priv))
- return bdw_digital_port_connected(dev_priv, port);
+ return bdw_digital_port_connected(encoder);
else if (IS_GEN9_LP(dev_priv))
- return bxt_digital_port_connected(dev_priv, port);
+ return bxt_digital_port_connected(encoder);
else
- return spt_digital_port_connected(dev_priv, port);
+ return spt_digital_port_connected(encoder);
}
static struct edid *
@@ -4747,8 +4748,7 @@ intel_dp_long_pulse(struct intel_connector *connector)
/* Can't disconnect eDP, but you can close the lid... */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
- else if (intel_digital_port_connected(dev_priv,
- dp_to_dig_port(intel_dp)))
+ else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
status = intel_dp_detect_dpcd(intel_dp);
else
status = connector_status_disconnected;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a73a9f0d790f..9ae820f82235 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1671,8 +1671,7 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
-bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
- struct intel_digital_port *port);
+bool intel_digital_port_connected(struct intel_encoder *encoder);
/* intel_dp_aux_backlight.c */
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c
index dcbc786479f9..8ae8f42f430a 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -167,11 +167,10 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
unsigned long start = jiffies;
while (1) {
- if (intel_digital_port_connected(dev_priv, dig_port)) {
+ if (intel_digital_port_connected(&dig_port->base)) {
DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n",
jiffies_to_msecs(jiffies - start));
return;
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
2018-01-22 21:44 ` Pandiyan, Dhinakaran
@ 2018-01-22 23:08 ` Rodrigo Vivi
0 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 23:08 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, De Marchi, Lucas
On Mon, Jan 22, 2018 at 09:44:47PM +0000, Pandiyan, Dhinakaran wrote:
> On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> > Since when it got introduced with commit '555e38d27317
> > ("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
> > was wrong, because Port F bits are far from bits used
> > for A to E.
> >
> > Since Port F is not used so far we don't need to propagate
> > Fixes back there.
> >
> > v2: Reuse _SHIFT definition to avoid complicated duplication (DK).
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3ad9ad4a7918..861a7d5a27af 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8838,10 +8838,12 @@ enum skl_power_gate {
> > * CNL Clocks
> > */
> > #define DPCLKA_CFGCR0 _MMIO(0x6C200)
> > -#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
> > -#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
> > -#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
> > -#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
> > +#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
> > + (port)+10))
> > +#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
> > + (port)*2)
>
> nit: I wouldn't bother with the new line, more readable without it. And
> there seems to be plenty of places in that file where the 80 char limit
> is exceeded.
well, it depends on the screen size. If not cut the screen size will limit that
and in my current case it gets worse...
>
>
> Either way, patch looks correct.
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Thanks,
Rodrigo.
>
>
> > +#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> > +#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> >
> > /* CNL PLL */
> > #define DPLL0_ENABLE 0x46010
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F.
2018-01-22 16:51 ` Ville Syrjälä
@ 2018-01-22 23:20 ` Rodrigo Vivi
0 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 23:20 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Lucas De Marchi, Dhinakaran Pandiyan
On Mon, Jan 22, 2018 at 04:51:08PM +0000, Ville Syrjälä wrote:
> On Fri, Jan 19, 2018 at 04:05:21PM -0800, Rodrigo Vivi wrote:
> > On CNP boards that are using DDI F,
> > bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
> > the Digital Port F hotplug line when the Digital
> > Port F hotplug detect input is enabled.
> >
> > v2: Reuse all existent structure instead of adding a
> > new HPD_PORT_F pointing to pin of port E.
> > v3: Use IS_CNL_WITH_PORT_F so we can start upstreaming
> > this right now. If that SKU ever get a proper name
> > we come back and update it.
> > v4: Rebase on top of digital connected port using encoder
> > instead of port.
> > v5: Moved IS_CNL_WITH_PORT_F definition to the PCI IDs patch.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 6 ++++--
> > drivers/gpu/drm/i915/i915_irq.c | 35 +++++++++++++++++++----------------
> > drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> > drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> > drivers/gpu/drm/i915/intel_hotplug.c | 19 +++++++++++++++----
> > 5 files changed, 42 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7206c7c5f81c..0b5f8d887bfd 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2957,8 +2957,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > void intel_hpd_init(struct drm_i915_private *dev_priv);
> > void intel_hpd_init_work(struct drm_i915_private *dev_priv);
> > void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
> > -enum port intel_hpd_pin_to_port(enum hpd_pin pin);
> > -enum hpd_pin intel_hpd_pin(enum port port);
> > +enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
> > + enum hpd_pin pin);
> > +enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> > + enum port port);
> > bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
> > void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 0af970d4b3cf..78af4594eb38 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1568,10 +1568,11 @@ static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
> > *
> > * Note that the caller is expected to zero out the masks initially.
> > */
> > -static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
> > - u32 hotplug_trigger, u32 dig_hotplug_reg,
> > - const u32 hpd[HPD_NUM_PINS],
> > - bool long_pulse_detect(enum port port, u32 val))
> > +static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> > + u32 *pin_mask, u32 *long_mask,
> > + u32 hotplug_trigger, u32 dig_hotplug_reg,
> > + const u32 hpd[HPD_NUM_PINS],
> > + bool long_pulse_detect(enum port port, u32 val))
> > {
> > enum port port;
> > int i;
> > @@ -1582,7 +1583,7 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
> >
> > *pin_mask |= BIT(i);
> >
> > - port = intel_hpd_pin_to_port(i);
> > + port = intel_hpd_pin_to_port(dev_priv, i);
> > if (port == PORT_NONE)
> > continue;
> >
> > @@ -1970,8 +1971,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
> >
> > if (hotplug_trigger) {
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> > - hotplug_trigger, hpd_status_g4x,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > + hotplug_trigger, hotplug_trigger,
> > + hpd_status_g4x,
> > i9xx_port_hotplug_long_detect);
> >
> > intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> > @@ -1983,8 +1985,9 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
> >
> > if (hotplug_trigger) {
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> > - hotplug_trigger, hpd_status_i915,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > + hotplug_trigger, hotplug_trigger,
> > + hpd_status_i915,
> > i9xx_port_hotplug_long_detect);
> > intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> > }
> > @@ -2185,7 +2188,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > if (!hotplug_trigger)
> > return;
> >
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> > dig_hotplug_reg, hpd,
> > pch_port_hotplug_long_detect);
> >
> > @@ -2327,8 +2330,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> > dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
> > I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
> >
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> > - dig_hotplug_reg, hpd_spt,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > + hotplug_trigger, dig_hotplug_reg, hpd_spt,
> > spt_port_hotplug_long_detect);
> > }
> >
> > @@ -2338,8 +2341,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> > dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
> > I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
> >
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
> > - dig_hotplug_reg, hpd_spt,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > + hotplug2_trigger, dig_hotplug_reg, hpd_spt,
> > spt_port_hotplug2_long_detect);
> > }
> >
> > @@ -2359,7 +2362,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
> > I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
> >
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> > dig_hotplug_reg, hpd,
> > ilk_port_hotplug_long_detect);
> >
> > @@ -2536,7 +2539,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
> > I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
> >
> > - intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
> > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
> > dig_hotplug_reg, hpd,
> > bxt_port_hotplug_long_detect);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 4ff6fcf542e9..4b963732454d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -6205,8 +6205,10 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
> > {
> > struct intel_encoder *encoder = &intel_dig_port->base;
> > struct intel_dp *intel_dp = &intel_dig_port->dp;
> > + struct intel_encoder *intel_encoder = &intel_dig_port->base;
> > + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> >
> > - encoder->hpd_pin = intel_hpd_pin(encoder->port);
> > + encoder->hpd_pin = intel_hpd_pin_default(dev_priv, encoder->port);
> >
> > switch (encoder->port) {
> > case PORT_A:
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 0d924ba42075..f9a1a32fd272 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -2334,7 +2334,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> >
> > if (WARN_ON(port == PORT_A))
> > return;
> > - intel_encoder->hpd_pin = intel_hpd_pin(port);
> > + intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
> >
> > if (HAS_DDI(dev_priv))
> > intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> > diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> > index 875d5d218d5c..fe28c1ea84a5 100644
> > --- a/drivers/gpu/drm/i915/intel_hotplug.c
> > +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> > @@ -78,12 +78,14 @@
> >
> > /**
> > * intel_hpd_port - return port hard associated with certain pin.
> > + * @dev_priv: private driver data pointer
> > * @pin: the hpd pin to get associated port
> > *
> > * Return port that is associatade with @pin and PORT_NONE if no port is
> > * hard associated with that @pin.
> > */
> > -enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> > +enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
> > + enum hpd_pin pin)
> > {
> > switch (pin) {
> > case HPD_PORT_A:
> > @@ -95,6 +97,8 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> > case HPD_PORT_D:
> > return PORT_D;
> > case HPD_PORT_E:
> > + if (IS_CNL_WITH_PORT_F(dev_priv))
> > + return PORT_F;
> > return PORT_E;
> > default:
> > return PORT_NONE; /* no port for this pin */
>
> I'm thinking we could rewrite this function as
>
> for_each_intel_encoder(...) {
> if (encoder->hpd_pin == pin)
> return encoder->port;
> }
>
> That way we have no hardcoded mapping anywhere but
> intel_hpd_pin_default().
>
> But this could be a followup patch.
I considered that, and even start to write here,
but irq handler would need to start knowing about encoder...
worth?
>
> Everything in this patch looks reasonable to me so
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
thanks
>
> > @@ -102,13 +106,17 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin)
> > }
> >
> > /**
> > - * intel_hpd_pin - return pin hard associated with certain port.
> > + * intel_hpd_pin_default - return default pin associated with certain port.
> > + * @dev_priv: private driver data pointer
> > * @port: the hpd port to get associated pin
> > *
> > + * It is only valid and used by digital port encoder.
> > + *
> > * Return pin that is associatade with @port and HDP_NONE if no pin is
> > * hard associated with that @port.
> > */
> > -enum hpd_pin intel_hpd_pin(enum port port)
> > +enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> > + enum port port)
> > {
> > switch (port) {
> > case PORT_A:
> > @@ -121,6 +129,9 @@ enum hpd_pin intel_hpd_pin(enum port port)
> > return HPD_PORT_D;
> > case PORT_E:
> > return HPD_PORT_E;
> > + case PORT_F:
> > + if (IS_CNL_WITH_PORT_F(dev_priv))
> > + return HPD_PORT_E;
> > default:
> > MISSING_CASE(port);
> > return HPD_NONE;
> > @@ -417,7 +428,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> > if (!(BIT(i) & pin_mask))
> > continue;
> >
> > - port = intel_hpd_pin_to_port(i);
> > + port = intel_hpd_pin_to_port(dev_priv, i);
> > is_dig_port = port != PORT_NONE &&
> > dev_priv->hotplug.irq_port[port];
> >
> > --
> > 2.13.6
>
> --
> Ville Syrjälä
> Intel OTC
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 02/10] drm/i915/cnl: Add AUX-F support
2018-01-20 0:05 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
@ 2018-01-22 23:42 ` Pandiyan, Dhinakaran
2018-01-22 23:59 ` [PATCH] " Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-01-22 23:42 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> On some Cannonlake SKUs we have a dedicated Aux for port F,
> that is only the full split between port A and port E.
>
> There is still no Aux E for Port E, as in previous platforms,
> because port_E still means shared lanes with port A.
>
> v2: Rebase.
> v3: Add couple missed PORT_F cases on intel_dp.
> v4: Rebase and fix commit message.
> v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
> v6: Rebase on top of display headers rework.
> v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_display.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> 6 files changed, 36 insertions(+)
<snip>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 83b3f02d33b7..381c6758f3a6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1312,6 +1312,7 @@ enum i915_power_well_id {
> CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> CNL_DISP_PW_AUX_D,
> + CNL_DISP_PW_AUX_F = 13,
Should be 12, status bit is 24 (= id*2) and request is 25 (= id*2 + 1)
>
> SKL_DISP_PW_1 = 14,
> SKL_DISP_PW_2,
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^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2018-01-22 12:12 ` Imre Deak
@ 2018-01-22 23:48 ` Rodrigo Vivi
2018-01-23 3:03 ` Pandiyan, Dhinakaran
0 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 23:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.
v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting
it instead of duplicating and redefining everything.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 433048ffa5c6..7cee63860a7b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1861,18 +1861,20 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/* Power wells for CNL with port F after this */
+#define CNL_FIRST_PORT_F_PW CNL_DISP_PW_AUX_F
+#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
@@ -2544,6 +2546,17 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
set_power_wells(power_domains, cnl_power_wells);
+
+ if (!IS_CNL_WITH_PORT_F(dev_priv)) {
+ int i;
+
+ for (i = 0; i < power_domains->power_well_count; i++)
+ if (power_domains->power_wells[i].id ==
+ CNL_FIRST_PORT_F_PW)
+ break;
+ WARN_ON(power_domains->power_well_count == i - 1);
+ power_domains->power_well_count = i - 1;
+ }
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-22 23:42 ` Pandiyan, Dhinakaran
@ 2018-01-22 23:59 ` Rodrigo Vivi
2018-01-23 2:43 ` Pandiyan, Dhinakaran
0 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 23:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Rebase and fix commit message.
v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
v6: Rebase on top of display headers rework.
v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
v8: Fix Aux bits for Port F (DK)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
drivers/gpu/drm/i915/intel_display.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
6 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d3727829ac7..7206c7c5f81c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1255,6 +1255,7 @@ enum modeset_restore {
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
+#define DP_AUX_F 0x50
#define DDC_PIN_B 0x05
#define DDC_PIN_C 0x04
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index db3466ec6faa..0af970d4b3cf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ tmp_mask |= CNL_AUX_CHANNEL_F;
+
if (iir & tmp_mask) {
dp_aux_irq_handler(dev_priv);
found = true;
@@ -3617,6 +3620,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+ if (IS_CNL_WITH_PORT_F(dev_priv))
+ de_port_masked |= CNL_AUX_CHANNEL_F;
+
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abd9ee876186..ebdee212767a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1312,6 +1312,7 @@ enum i915_power_well_id {
CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
CNL_DISP_PW_AUX_D,
+ CNL_DISP_PW_AUX_F,
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
@@ -5284,6 +5285,13 @@ enum {
#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
+
#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
@@ -6939,6 +6947,7 @@ enum {
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
#define GEN8_DE_PORT_IIR _MMIO(0x44448)
#define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define CNL_AUX_CHANNEL_F (1 << 28)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define GEN9_AUX_CHANNEL_C (1 << 26)
#define GEN9_AUX_CHANNEL_B (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index e47638931b51..30fa2041a45f 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -172,6 +172,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_AUX_F,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2e887999915..ae3b0b030177 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1323,6 +1323,9 @@ static enum port intel_aux_port(struct drm_i915_private *dev_priv,
case DP_AUX_D:
aux_port = PORT_D;
break;
+ case DP_AUX_F:
+ aux_port = PORT_F;
+ break;
default:
MISSING_CASE(info->alternate_aux_channel);
aux_port = PORT_A;
@@ -1342,6 +1345,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_CTL(port);
default:
MISSING_CASE(port);
@@ -1356,6 +1360,7 @@ static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
case PORT_B:
case PORT_C:
case PORT_D:
+ case PORT_F:
return DP_AUX_CH_DATA(port, index);
default:
MISSING_CASE(port);
@@ -6224,6 +6229,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
/* FIXME: Check VBT for actual wiring of PORT E */
intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
break;
+ case PORT_F:
+ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
+ break;
default:
MISSING_CASE(encoder->port);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5b1aa4b9c72c..27174d49a529 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_C";
case POWER_DOMAIN_AUX_D:
return "AUX_D";
+ case POWER_DOMAIN_AUX_F:
+ return "AUX_F";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1855,6 +1857,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
@@ -2405,6 +2410,12 @@ static struct i915_power_well cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
},
+ {
+ .name = "AUX F",
+ .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = CNL_DISP_PW_AUX_F,
+ },
};
static int
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4)
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (11 preceding siblings ...)
2018-01-22 16:56 ` [PATCH 01/10] " Ville Syrjälä
@ 2018-01-23 0:11 ` Patchwork
2018-01-23 0:32 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5) Patchwork
` (5 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-23 0:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4)
URL : https://patchwork.freedesktop.org/series/36828/
State : success
== Summary ==
Series 36828v4 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
https://patchwork.freedesktop.org/api/1.0/series/36828/revisions/4/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:429s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:372s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:484s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:454s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:280s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:515s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:392s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:410s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:457s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:497s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:504s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:598s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:430s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:507s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:528s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:486s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:483s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:420s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:428s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:527s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:397s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:471s
06c8efda323ac918fad0e26d81e8884574ec8b84 drm-tip: 2018y-01m-22d-17h-43m-26s UTC integration manifest
9f5b51071be1 drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
ca2178f36358 drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
8f60cfa6b58d drm/i915/cnl: Enable DDI-F on Cannonlake.
68f82bbfe11e drm/i915/cnl: Add HPD support for Port F.
ce1021de5ce2 drm/i915: For HPD connected port use hpd_pin instead of port.
7821c0fda1f7 drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
bb9c87f63c8f drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
454b349cec3f drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
5df350c312bf drm/i915/cnl: Add AUX-F support
7566db01d212 drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7748/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5)
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (12 preceding siblings ...)
2018-01-23 0:11 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) Patchwork
@ 2018-01-23 0:32 ` Patchwork
2018-01-23 6:54 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-23 0:32 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5)
URL : https://patchwork.freedesktop.org/series/36828/
State : success
== Summary ==
Series 36828v5 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
https://patchwork.freedesktop.org/api/1.0/series/36828/revisions/5/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:421s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:373s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:488s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:491s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:485s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:454s
fi-elk-e7500 total:224 pass:168 dwarn:9 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:279s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:514s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:392s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:399s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:459s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:415s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:460s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:503s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:578s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:432s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:509s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:528s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:486s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:482s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:419s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:432s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:512s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:397s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:480s
06c8efda323ac918fad0e26d81e8884574ec8b84 drm-tip: 2018y-01m-22d-17h-43m-26s UTC integration manifest
fa8e29c5efca drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
9e809a487e96 drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
8a59bbb7760c drm/i915/cnl: Enable DDI-F on Cannonlake.
ebf6b037613a drm/i915/cnl: Add HPD support for Port F.
61fa99461586 drm/i915: For HPD connected port use hpd_pin instead of port.
6bdd9adcc251 drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
aedb3f70c1bf drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
39a900b42f1a drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
bc396648ec88 drm/i915/cnl: Add AUX-F support
2f3f59fe0a19 drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7749/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-22 23:59 ` [PATCH] " Rodrigo Vivi
@ 2018-01-23 2:43 ` Pandiyan, Dhinakaran
2018-01-23 4:53 ` Pandiyan, Dhinakaran
2018-01-23 21:10 ` [PATCH] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
0 siblings, 2 replies; 47+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-01-23 2:43 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> On some Cannonlake SKUs we have a dedicated Aux for port F,
> that is only the full split between port A and port E.
>
> There is still no Aux E for Port E, as in previous platforms,
> because port_E still means shared lanes with port A.
>
> v2: Rebase.
> v3: Add couple missed PORT_F cases on intel_dp.
> v4: Rebase and fix commit message.
> v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
> v6: Rebase on top of display headers rework.
> v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
> v8: Fix Aux bits for Port F (DK)
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_display.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> 6 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3d3727829ac7..7206c7c5f81c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1255,6 +1255,7 @@ enum modeset_restore {
> #define DP_AUX_B 0x10
> #define DP_AUX_C 0x20
> #define DP_AUX_D 0x30
> +#define DP_AUX_F 0x50
How is this decided? Looks like drivers/gpu/drm/i915/gvt/opregion.c
<<virt_vbt_generation>> needs to be updated too. I guess that's a
separate patch.
>
> #define DDC_PIN_B 0x05
> #define DDC_PIN_C 0x04
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index db3466ec6faa..0af970d4b3cf 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + tmp_mask |= CNL_AUX_CHANNEL_F;
> +
> if (iir & tmp_mask) {
> dp_aux_irq_handler(dev_priv);
> found = true;
> @@ -3617,6 +3620,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
> + if (IS_CNL_WITH_PORT_F(dev_priv))
> + de_port_masked |= CNL_AUX_CHANNEL_F;
> +
> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> GEN8_PIPE_FIFO_UNDERRUN;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index abd9ee876186..ebdee212767a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1312,6 +1312,7 @@ enum i915_power_well_id {
> CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> CNL_DISP_PW_AUX_D,
> + CNL_DISP_PW_AUX_F,
>
> SKL_DISP_PW_1 = 14,
> SKL_DISP_PW_2,
> @@ -5284,6 +5285,13 @@ enum {
> #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
> #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
>
> +#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
> +#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
> +#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
> +#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
> +#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
> +#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
> +
> #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>
> @@ -6939,6 +6947,7 @@ enum {
> #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> #define GEN8_DE_PORT_IIR _MMIO(0x44448)
> #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define CNL_AUX_CHANNEL_F (1 << 28)
> #define GEN9_AUX_CHANNEL_D (1 << 27)
> #define GEN9_AUX_CHANNEL_C (1 << 26)
> #define GEN9_AUX_CHANNEL_B (1 << 25)
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index e47638931b51..30fa2041a45f 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -172,6 +172,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> + POWER_DOMAIN_AUX_F,
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a2e887999915..ae3b0b030177 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1323,6 +1323,9 @@ static enum port intel_aux_port(struct drm_i915_private *dev_priv,
> case DP_AUX_D:
> aux_port = PORT_D;
> break;
> + case DP_AUX_F:
> + aux_port = PORT_F;
> + break;
> default:
> MISSING_CASE(info->alternate_aux_channel);
> aux_port = PORT_A;
> @@ -1342,6 +1345,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> case PORT_B:
> case PORT_C:
> case PORT_D:
> + case PORT_F:
This hunk and the next are not needed. skl_aux_ctl_reg() and
skl_aux_data_reg() already have the required change.
> return DP_AUX_CH_CTL(port);
> default:
> MISSING_CASE(port);
> @@ -1356,6 +1360,7 @@ static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
> case PORT_B:
> case PORT_C:
> case PORT_D:
> + case PORT_F:
> return DP_AUX_CH_DATA(port, index);
> default:
> MISSING_CASE(port);
> @@ -6224,6 +6229,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
> /* FIXME: Check VBT for actual wiring of PORT E */
> intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
> break;
> + case PORT_F:
> + intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
> + break;
> default:
> MISSING_CASE(encoder->port);
> }
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5b1aa4b9c72c..27174d49a529 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> return "AUX_C";
> case POWER_DOMAIN_AUX_D:
> return "AUX_D";
> + case POWER_DOMAIN_AUX_F:
> + return "AUX_F";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> case POWER_DOMAIN_INIT:
> @@ -1855,6 +1857,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> @@ -2405,6 +2410,12 @@ static struct i915_power_well cnl_power_wells[] = {
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_DDI_D,
> },
> + {
> + .name = "AUX F",
> + .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = CNL_DISP_PW_AUX_F,
> + },
This breaks CNL's without port F and gets fixed in a later patch. I am
wondering if we should set ->power_well_count -= 1 here, and set it
properly later.
> };
>
> static int
_______________________________________________
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2018-01-22 23:48 ` [PATCH] " Rodrigo Vivi
@ 2018-01-23 3:03 ` Pandiyan, Dhinakaran
2018-01-23 16:27 ` Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-01-23 3:03 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
On Mon, 2018-01-22 at 15:48 -0800, Rodrigo Vivi wrote:
> SKUs that lacks on the full port F split will just time out
> when touching this power well bits, causing a noisy warn.
>
> v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting
> it instead of duplicating and redefining everything.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++++++++++++------
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 433048ffa5c6..7cee63860a7b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1861,18 +1861,20 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +/* Power wells for CNL with port F after this */
> +#define CNL_FIRST_PORT_F_PW CNL_DISP_PW_AUX_F
> +#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> @@ -2544,6 +2546,17 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> set_power_wells(power_domains, skl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> set_power_wells(power_domains, cnl_power_wells);
> +
> + if (!IS_CNL_WITH_PORT_F(dev_priv)) {
> + int i;
> +
> + for (i = 0; i < power_domains->power_well_count; i++)
> + if (power_domains->power_wells[i].id ==
> + CNL_FIRST_PORT_F_PW)
> + break;
> + WARN_ON(power_domains->power_well_count == i - 1);
> + power_domains->power_well_count = i - 1;
Shouldn't this be
WARN_ON(power_domains->power_well_count == i);
power_domains->power_well_count = i; ?
> + }
> } else if (IS_BROXTON(dev_priv)) {
> set_power_wells(power_domains, bxt_power_wells);
> } else if (IS_GEMINILAKE(dev_priv)) {
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake.
2018-01-20 0:05 ` [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
@ 2018-01-23 3:12 ` Pandiyan, Dhinakaran
2018-01-23 16:29 ` Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-01-23 3:12 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx
On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> Now let's finish the Port-F support by adding the
> proper port F detection, irq and power well support.
>
> v2: Rebase
> v3: Use BIT_ULL
> v4: Cover missed case on ddi init.
> v5: Update commit message.
> v6: Rebase on top of display headers rework.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
> drivers/gpu/drm/i915/intel_display.c | 6 +++++-
> drivers/gpu/drm/i915/intel_display.h | 2 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
> 5 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 861a7d5a27af..32ec64eb2c5a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1304,6 +1304,7 @@ enum i915_power_well_id {
> SKL_DISP_PW_DDI_B,
> SKL_DISP_PW_DDI_C,
> SKL_DISP_PW_DDI_D,
This looks suspicious, why isn't there a DDI_E here for CNL? I see that
bit 10 and 11 correspond to CNL port E in the spec.
> + CNL_DISP_PW_DDI_F = 6,
>
> GLK_DISP_PW_AUX_A = 8,
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-23 2:43 ` Pandiyan, Dhinakaran
@ 2018-01-23 4:53 ` Pandiyan, Dhinakaran
2018-01-23 16:12 ` Lucas De Marchi
2018-01-23 16:30 ` Rodrigo Vivi
2018-01-23 21:10 ` [PATCH] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
1 sibling, 2 replies; 47+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-01-23 4:53 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
On Tue, 2018-01-23 at 02:43 +0000, Pandiyan, Dhinakaran wrote:
>
>
> On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > that is only the full split between port A and port E.
> >
> > There is still no Aux E for Port E, as in previous platforms,
> > because port_E still means shared lanes with port A.
> >
Lucas,
Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
extended to AUX F ?
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^ permalink raw reply [flat|nested] 47+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5)
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (13 preceding siblings ...)
2018-01-23 0:32 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5) Patchwork
@ 2018-01-23 6:54 ` Patchwork
2018-01-23 22:16 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6) Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-23 6:54 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5)
URL : https://patchwork.freedesktop.org/series/36828/
State : failure
== Summary ==
Test kms_flip:
Subgroup flip-vs-panning-vs-hang-interruptible:
dmesg-warn -> PASS (shard-snb) fdo#103821
Subgroup 2x-vblank-vs-hang:
pass -> INCOMPLETE (shard-hsw)
Test gem_softpin:
Subgroup noreloc-s4:
fail -> SKIP (shard-snb) fdo#103375
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass -> FAIL (shard-snb) fdo#101623 +1
Subgroup fbc-tilingchange:
fail -> PASS (shard-apl)
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-legacy:
fail -> PASS (shard-apl) fdo#103355
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-apl) fdo#102254
Subgroup enable-disable:
pass -> FAIL (shard-apl) fdo#103715
Test pm_rpm:
Subgroup gem-execbuf-stress:
pass -> INCOMPLETE (shard-hsw)
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
shard-apl total:2753 pass:1715 dwarn:1 dfail:0 fail:24 skip:1013 time:14021s
shard-hsw total:2652 pass:1669 dwarn:1 dfail:0 fail:11 skip:968 time:14667s
shard-snb total:2753 pass:1318 dwarn:1 dfail:0 fail:10 skip:1424 time:7894s
Blacklisted hosts:
shard-kbl total:2753 pass:1815 dwarn:4 dfail:0 fail:23 skip:911 time:10642s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7749/shards.html
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-23 4:53 ` Pandiyan, Dhinakaran
@ 2018-01-23 16:12 ` Lucas De Marchi
2018-01-23 16:30 ` Rodrigo Vivi
1 sibling, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2018-01-23 16:12 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, Vivi, Rodrigo
On Tue, Jan 23, 2018 at 02:53:55AM -0200, Pandiyan, Dhinakaran wrote:
>
> On Tue, 2018-01-23 at 02:43 +0000, Pandiyan, Dhinakaran wrote:
> >
> >
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the full split between port A and port E.
> > >
> > > There is still no Aux E for Port E, as in previous platforms,
> > > because port_E still means shared lanes with port A.
> > >
>
>
> Lucas,
>
>
> Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
> extended to AUX F ?
No, on CNL it only applies to AUX B-D according to w/a
documentation (and since it doesn't apply to AUX A, I don't think it's
something missing there).
Lucas De Marchi
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2018-01-23 3:03 ` Pandiyan, Dhinakaran
@ 2018-01-23 16:27 ` Rodrigo Vivi
2018-01-23 23:11 ` Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 16:27 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, De Marchi, Lucas
On Tue, Jan 23, 2018 at 03:03:28AM +0000, Pandiyan, Dhinakaran wrote:
>
>
>
> On Mon, 2018-01-22 at 15:48 -0800, Rodrigo Vivi wrote:
> > SKUs that lacks on the full port F split will just time out
> > when touching this power well bits, causing a noisy warn.
> >
> > v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting
> > it instead of duplicating and redefining everything.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++++++++++++------
> > 1 file changed, 19 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 433048ffa5c6..7cee63860a7b 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1861,18 +1861,20 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > -#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > -#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > +/* Power wells for CNL with port F after this */
> > +#define CNL_FIRST_PORT_F_PW CNL_DISP_PW_AUX_F
> > +#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> >
> > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > .sync_hw = i9xx_power_well_sync_hw_noop,
> > @@ -2544,6 +2546,17 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> > set_power_wells(power_domains, skl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > set_power_wells(power_domains, cnl_power_wells);
> > +
> > + if (!IS_CNL_WITH_PORT_F(dev_priv)) {
> > + int i;
> > +
> > + for (i = 0; i < power_domains->power_well_count; i++)
> > + if (power_domains->power_wells[i].id ==
> > + CNL_FIRST_PORT_F_PW)
> > + break;
> > + WARN_ON(power_domains->power_well_count == i - 1);
> > + power_domains->power_well_count = i - 1;
> Shouldn't this be
> WARN_ON(power_domains->power_well_count == i);
oh yeap... c&p from below without thinking. :/
> power_domains->power_well_count = i; ?
this is also what Imre suggested, but I don't think so.
The first-of-non-port-f - 1 is the last of non-port-f.
>
>
> > + }
> > } else if (IS_BROXTON(dev_priv)) {
> > set_power_wells(power_domains, bxt_power_wells);
> > } else if (IS_GEMINILAKE(dev_priv)) {
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake.
2018-01-23 3:12 ` Pandiyan, Dhinakaran
@ 2018-01-23 16:29 ` Rodrigo Vivi
0 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 16:29 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 03:12:52AM +0000, Pandiyan, Dhinakaran wrote:
>
>
>
> On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> > Now let's finish the Port-F support by adding the
> > proper port F detection, irq and power well support.
> >
> > v2: Rebase
> > v3: Use BIT_ULL
> > v4: Cover missed case on ddi init.
> > v5: Update commit message.
> > v6: Rebase on top of display headers rework.
> >
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
> > drivers/gpu/drm/i915/intel_display.c | 6 +++++-
> > drivers/gpu/drm/i915/intel_display.h | 2 ++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
> > 5 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 861a7d5a27af..32ec64eb2c5a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1304,6 +1304,7 @@ enum i915_power_well_id {
> > SKL_DISP_PW_DDI_B,
> > SKL_DISP_PW_DDI_C,
> > SKL_DISP_PW_DDI_D,
>
> This looks suspicious, why isn't there a DDI_E here for CNL? I see that
> bit 10 and 11 correspond to CNL port E in the spec.
because spec likes being contradictory ;)
There is no port E on CNL.
SKUs without port F has only ports A to D.
SKU with full port split has ports A to D and F.
>
> > + CNL_DISP_PW_DDI_F = 6,
> >
> > GLK_DISP_PW_AUX_A = 8,
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-23 4:53 ` Pandiyan, Dhinakaran
2018-01-23 16:12 ` Lucas De Marchi
@ 2018-01-23 16:30 ` Rodrigo Vivi
2018-01-23 18:35 ` Runyan, Arthur J
1 sibling, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 16:30 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, Runyan, Arthur J, De Marchi, Lucas
On Tue, Jan 23, 2018 at 04:53:55AM +0000, Pandiyan, Dhinakaran wrote:
>
> On Tue, 2018-01-23 at 02:43 +0000, Pandiyan, Dhinakaran wrote:
> >
> >
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the full split between port A and port E.
> > >
> > > There is still no Aux E for Port E, as in previous platforms,
> > > because port_E still means shared lanes with port A.
> > >
>
>
> Lucas,
>
>
> Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
> extended to AUX F ?
>
This is a very good question. Art?
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-23 16:30 ` Rodrigo Vivi
@ 2018-01-23 18:35 ` Runyan, Arthur J
2018-01-23 21:57 ` [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F Rodrigo Vivi
0 siblings, 1 reply; 47+ messages in thread
From: Runyan, Arthur J @ 2018-01-23 18:35 UTC (permalink / raw)
To: Vivi, Rodrigo, Pandiyan, Dhinakaran; +Cc: intel-gfx, De Marchi, Lucas
Good question. We forgot that one. It's 0x162A90.
-----Original Message-----
From: Vivi, Rodrigo
Sent: Tuesday, 23 January, 2018 8:30 AM
To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas <lucas.demarchi@intel.com>; Runyan, Arthur J <arthur.j.runyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support
On Tue, Jan 23, 2018 at 04:53:55AM +0000, Pandiyan, Dhinakaran wrote:
>
> On Tue, 2018-01-23 at 02:43 +0000, Pandiyan, Dhinakaran wrote:
> >
> >
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the full split between port A and port E.
> > >
> > > There is still no Aux E for Port E, as in previous platforms,
> > > because port_E still means shared lanes with port A.
> > >
>
>
> Lucas,
>
>
> Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
> extended to AUX F ?
>
This is a very good question. Art?
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Add AUX-F support
2018-01-23 2:43 ` Pandiyan, Dhinakaran
2018-01-23 4:53 ` Pandiyan, Dhinakaran
@ 2018-01-23 21:10 ` Rodrigo Vivi
1 sibling, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 21:10 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx, De Marchi, Lucas
On Tue, Jan 23, 2018 at 02:43:22AM +0000, Pandiyan, Dhinakaran wrote:
>
>
>
> On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > that is only the full split between port A and port E.
> >
> > There is still no Aux E for Port E, as in previous platforms,
> > because port_E still means shared lanes with port A.
> >
> > v2: Rebase.
> > v3: Add couple missed PORT_F cases on intel_dp.
> > v4: Rebase and fix commit message.
> > v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
> > v6: Rebase on top of display headers rework.
> > v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
> > v8: Fix Aux bits for Port F (DK)
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> > drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> > drivers/gpu/drm/i915/intel_display.h | 1 +
> > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> > 6 files changed, 36 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 3d3727829ac7..7206c7c5f81c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1255,6 +1255,7 @@ enum modeset_restore {
> > #define DP_AUX_B 0x10
> > #define DP_AUX_C 0x20
> > #define DP_AUX_D 0x30
> > +#define DP_AUX_F 0x50
>
> How is this decided? Looks like drivers/gpu/drm/i915/gvt/opregion.c
> <<virt_vbt_generation>> needs to be updated too. I guess that's a
> separate patch.
Thanks! Another thing that was totally wrong here...
It is defined by VBT.
"Block 2 (General Bytes Definition)"
Aux Channel: "0x60 = DisplayPort Aux F"
>
> >
> > #define DDC_PIN_B 0x05
> > #define DDC_PIN_C 0x04
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index db3466ec6faa..0af970d4b3cf 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> > GEN9_AUX_CHANNEL_C |
> > GEN9_AUX_CHANNEL_D;
> >
> > + if (IS_CNL_WITH_PORT_F(dev_priv))
> > + tmp_mask |= CNL_AUX_CHANNEL_F;
> > +
> > if (iir & tmp_mask) {
> > dp_aux_irq_handler(dev_priv);
> > found = true;
> > @@ -3617,6 +3620,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> > de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > }
> >
> > + if (IS_CNL_WITH_PORT_F(dev_priv))
> > + de_port_masked |= CNL_AUX_CHANNEL_F;
> > +
> > de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> > GEN8_PIPE_FIFO_UNDERRUN;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index abd9ee876186..ebdee212767a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1312,6 +1312,7 @@ enum i915_power_well_id {
> > CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> > CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> > CNL_DISP_PW_AUX_D,
> > + CNL_DISP_PW_AUX_F,
> >
> > SKL_DISP_PW_1 = 14,
> > SKL_DISP_PW_2,
> > @@ -5284,6 +5285,13 @@ enum {
> > #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
> > #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
> >
> > +#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
> > +#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
> > +#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
> > +#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
> > +#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
> > +#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
> > +
> > #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> > #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >
> > @@ -6939,6 +6947,7 @@ enum {
> > #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> > #define GEN8_DE_PORT_IIR _MMIO(0x44448)
> > #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> > +#define CNL_AUX_CHANNEL_F (1 << 28)
> > #define GEN9_AUX_CHANNEL_D (1 << 27)
> > #define GEN9_AUX_CHANNEL_C (1 << 26)
> > #define GEN9_AUX_CHANNEL_B (1 << 25)
> > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> > index e47638931b51..30fa2041a45f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -172,6 +172,7 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_AUX_B,
> > POWER_DOMAIN_AUX_C,
> > POWER_DOMAIN_AUX_D,
> > + POWER_DOMAIN_AUX_F,
> > POWER_DOMAIN_GMBUS,
> > POWER_DOMAIN_MODESET,
> > POWER_DOMAIN_GT_IRQ,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index a2e887999915..ae3b0b030177 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1323,6 +1323,9 @@ static enum port intel_aux_port(struct drm_i915_private *dev_priv,
> > case DP_AUX_D:
> > aux_port = PORT_D;
> > break;
> > + case DP_AUX_F:
> > + aux_port = PORT_F;
> > + break;
> > default:
> > MISSING_CASE(info->alternate_aux_channel);
> > aux_port = PORT_A;
> > @@ -1342,6 +1345,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
> > case PORT_B:
> > case PORT_C:
> > case PORT_D:
> > + case PORT_F:
>
> This hunk and the next are not needed. skl_aux_ctl_reg() and
> skl_aux_data_reg() already have the required change.
>
> > return DP_AUX_CH_CTL(port);
> > default:
> > MISSING_CASE(port);
> > @@ -1356,6 +1360,7 @@ static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
> > case PORT_B:
> > case PORT_C:
> > case PORT_D:
> > + case PORT_F:
>
>
> > return DP_AUX_CH_DATA(port, index);
> > default:
> > MISSING_CASE(port);
> > @@ -6224,6 +6229,9 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
> > /* FIXME: Check VBT for actual wiring of PORT E */
> > intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
> > break;
> > + case PORT_F:
> > + intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
> > + break;
> > default:
> > MISSING_CASE(encoder->port);
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 5b1aa4b9c72c..27174d49a529 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> > return "AUX_C";
> > case POWER_DOMAIN_AUX_D:
> > return "AUX_D";
> > + case POWER_DOMAIN_AUX_F:
> > + return "AUX_F";
> > case POWER_DOMAIN_GMBUS:
> > return "GMBUS";
> > case POWER_DOMAIN_INIT:
> > @@ -1855,6 +1857,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > @@ -2405,6 +2410,12 @@ static struct i915_power_well cnl_power_wells[] = {
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_DDI_D,
> > },
> > + {
> > + .name = "AUX F",
> > + .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = CNL_DISP_PW_AUX_F,
> > + },
>
> This breaks CNL's without port F and gets fixed in a later patch. I am
> wondering if we should set ->power_well_count -= 1 here, and set it
> properly later.
Well... it is not harmful... just a warning.... But now with
IS_CNL_WITH_PORT_F defined along with PCI IDs and having that
simple power well solution Imre proposed we can sort the patches
in a way that those comes first.
>
>
>
> > };
> >
> > static int
_______________________________________________
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^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F.
2018-01-23 18:35 ` Runyan, Arthur J
@ 2018-01-23 21:57 ` Rodrigo Vivi
2018-01-23 23:21 ` Lucas De Marchi
0 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 21:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
We also need to extend this WA to Aux F.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 671303a0310f..2916124d2950 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8435,10 +8435,12 @@ enum skl_power_gate {
#define _CNL_AUX_ANAOVRD1_B 0x162250
#define _CNL_AUX_ANAOVRD1_C 0x162210
#define _CNL_AUX_ANAOVRD1_D 0x1622D0
+#define _CNL_AUX_ANAOVRD1_F 0x162A90
#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
_CNL_AUX_ANAOVRD1_B, \
_CNL_AUX_ANAOVRD1_C, \
- _CNL_AUX_ANAOVRD1_D))
+ _CNL_AUX_ANAOVRD1_D, \
+ _CNL_AUX_ANAOVRD1_F))
#define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27174d49a529..73700a41723e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -395,7 +395,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
/* Display WA #1178: cnl */
if (IS_CANNONLAKE(dev_priv) &&
(id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
- id == CNL_DISP_PW_AUX_D)) {
+ id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) {
val = I915_READ(CNL_AUX_ANAOVRD1(id));
val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
--
2.13.6
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6)
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (14 preceding siblings ...)
2018-01-23 6:54 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-01-23 22:16 ` Patchwork
2018-01-23 22:36 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7) Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-23 22:16 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6)
URL : https://patchwork.freedesktop.org/series/36828/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Extend Wa 1178 to Aux F.
Applying: drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Applying: drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
Applying: drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
Applying: drm/i915: For HPD connected port use hpd_pin instead of port.
Applying: drm/i915/cnl: Add HPD support for Port F.
Applying: drm/i915/cnl: Enable DDI-F on Cannonlake.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_reg.h
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_display.h
M drivers/gpu/drm/i915/intel_runtime_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.c
Auto-merging drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0008 drm/i915/cnl: Enable DDI-F on Cannonlake.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
2018-01-22 16:46 ` Ville Syrjälä
@ 2018-01-23 22:32 ` Rodrigo Vivi
2018-01-23 22:45 ` Manasi Navare
0 siblings, 1 reply; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage.
v2: Make commit message more generic.
v3: Move conditions to a helper to get easier to read. (Ville).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2b26ffe100b1..31a968f20761 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -220,15 +220,34 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
return max_dotclk;
}
+static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum port port = dig_port->base.port;
+
+ u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+ /* Low voltage SKUs are limited to max of 5.4G */
+ if (voltage == VOLTAGE_INFO_0_85V)
+ return size - 2;
+
+ /* For this SKU 8.1G is supported in all ports */
+ if(IS_CNL_WITH_PORT_F(dev_priv))
+ return size;
+
+ /* For other SKUs, max rate on ports A and B is 5.4G */
+ if (port == PORT_A || port == PORT_D)
+ return size - 2;
+}
+
static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum port port = dig_port->base.port;
const int *source_rates;
int size;
- u32 voltage;
/* This should only be done once */
WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -238,11 +257,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(bxt_rates);
} else if (IS_CANNONLAKE(dev_priv)) {
source_rates = cnl_rates;
- size = ARRAY_SIZE(cnl_rates);
- voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
- if (port == PORT_A || port == PORT_D ||
- voltage == VOLTAGE_INFO_0_85V)
- size -= 2;
+ size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7)
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (15 preceding siblings ...)
2018-01-23 22:16 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6) Patchwork
@ 2018-01-23 22:36 ` Patchwork
2018-01-23 23:15 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8) Patchwork
2018-01-25 17:40 ` [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Paulo Zanoni
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-23 22:36 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7)
URL : https://patchwork.freedesktop.org/series/36828/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Extend Wa 1178 to Aux F.
Applying: drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Applying: drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
Applying: drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
Applying: drm/i915: For HPD connected port use hpd_pin instead of port.
Applying: drm/i915/cnl: Add HPD support for Port F.
Applying: drm/i915/cnl: Enable DDI-F on Cannonlake.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_reg.h
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_display.h
M drivers/gpu/drm/i915/intel_runtime_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.c
Auto-merging drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0008 drm/i915/cnl: Enable DDI-F on Cannonlake.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
2018-01-23 22:32 ` [PATCH] " Rodrigo Vivi
@ 2018-01-23 22:45 ` Manasi Navare
0 siblings, 0 replies; 47+ messages in thread
From: Manasi Navare @ 2018-01-23 22:45 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi
On Tue, Jan 23, 2018 at 02:32:57PM -0800, Rodrigo Vivi wrote:
> On CNL SKUs that uses port F, max DP rate is 8.1G for all
> ports when we have the elevated voltage.
>
Just a nit here on the commit message. Would it make more sense
to mention the elevated voltage numerical value instead of just
elevated voltage?
Other than that the rate selection logic is correct.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> v2: Make commit message more generic.
> v3: Move conditions to a helper to get easier to read. (Ville).
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 29 ++++++++++++++++++++++-------
> 1 file changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2b26ffe100b1..31a968f20761 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -220,15 +220,34 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
> return max_dotclk;
> }
>
> +static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + enum port port = dig_port->base.port;
> +
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + /* Low voltage SKUs are limited to max of 5.4G */
> + if (voltage == VOLTAGE_INFO_0_85V)
> + return size - 2;
> +
> + /* For this SKU 8.1G is supported in all ports */
> + if(IS_CNL_WITH_PORT_F(dev_priv))
> + return size;
> +
> + /* For other SKUs, max rate on ports A and B is 5.4G */
> + if (port == PORT_A || port == PORT_D)
> + return size - 2;
> +}
> +
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum port port = dig_port->base.port;
> const int *source_rates;
> int size;
> - u32 voltage;
>
> /* This should only be done once */
> WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -238,11 +257,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> size = ARRAY_SIZE(bxt_rates);
> } else if (IS_CANNONLAKE(dev_priv)) {
> source_rates = cnl_rates;
> - size = ARRAY_SIZE(cnl_rates);
> - voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> - if (port == PORT_A || port == PORT_D ||
> - voltage == VOLTAGE_INFO_0_85V)
> - size -= 2;
> + size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
> } else if (IS_GEN9_BC(dev_priv)) {
> source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> --
> 2.13.6
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.
2018-01-23 16:27 ` Rodrigo Vivi
@ 2018-01-23 23:11 ` Rodrigo Vivi
0 siblings, 0 replies; 47+ messages in thread
From: Rodrigo Vivi @ 2018-01-23 23:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan, Rodrigo Vivi
SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.
v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting
it instead of duplicating and redefining everything.
v3: Simplify even more the logic, using one that don't mix the
array size with the pw bits. Also add a comment.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4b215acea439..30e50ea16960 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2544,6 +2544,16 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
set_power_wells(power_domains, cnl_power_wells);
+
+ /*
+ * DDI and Aux IO are getting enabled for all ports
+ * regardless the presence or use. So, in order to avoid
+ * timeouts, lets remove them from the list
+ * for the SKUs without port F.
+ */
+ if (!IS_CNL_WITH_PORT_F(dev_priv))
+ power_domains->power_well_count -= 2;
+
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
--
2.13.6
_______________________________________________
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8)
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (16 preceding siblings ...)
2018-01-23 22:36 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7) Patchwork
@ 2018-01-23 23:15 ` Patchwork
2018-01-25 17:40 ` [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Paulo Zanoni
18 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2018-01-23 23:15 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8)
URL : https://patchwork.freedesktop.org/series/36828/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Extend Wa 1178 to Aux F.
Applying: drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Applying: drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
Applying: drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
Applying: drm/i915: For HPD connected port use hpd_pin instead of port.
Applying: drm/i915/cnl: Add HPD support for Port F.
Applying: drm/i915/cnl: Enable DDI-F on Cannonlake.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_reg.h
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_display.h
M drivers/gpu/drm/i915/intel_runtime_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.c
Auto-merging drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0008 drm/i915/cnl: Enable DDI-F on Cannonlake.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F.
2018-01-23 21:57 ` [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F Rodrigo Vivi
@ 2018-01-23 23:21 ` Lucas De Marchi
0 siblings, 0 replies; 47+ messages in thread
From: Lucas De Marchi @ 2018-01-23 23:21 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi, Dhinakaran Pandiyan
On Tue, Jan 23, 2018 at 01:57:13PM -0800, Rodrigo Vivi wrote:
> We also need to extend this WA to Aux F.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 671303a0310f..2916124d2950 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8435,10 +8435,12 @@ enum skl_power_gate {
> #define _CNL_AUX_ANAOVRD1_B 0x162250
> #define _CNL_AUX_ANAOVRD1_C 0x162210
> #define _CNL_AUX_ANAOVRD1_D 0x1622D0
> +#define _CNL_AUX_ANAOVRD1_F 0x162A90
> #define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
> _CNL_AUX_ANAOVRD1_B, \
> _CNL_AUX_ANAOVRD1_C, \
> - _CNL_AUX_ANAOVRD1_D))
> + _CNL_AUX_ANAOVRD1_D, \
> + _CNL_AUX_ANAOVRD1_F))
> #define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
> #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 27174d49a529..73700a41723e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -395,7 +395,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> /* Display WA #1178: cnl */
> if (IS_CANNONLAKE(dev_priv) &&
> (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
> - id == CNL_DISP_PW_AUX_D)) {
> + id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) {
> val = I915_READ(CNL_AUX_ANAOVRD1(id));
> val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
` (17 preceding siblings ...)
2018-01-23 23:15 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8) Patchwork
@ 2018-01-25 17:40 ` Paulo Zanoni
18 siblings, 0 replies; 47+ messages in thread
From: Paulo Zanoni @ 2018-01-25 17:40 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan
Em Sex, 2018-01-19 às 16:05 -0800, Rodrigo Vivi escreveu:
> The only difference is that this SKUs has the full
> Port A/E split named as Port F.
>
> But since SKUs differences don't matter on the platform
> definition group and ids, let's merge all off them together.
>
> v2: Really include the PCI IDs to the picidlist[];
> v3: Add the PCI Id for another SKU (Anusha).
> v4: Update IDs, really include to pciidlists again.
> v5: Unify all GT2 IDs.
> v6: Unify in a way that we don't break early-quirks.c
> v7: Remove GT reference since it doesn't matter here (Paulo)
> Also move IS_CNL_WITH_PORT_F macro to this patch to
> make it easier for review this part and also to get
> used sooner.
>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(although I still would have preferred the split)
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 5 ++---
> include/drm/i915_pciids.h | 18 +++++++-----------
> 3 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..3d3727829ac7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2647,6 +2647,8 @@ intel_info(const struct drm_i915_private
> *dev_priv)
> (dev_priv)->info.gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> (dev_priv)->info.gt == 3)
> +#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> + (INTEL_DEVID(dev_priv) &
> 0x0004) == 0x0004)
>
> #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)-
> >is_alpha_support)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index f28c165fc49d..7eb3d5e4350e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -571,7 +571,7 @@ static const struct intel_device_info
> intel_coffeelake_gt3_info __initconst = {
> .ddb_size = 1024, \
> GLK_COLORS
>
> -static const struct intel_device_info intel_cannonlake_gt2_info
> __initconst = {
> +static const struct intel_device_info intel_cannonlake_info
> __initconst = {
> GEN10_FEATURES,
> .is_alpha_support = 1,
> .platform = INTEL_CANNONLAKE,
> @@ -649,8 +649,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
> INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> - INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
> - INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
> + INTEL_CNL_IDS(&intel_cannonlake_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 5db0458dd832..9e1fe6634424 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -414,24 +414,20 @@
> INTEL_CFL_U_GT2_IDS(info), \
> INTEL_CFL_U_GT3_IDS(info)
>
> -/* CNL U 2+2 */
> -#define INTEL_CNL_U_GT2_IDS(info) \
> +/* CNL */
> +#define INTEL_CNL_IDS(info) \
> INTEL_VGA_DEVICE(0x5A52, info), \
> INTEL_VGA_DEVICE(0x5A5A, info), \
> INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info)
> -
> -/* CNL Y 2+2 */
> -#define INTEL_CNL_Y_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x5A4A, info), \
> INTEL_VGA_DEVICE(0x5A51, info), \
> INTEL_VGA_DEVICE(0x5A59, info), \
> INTEL_VGA_DEVICE(0x5A41, info), \
> INTEL_VGA_DEVICE(0x5A49, info), \
> INTEL_VGA_DEVICE(0x5A71, info), \
> - INTEL_VGA_DEVICE(0x5A79, info)
> -
> -#define INTEL_CNL_IDS(info) \
> - INTEL_CNL_U_GT2_IDS(info), \
> - INTEL_CNL_Y_GT2_IDS(info)
> + INTEL_VGA_DEVICE(0x5A79, info), \
> + INTEL_VGA_DEVICE(0x5A54, info), \
> + INTEL_VGA_DEVICE(0x5A5C, info), \
> + INTEL_VGA_DEVICE(0x5A44, info)
>
> #endif /* _I915_PCIIDS_H */
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^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2018-01-25 17:40 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-20 0:05 [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 02/10] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2018-01-22 23:42 ` Pandiyan, Dhinakaran
2018-01-22 23:59 ` [PATCH] " Rodrigo Vivi
2018-01-23 2:43 ` Pandiyan, Dhinakaran
2018-01-23 4:53 ` Pandiyan, Dhinakaran
2018-01-23 16:12 ` Lucas De Marchi
2018-01-23 16:30 ` Rodrigo Vivi
2018-01-23 18:35 ` Runyan, Arthur J
2018-01-23 21:57 ` [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F Rodrigo Vivi
2018-01-23 23:21 ` Lucas De Marchi
2018-01-23 21:10 ` [PATCH] drm/i915/cnl: Add AUX-F support Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 03/10] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 04/10] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F Rodrigo Vivi
2018-01-22 21:44 ` Pandiyan, Dhinakaran
2018-01-22 23:08 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 05/10] drm/i915/cnl: Add right GMBUS pin number for HDMI on " Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 06/10] drm/i915: For HPD connected port use hpd_pin instead of port Rodrigo Vivi
2018-01-22 16:40 ` Ville Syrjälä
2018-01-22 23:05 ` [PATCH] " Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 07/10] drm/i915/cnl: Add HPD support for Port F Rodrigo Vivi
2018-01-22 16:51 ` Ville Syrjälä
2018-01-22 23:20 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake Rodrigo Vivi
2018-01-23 3:12 ` Pandiyan, Dhinakaran
2018-01-23 16:29 ` Rodrigo Vivi
2018-01-20 0:05 ` [PATCH 09/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F Rodrigo Vivi
2018-01-22 16:46 ` Ville Syrjälä
2018-01-23 22:32 ` [PATCH] " Rodrigo Vivi
2018-01-23 22:45 ` Manasi Navare
2018-01-20 0:05 ` [PATCH 10/10] drm/i915/cnl: Don't try to manage Port F power wells on all CNL Rodrigo Vivi
2018-01-22 12:12 ` Imre Deak
2018-01-22 23:48 ` [PATCH] " Rodrigo Vivi
2018-01-23 3:03 ` Pandiyan, Dhinakaran
2018-01-23 16:27 ` Rodrigo Vivi
2018-01-23 23:11 ` Rodrigo Vivi
2018-01-20 0:30 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Patchwork
2018-01-20 8:40 ` ✗ Fi.CI.IGT: warning " Patchwork
2018-01-22 16:56 ` [PATCH 01/10] " Ville Syrjälä
2018-01-22 23:00 ` Rodrigo Vivi
2018-01-23 0:11 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) Patchwork
2018-01-23 0:32 ` ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev5) Patchwork
2018-01-23 6:54 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-01-23 22:16 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6) Patchwork
2018-01-23 22:36 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7) Patchwork
2018-01-23 23:15 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8) Patchwork
2018-01-25 17:40 ` [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU Paulo Zanoni
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