* [PATCH] drm/i915: Implement display w/a #1143
@ 2018-01-19 18:45 Ville Syrjala
2018-01-19 19:05 ` ✓ Fi.CI.BAT: success for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Ville Syrjala @ 2018-01-19 18:45 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently SKL/KBL need some manual help to get the
programmed HDMI vswing to stick. Implement the relevant
workaround (display w/a #1143).
Note that the relevant chicken bits live in a transcoder register
even though the bits affect a specific DDI port rather than a
specific transcoder. Hence we must pick the correct transcoder
register instance based on the port rather than based on the
cpu_transcoder.
Also note that for completeness I included support for DDI A/E
in the code even though we never have HDMI on those ports.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10e1269ad6af..2e6d0dc01dc7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7012,8 +7012,12 @@ enum {
#define CHICKEN_TRANS_A 0x420c0
#define CHICKEN_TRANS_B 0x420c4
#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
-#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
-#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
+#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
+#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
+#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
+#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
+#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
+#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6260a882fbe4..7b1ab003279f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
crtc_state->hdmi_high_tmds_clock_ratio,
crtc_state->hdmi_scrambling);
+ /* Display WA #1143: skl,kbl */
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
+ /*
+ * For some reason these chicken bits have been
+ * stuffed into a transcoder register, event though
+ * the bits affect a specific DDI port rather than
+ * a specific transcoder.
+ */
+ static const enum transcoder port_to_transcoder[] = {
+ [PORT_A] = TRANSCODER_EDP,
+ [PORT_B] = TRANSCODER_A,
+ [PORT_C] = TRANSCODER_B,
+ [PORT_D] = TRANSCODER_C,
+ [PORT_E] = TRANSCODER_A,
+ };
+ enum transcoder transcoder = port_to_transcoder[port];
+ u32 val;
+
+ val = I915_READ(CHICKEN_TRANS(transcoder));
+
+ if (port == PORT_E)
+ val |= DDIE_TRAINING_OVERRIDE_ENABLE |
+ DDIE_TRAINING_OVERRIDE_VALUE;
+ else
+ val |= DDI_TRAINING_OVERRIDE_ENABLE |
+ DDI_TRAINING_OVERRIDE_VALUE;
+
+ I915_WRITE(CHICKEN_TRANS(transcoder), val);
+ POSTING_READ(CHICKEN_TRANS(transcoder));
+
+ udelay(1);
+
+ if (port == PORT_E)
+ val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
+ DDIE_TRAINING_OVERRIDE_VALUE);
+ else
+ val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
+ DDI_TRAINING_OVERRIDE_VALUE);
+
+ I915_WRITE(CHICKEN_TRANS(transcoder), val);
+ }
+
/* In HDMI/DVI mode, the port width, and swing/emphasis values
* are ignored so nothing special needs to be done besides
* enabling the port.
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Implement display w/a #1143
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
@ 2018-01-19 19:05 ` Patchwork
2018-01-19 20:07 ` [PATCH] " Rodrigo Vivi
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-01-19 19:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement display w/a #1143
URL : https://patchwork.freedesktop.org/series/36813/
State : success
== Summary ==
Series 36813v1 drm/i915: Implement display w/a #1143
https://patchwork.freedesktop.org/api/1.0/series/36813/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:426s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:435s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:511s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:294s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:500s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:504s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:492s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:483s
fi-elk-e7500 total:224 pass:168 dwarn:9 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:306s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:528s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:396s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:406s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:422s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:460s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:424s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:466s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:508s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:458s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:510s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:640s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:447s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:519s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:532s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:492s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:438s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:532s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:403s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:26 time:564s
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:485s
fi-skl-guc total:288 pass:216 dwarn:44 dfail:0 fail:0 skip:28 time:417s
fa43579841f4858ed082e779c5a45b829a6c99f4 drm-tip: 2018y-01m-19d-17h-26m-25s UTC integration manifest
c92cf75263e1 drm/i915: Implement display w/a #1143
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7727/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Implement display w/a #1143
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
2018-01-19 19:05 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-01-19 20:07 ` Rodrigo Vivi
2018-01-19 20:39 ` Runyan, Arthur J
2018-01-22 17:39 ` Ville Syrjälä
2018-01-20 1:59 ` ✗ Fi.CI.IGT: failure for " Patchwork
` (3 subsequent siblings)
5 siblings, 2 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2018-01-19 20:07 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, Runyan, Arthur J
On Fri, Jan 19, 2018 at 06:45:49PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently SKL/KBL need some manual help to get the
> programmed HDMI vswing to stick. Implement the relevant
> workaround (display w/a #1143).
>
> Note that the relevant chicken bits live in a transcoder register
> even though the bits affect a specific DDI port rather than a
> specific transcoder. Hence we must pick the correct transcoder
> register instance based on the port rather than based on the
> cpu_transcoder.
>
> Also note that for completeness I included support for DDI A/E
> in the code even though we never have HDMI on those ports.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10e1269ad6af..2e6d0dc01dc7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7012,8 +7012,12 @@ enum {
> #define CHICKEN_TRANS_A 0x420c0
> #define CHICKEN_TRANS_B 0x420c4
> #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> -#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> -#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> +#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> +#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> +#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
Wa on Bspec doesnt mention port E, although it makes sense to have...
maybe a WARN_ON if DDIE but not TRANS_A then?!
> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
>
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6260a882fbe4..7b1ab003279f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> crtc_state->hdmi_high_tmds_clock_ratio,
> crtc_state->hdmi_scrambling);
>
> + /* Display WA #1143: skl,kbl */
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
on KBL, but not on CFL?! Strange... Art?
> + /*
> + * For some reason these chicken bits have been
> + * stuffed into a transcoder register, event though
> + * the bits affect a specific DDI port rather than
> + * a specific transcoder.
> + */
> + static const enum transcoder port_to_transcoder[] = {
> + [PORT_A] = TRANSCODER_EDP,
> + [PORT_B] = TRANSCODER_A,
> + [PORT_C] = TRANSCODER_B,
> + [PORT_D] = TRANSCODER_C,
> + [PORT_E] = TRANSCODER_A,
> + };
> + enum transcoder transcoder = port_to_transcoder[port];
> + u32 val;
> +
> + val = I915_READ(CHICKEN_TRANS(transcoder));
> +
> + if (port == PORT_E)
> + val |= DDIE_TRAINING_OVERRIDE_ENABLE |
> + DDIE_TRAINING_OVERRIDE_VALUE;
> + else
> + val |= DDI_TRAINING_OVERRIDE_ENABLE |
> + DDI_TRAINING_OVERRIDE_VALUE;
> +
> + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> + POSTING_READ(CHICKEN_TRANS(transcoder));
> +
> + udelay(1);
> +
> + if (port == PORT_E)
> + val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
> + DDIE_TRAINING_OVERRIDE_VALUE);
> + else
> + val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
> + DDI_TRAINING_OVERRIDE_VALUE);
> +
> + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> + }
> +
> /* In HDMI/DVI mode, the port width, and swing/emphasis values
> * are ignored so nothing special needs to be done besides
> * enabling the port.
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Implement display w/a #1143
2018-01-19 20:07 ` [PATCH] " Rodrigo Vivi
@ 2018-01-19 20:39 ` Runyan, Arthur J
2018-01-22 17:39 ` Ville Syrjälä
1 sibling, 0 replies; 11+ messages in thread
From: Runyan, Arthur J @ 2018-01-19 20:39 UTC (permalink / raw)
To: Vivi, Rodrigo, Ville Syrjala; +Cc: intel-gfx
Yes, this applies to CFL also. CFL follows on from KBL and doesn't have any display changes, so for the workarounds you can translate KBL:All to CFL:All. There is a note about that.
-----Original Message-----
From: Vivi, Rodrigo
Sent: Friday, 19 January, 2018 12:08 PM
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org; Runyan, Arthur J <arthur.j.runyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Implement display w/a #1143
On Fri, Jan 19, 2018 at 06:45:49PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently SKL/KBL need some manual help to get the
> programmed HDMI vswing to stick. Implement the relevant
> workaround (display w/a #1143).
>
> Note that the relevant chicken bits live in a transcoder register
> even though the bits affect a specific DDI port rather than a
> specific transcoder. Hence we must pick the correct transcoder
> register instance based on the port rather than based on the
> cpu_transcoder.
>
> Also note that for completeness I included support for DDI A/E
> in the code even though we never have HDMI on those ports.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10e1269ad6af..2e6d0dc01dc7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7012,8 +7012,12 @@ enum {
> #define CHICKEN_TRANS_A 0x420c0
> #define CHICKEN_TRANS_B 0x420c4
> #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> -#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> -#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> +#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> +#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> +#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
Wa on Bspec doesnt mention port E, although it makes sense to have...
maybe a WARN_ON if DDIE but not TRANS_A then?!
> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
>
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6260a882fbe4..7b1ab003279f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> crtc_state->hdmi_high_tmds_clock_ratio,
> crtc_state->hdmi_scrambling);
>
> + /* Display WA #1143: skl,kbl */
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
on KBL, but not on CFL?! Strange... Art?
> + /*
> + * For some reason these chicken bits have been
> + * stuffed into a transcoder register, event though
> + * the bits affect a specific DDI port rather than
> + * a specific transcoder.
> + */
> + static const enum transcoder port_to_transcoder[] = {
> + [PORT_A] = TRANSCODER_EDP,
> + [PORT_B] = TRANSCODER_A,
> + [PORT_C] = TRANSCODER_B,
> + [PORT_D] = TRANSCODER_C,
> + [PORT_E] = TRANSCODER_A,
> + };
> + enum transcoder transcoder = port_to_transcoder[port];
> + u32 val;
> +
> + val = I915_READ(CHICKEN_TRANS(transcoder));
> +
> + if (port == PORT_E)
> + val |= DDIE_TRAINING_OVERRIDE_ENABLE |
> + DDIE_TRAINING_OVERRIDE_VALUE;
> + else
> + val |= DDI_TRAINING_OVERRIDE_ENABLE |
> + DDI_TRAINING_OVERRIDE_VALUE;
> +
> + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> + POSTING_READ(CHICKEN_TRANS(transcoder));
> +
> + udelay(1);
> +
> + if (port == PORT_E)
> + val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
> + DDIE_TRAINING_OVERRIDE_VALUE);
> + else
> + val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
> + DDI_TRAINING_OVERRIDE_VALUE);
> +
> + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> + }
> +
> /* In HDMI/DVI mode, the port width, and swing/emphasis values
> * are ignored so nothing special needs to be done besides
> * enabling the port.
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Implement display w/a #1143
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
2018-01-19 19:05 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-01-19 20:07 ` [PATCH] " Rodrigo Vivi
@ 2018-01-20 1:59 ` Patchwork
2018-01-22 17:41 ` [PATCH v2] " Ville Syrjala
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-01-20 1:59 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement display w/a #1143
URL : https://patchwork.freedesktop.org/series/36813/
State : failure
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail -> PASS (shard-snb) fdo#101623 +1
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Subgroup enable-disable:
pass -> FAIL (shard-apl) fdo#103715
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail -> PASS (shard-apl) fdo#100368 +1
Subgroup 2x-vblank-vs-dpms-suspend:
pass -> SKIP (shard-hsw)
Subgroup vblank-vs-modeset-suspend:
pass -> INCOMPLETE (shard-hsw) fdo#104682
Subgroup 2x-vblank-vs-dpms-suspend-interruptible:
pass -> INCOMPLETE (shard-hsw)
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104682 https://bugs.freedesktop.org/show_bug.cgi?id=104682
shard-apl total:2780 pass:1715 dwarn:1 dfail:0 fail:24 skip:1040 time:14733s
shard-hsw total:2754 pass:1709 dwarn:1 dfail:0 fail:11 skip:1029 time:13799s
shard-snb total:2780 pass:1316 dwarn:1 dfail:0 fail:13 skip:1450 time:8087s
Blacklisted hosts:
shard-kbl total:2780 pass:1834 dwarn:1 dfail:0 fail:26 skip:919 time:11113s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7727/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915: Implement display w/a #1143
2018-01-19 20:07 ` [PATCH] " Rodrigo Vivi
2018-01-19 20:39 ` Runyan, Arthur J
@ 2018-01-22 17:39 ` Ville Syrjälä
1 sibling, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-01-22 17:39 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Runyan, Arthur J
On Fri, Jan 19, 2018 at 12:07:47PM -0800, Rodrigo Vivi wrote:
> On Fri, Jan 19, 2018 at 06:45:49PM +0000, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Apparently SKL/KBL need some manual help to get the
> > programmed HDMI vswing to stick. Implement the relevant
> > workaround (display w/a #1143).
> >
> > Note that the relevant chicken bits live in a transcoder register
> > even though the bits affect a specific DDI port rather than a
> > specific transcoder. Hence we must pick the correct transcoder
> > register instance based on the port rather than based on the
> > cpu_transcoder.
> >
> > Also note that for completeness I included support for DDI A/E
> > in the code even though we never have HDMI on those ports.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> > drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 48 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 10e1269ad6af..2e6d0dc01dc7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7012,8 +7012,12 @@ enum {
> > #define CHICKEN_TRANS_A 0x420c0
> > #define CHICKEN_TRANS_B 0x420c4
> > #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> > -#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> > -#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> > +#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> > +#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> > +#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> > +#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
>
> Wa on Bspec doesnt mention port E, although it makes sense to have...
> maybe a WARN_ON if DDIE but not TRANS_A then?!
We pick the registers instance purely based on the port, so
there's no point in such a WARN_ON() as it would just be
asserting that we didn't mess up a part of the
port_to_transcoder[] table.
>
> > +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> > +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> >
> > #define DISP_ARB_CTL _MMIO(0x45000)
> > #define DISP_FBC_MEMORY_WAKE (1<<31)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 6260a882fbe4..7b1ab003279f 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> > crtc_state->hdmi_high_tmds_clock_ratio,
> > crtc_state->hdmi_scrambling);
> >
> > + /* Display WA #1143: skl,kbl */
> > + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>
> on KBL, but not on CFL?! Strange... Art?
>
> > + /*
> > + * For some reason these chicken bits have been
> > + * stuffed into a transcoder register, event though
> > + * the bits affect a specific DDI port rather than
> > + * a specific transcoder.
> > + */
> > + static const enum transcoder port_to_transcoder[] = {
> > + [PORT_A] = TRANSCODER_EDP,
> > + [PORT_B] = TRANSCODER_A,
> > + [PORT_C] = TRANSCODER_B,
> > + [PORT_D] = TRANSCODER_C,
> > + [PORT_E] = TRANSCODER_A,
> > + };
> > + enum transcoder transcoder = port_to_transcoder[port];
> > + u32 val;
> > +
> > + val = I915_READ(CHICKEN_TRANS(transcoder));
> > +
> > + if (port == PORT_E)
> > + val |= DDIE_TRAINING_OVERRIDE_ENABLE |
> > + DDIE_TRAINING_OVERRIDE_VALUE;
> > + else
> > + val |= DDI_TRAINING_OVERRIDE_ENABLE |
> > + DDI_TRAINING_OVERRIDE_VALUE;
> > +
> > + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> > + POSTING_READ(CHICKEN_TRANS(transcoder));
> > +
> > + udelay(1);
> > +
> > + if (port == PORT_E)
> > + val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
> > + DDIE_TRAINING_OVERRIDE_VALUE);
> > + else
> > + val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
> > + DDI_TRAINING_OVERRIDE_VALUE);
> > +
> > + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> > + }
> > +
> > /* In HDMI/DVI mode, the port width, and swing/emphasis values
> > * are ignored so nothing special needs to be done besides
> > * enabling the port.
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2] drm/i915: Implement display w/a #1143
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
` (2 preceding siblings ...)
2018-01-20 1:59 ` ✗ Fi.CI.IGT: failure for " Patchwork
@ 2018-01-22 17:41 ` Ville Syrjala
2018-01-22 17:48 ` Rodrigo Vivi
2018-01-22 18:25 ` ✓ Fi.CI.BAT: success for drm/i915: Implement display w/a #1143 (rev2) Patchwork
2018-01-23 3:40 ` ✗ Fi.CI.IGT: warning " Patchwork
5 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjala @ 2018-01-22 17:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Art Runyan, Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently SKL/KBL/CFL need some manual help to get the
programmed HDMI vswing to stick. Implement the relevant
workaround (display w/a #1143).
Note that the relevant chicken bits live in a transcoder register
even though the bits affect a specific DDI port rather than a
specific transcoder. Hence we must pick the correct transcoder
register instance based on the port rather than based on the
cpu_transcoder.
Also note that for completeness I included support for DDI A/E
in the code even though we never have HDMI on those ports.
v2: CFL needs the w/a as well (Rodrigo and Art)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10e1269ad6af..2e6d0dc01dc7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7012,8 +7012,12 @@ enum {
#define CHICKEN_TRANS_A 0x420c0
#define CHICKEN_TRANS_B 0x420c4
#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
-#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
-#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
+#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
+#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
+#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
+#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
+#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
+#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6260a882fbe4..e51559be2e3b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
crtc_state->hdmi_high_tmds_clock_ratio,
crtc_state->hdmi_scrambling);
+ /* Display WA #1143: skl,kbl,cfl */
+ if (IS_GEN9_BC(dev_priv)) {
+ /*
+ * For some reason these chicken bits have been
+ * stuffed into a transcoder register, event though
+ * the bits affect a specific DDI port rather than
+ * a specific transcoder.
+ */
+ static const enum transcoder port_to_transcoder[] = {
+ [PORT_A] = TRANSCODER_EDP,
+ [PORT_B] = TRANSCODER_A,
+ [PORT_C] = TRANSCODER_B,
+ [PORT_D] = TRANSCODER_C,
+ [PORT_E] = TRANSCODER_A,
+ };
+ enum transcoder transcoder = port_to_transcoder[port];
+ u32 val;
+
+ val = I915_READ(CHICKEN_TRANS(transcoder));
+
+ if (port == PORT_E)
+ val |= DDIE_TRAINING_OVERRIDE_ENABLE |
+ DDIE_TRAINING_OVERRIDE_VALUE;
+ else
+ val |= DDI_TRAINING_OVERRIDE_ENABLE |
+ DDI_TRAINING_OVERRIDE_VALUE;
+
+ I915_WRITE(CHICKEN_TRANS(transcoder), val);
+ POSTING_READ(CHICKEN_TRANS(transcoder));
+
+ udelay(1);
+
+ if (port == PORT_E)
+ val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
+ DDIE_TRAINING_OVERRIDE_VALUE);
+ else
+ val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
+ DDI_TRAINING_OVERRIDE_VALUE);
+
+ I915_WRITE(CHICKEN_TRANS(transcoder), val);
+ }
+
/* In HDMI/DVI mode, the port width, and swing/emphasis values
* are ignored so nothing special needs to be done besides
* enabling the port.
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915: Implement display w/a #1143
2018-01-22 17:41 ` [PATCH v2] " Ville Syrjala
@ 2018-01-22 17:48 ` Rodrigo Vivi
2018-01-24 18:18 ` Ville Syrjälä
0 siblings, 1 reply; 11+ messages in thread
From: Rodrigo Vivi @ 2018-01-22 17:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, Art Runyan
On Mon, Jan 22, 2018 at 05:41:31PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently SKL/KBL/CFL need some manual help to get the
> programmed HDMI vswing to stick. Implement the relevant
> workaround (display w/a #1143).
>
> Note that the relevant chicken bits live in a transcoder register
> even though the bits affect a specific DDI port rather than a
> specific transcoder. Hence we must pick the correct transcoder
> register instance based on the port rather than based on the
> cpu_transcoder.
>
> Also note that for completeness I included support for DDI A/E
> in the code even though we never have HDMI on those ports.
>
> v2: CFL needs the w/a as well (Rodrigo and Art)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10e1269ad6af..2e6d0dc01dc7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7012,8 +7012,12 @@ enum {
> #define CHICKEN_TRANS_A 0x420c0
> #define CHICKEN_TRANS_B 0x420c4
> #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> -#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> -#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> +#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> +#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> +#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
>
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6260a882fbe4..e51559be2e3b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> crtc_state->hdmi_high_tmds_clock_ratio,
> crtc_state->hdmi_scrambling);
>
> + /* Display WA #1143: skl,kbl,cfl */
> + if (IS_GEN9_BC(dev_priv)) {
> + /*
> + * For some reason these chicken bits have been
> + * stuffed into a transcoder register, event though
> + * the bits affect a specific DDI port rather than
> + * a specific transcoder.
> + */
> + static const enum transcoder port_to_transcoder[] = {
> + [PORT_A] = TRANSCODER_EDP,
> + [PORT_B] = TRANSCODER_A,
> + [PORT_C] = TRANSCODER_B,
> + [PORT_D] = TRANSCODER_C,
> + [PORT_E] = TRANSCODER_A,
> + };
> + enum transcoder transcoder = port_to_transcoder[port];
> + u32 val;
> +
> + val = I915_READ(CHICKEN_TRANS(transcoder));
> +
> + if (port == PORT_E)
> + val |= DDIE_TRAINING_OVERRIDE_ENABLE |
> + DDIE_TRAINING_OVERRIDE_VALUE;
> + else
> + val |= DDI_TRAINING_OVERRIDE_ENABLE |
> + DDI_TRAINING_OVERRIDE_VALUE;
> +
> + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> + POSTING_READ(CHICKEN_TRANS(transcoder));
> +
> + udelay(1);
> +
> + if (port == PORT_E)
> + val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
> + DDIE_TRAINING_OVERRIDE_VALUE);
> + else
> + val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
> + DDI_TRAINING_OVERRIDE_VALUE);
> +
> + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> + }
> +
> /* In HDMI/DVI mode, the port width, and swing/emphasis values
> * are ignored so nothing special needs to be done besides
> * enabling the port.
> --
> 2.13.6
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Implement display w/a #1143 (rev2)
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
` (3 preceding siblings ...)
2018-01-22 17:41 ` [PATCH v2] " Ville Syrjala
@ 2018-01-22 18:25 ` Patchwork
2018-01-23 3:40 ` ✗ Fi.CI.IGT: warning " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-01-22 18:25 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement display w/a #1143 (rev2)
URL : https://patchwork.freedesktop.org/series/36813/
State : success
== Summary ==
Series 36813v2 drm/i915: Implement display w/a #1143
https://patchwork.freedesktop.org/api/1.0/series/36813/revisions/2/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:421s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:379s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:481s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:481s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:467s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:466s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:279s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:510s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:390s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:416s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:409s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:498s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:457s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:578s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:432s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:511s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:527s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:491s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:486s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:418s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:428s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:527s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:566s
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:469s
06c8efda323ac918fad0e26d81e8884574ec8b84 drm-tip: 2018y-01m-22d-17h-43m-26s UTC integration manifest
0cc7ea9e43d0 drm/i915: Implement display w/a #1143
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7741/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Implement display w/a #1143 (rev2)
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
` (4 preceding siblings ...)
2018-01-22 18:25 ` ✓ Fi.CI.BAT: success for drm/i915: Implement display w/a #1143 (rev2) Patchwork
@ 2018-01-23 3:40 ` Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-01-23 3:40 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement display w/a #1143 (rev2)
URL : https://patchwork.freedesktop.org/series/36813/
State : warning
== Summary ==
Test kms_flip:
Subgroup vblank-vs-dpms-suspend:
pass -> INCOMPLETE (shard-hsw) fdo#103540
Subgroup vblank-vs-modeset-rpm:
pass -> DMESG-WARN (shard-apl)
Subgroup flip-vs-panning-vs-hang-interruptible:
dmesg-warn -> PASS (shard-snb) fdo#103821
Test kms_frontbuffer_tracking:
Subgroup fbc-tilingchange:
fail -> PASS (shard-apl)
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
fail -> PASS (shard-snb) fdo#101623
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-legacy:
fail -> PASS (shard-apl) fdo#103355
Test gem_exec_schedule:
Subgroup reorder-wide-blt:
pass -> FAIL (shard-apl) fdo#102848
Test drv_suspend:
Subgroup fence-restore-tiled2untiled-hibernate:
fail -> SKIP (shard-hsw) fdo#103375
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-apl) fdo#102254
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
shard-apl total:2675 pass:1671 dwarn:2 dfail:0 fail:21 skip:981 time:13568s
shard-hsw total:2709 pass:1695 dwarn:1 dfail:0 fail:10 skip:1001 time:15070s
shard-snb total:2753 pass:1319 dwarn:1 dfail:0 fail:10 skip:1423 time:7879s
Blacklisted hosts:
shard-kbl total:2735 pass:1821 dwarn:1 dfail:0 fail:25 skip:887 time:10553s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7741/shards.html
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915: Implement display w/a #1143
2018-01-22 17:48 ` Rodrigo Vivi
@ 2018-01-24 18:18 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-01-24 18:18 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Art Runyan
On Mon, Jan 22, 2018 at 09:48:46AM -0800, Rodrigo Vivi wrote:
> On Mon, Jan 22, 2018 at 05:41:31PM +0000, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Apparently SKL/KBL/CFL need some manual help to get the
> > programmed HDMI vswing to stick. Implement the relevant
> > workaround (display w/a #1143).
> >
> > Note that the relevant chicken bits live in a transcoder register
> > even though the bits affect a specific DDI port rather than a
> > specific transcoder. Hence we must pick the correct transcoder
> > register instance based on the port rather than based on the
> > cpu_transcoder.
> >
> > Also note that for completeness I included support for DDI A/E
> > in the code even though we never have HDMI on those ports.
> >
> > v2: CFL needs the w/a as well (Rodrigo and Art)
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Art Runyan <arthur.j.runyan@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Pushed to dinq. Thanks for the review.
>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> > drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 48 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 10e1269ad6af..2e6d0dc01dc7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7012,8 +7012,12 @@ enum {
> > #define CHICKEN_TRANS_A 0x420c0
> > #define CHICKEN_TRANS_B 0x420c4
> > #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> > -#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> > -#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> > +#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> > +#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> > +#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> > +#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
> > +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> > +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> >
> > #define DISP_ARB_CTL _MMIO(0x45000)
> > #define DISP_FBC_MEMORY_WAKE (1<<31)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 6260a882fbe4..e51559be2e3b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2433,6 +2433,48 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> > crtc_state->hdmi_high_tmds_clock_ratio,
> > crtc_state->hdmi_scrambling);
> >
> > + /* Display WA #1143: skl,kbl,cfl */
> > + if (IS_GEN9_BC(dev_priv)) {
> > + /*
> > + * For some reason these chicken bits have been
> > + * stuffed into a transcoder register, event though
> > + * the bits affect a specific DDI port rather than
> > + * a specific transcoder.
> > + */
> > + static const enum transcoder port_to_transcoder[] = {
> > + [PORT_A] = TRANSCODER_EDP,
> > + [PORT_B] = TRANSCODER_A,
> > + [PORT_C] = TRANSCODER_B,
> > + [PORT_D] = TRANSCODER_C,
> > + [PORT_E] = TRANSCODER_A,
> > + };
> > + enum transcoder transcoder = port_to_transcoder[port];
> > + u32 val;
> > +
> > + val = I915_READ(CHICKEN_TRANS(transcoder));
> > +
> > + if (port == PORT_E)
> > + val |= DDIE_TRAINING_OVERRIDE_ENABLE |
> > + DDIE_TRAINING_OVERRIDE_VALUE;
> > + else
> > + val |= DDI_TRAINING_OVERRIDE_ENABLE |
> > + DDI_TRAINING_OVERRIDE_VALUE;
> > +
> > + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> > + POSTING_READ(CHICKEN_TRANS(transcoder));
> > +
> > + udelay(1);
> > +
> > + if (port == PORT_E)
> > + val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
> > + DDIE_TRAINING_OVERRIDE_VALUE);
> > + else
> > + val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
> > + DDI_TRAINING_OVERRIDE_VALUE);
> > +
> > + I915_WRITE(CHICKEN_TRANS(transcoder), val);
> > + }
> > +
> > /* In HDMI/DVI mode, the port width, and swing/emphasis values
> > * are ignored so nothing special needs to be done besides
> > * enabling the port.
> > --
> > 2.13.6
> >
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-01-24 18:18 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-19 18:45 [PATCH] drm/i915: Implement display w/a #1143 Ville Syrjala
2018-01-19 19:05 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-01-19 20:07 ` [PATCH] " Rodrigo Vivi
2018-01-19 20:39 ` Runyan, Arthur J
2018-01-22 17:39 ` Ville Syrjälä
2018-01-20 1:59 ` ✗ Fi.CI.IGT: failure for " Patchwork
2018-01-22 17:41 ` [PATCH v2] " Ville Syrjala
2018-01-22 17:48 ` Rodrigo Vivi
2018-01-24 18:18 ` Ville Syrjälä
2018-01-22 18:25 ` ✓ Fi.CI.BAT: success for drm/i915: Implement display w/a #1143 (rev2) Patchwork
2018-01-23 3:40 ` ✗ Fi.CI.IGT: warning " Patchwork
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