[PATCH] drm/amdgpu: use queue 0 for kiq ring

[PATCH] drm/amdgpu: use queue 0 for kiq ring

[Huang Rui]

It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
queue 0.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ef04336..0cfb939 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 
 		amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
 
-		/* Using pipes 2/3 from MEC 2 seems cause problems */
-		if (mec == 1 && pipe > 1)
+		/*
+		 * 1. Using pipes 2/3 from MEC 2 seems cause problems.
+		 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
+		 * only can be issued on queue 0.
+		 */
+		if ((mec == 1 && pipe > 1) || queue != 0)
 			continue;
 
 		ring->me = mec + 1;
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: use queue 0 for kiq ring

[Alex Deucher]

On Mon, Jan 22, 2018 at 8:45 AM, Huang Rui <ray.huang@amd.com> wrote:
> It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
> queue 0.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index ef04336..0cfb939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
>
>                 amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
>
> -               /* Using pipes 2/3 from MEC 2 seems cause problems */
> -               if (mec == 1 && pipe > 1)
> +               /*
> +                * 1. Using pipes 2/3 from MEC 2 seems cause problems.
> +                * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
> +                * only can be issued on queue 0.
> +                */
> +               if ((mec == 1 && pipe > 1) || queue != 0)
>                         continue;
>
>                 ring->me = mec + 1;
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] drm/amdgpu: use queue 0 for kiq ring

[Andres Rodriguez]

On 2018-01-22 08:45 AM, Huang Rui wrote:
> It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
> queue 0.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index ef04336..0cfb939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
>   
>   		amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
>   
> -		/* Using pipes 2/3 from MEC 2 seems cause problems */
> -		if (mec == 1 && pipe > 1)
> +		/*
> +		 * 1. Using pipes 2/3 from MEC 2 seems cause problems.'

Could this have been related to #2? Should we just simplify this by 
guaranteeing KIQ MEC[0] PIPE[0] QUEUE[0]?

Regards,
Andres

> +		 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
> +		 * only can be issued on queue 0.
> +		 */
> +		if ((mec == 1 && pipe > 1) || queue != 0)
>   			continue;
>   
>   		ring->me = mec + 1;
> 
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Re: [PATCH] drm/amdgpu: use queue 0 for kiq ring

[Alex Deucher]

On Mon, Jan 22, 2018 at 12:53 PM, Andres Rodriguez <andresx7@gmail.com> wrote:
>
>
> On 2018-01-22 08:45 AM, Huang Rui wrote:
>>
>> It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued
>> on
>> queue 0.
>>
>> Signed-off-by: Huang Rui <ray.huang@amd.com>
>> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++--
>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index ef04336..0cfb939 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct
>> amdgpu_device *adev,
>>                 amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe,
>> &queue);
>>   -             /* Using pipes 2/3 from MEC 2 seems cause problems */
>> -               if (mec == 1 && pipe > 1)
>> +               /*
>> +                * 1. Using pipes 2/3 from MEC 2 seems cause problems.'
>
>
> Could this have been related to #2? Should we just simplify this by
> guaranteeing KIQ MEC[0] PIPE[0] QUEUE[0]?
>

It's possible.  Other OSes use a hardcoded config for KIQ so there may
be corner cases we never validated when using a non-standard config.

Alex

> Regards,
> Andres
>
>> +                * 2. It must use queue id 0, because
>> CGPG_IDLE/SAVE/LOAD/RUN
>> +                * only can be issued on queue 0.
>> +                */
>> +               if ((mec == 1 && pipe > 1) || queue != 0)
>>                         continue;
>>                 ring->me = mec + 1;
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] drm/amdgpu: use queue 0 for kiq ring

[Felix Kuehling]

KFD currently hard-codes MEC2, Pipe0, Queue0 for the HIQ. (For some
reason KFD numbers MECs starting from 1, not 0.)

So that narrows your choice for KIQ on MEC2 down to pipe == 1, queue == 0.

Regards,
  Felix


On 2018-01-22 08:45 AM, Huang Rui wrote:
> It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
> queue 0.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index ef04336..0cfb939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
>  
>  		amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
>  
> -		/* Using pipes 2/3 from MEC 2 seems cause problems */
> -		if (mec == 1 && pipe > 1)
> +		/*
> +		 * 1. Using pipes 2/3 from MEC 2 seems cause problems.
> +		 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
> +		 * only can be issued on queue 0.
> +		 */
> +		if ((mec == 1 && pipe > 1) || queue != 0)
>  			continue;
>  
>  		ring->me = mec + 1;

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Re: [PATCH] drm/amdgpu: use queue 0 for kiq ring

[Huang Rui]

On Tue, Jan 23, 2018 at 06:28:52AM +0800, Kuehling, Felix wrote:
> KFD currently hard-codes MEC2, Pipe0, Queue0 for the HIQ. (For some
> reason KFD numbers MECs starting from 1, not 0.)
> 
> So that narrows your choice for KIQ on MEC2 down to pipe == 1, queue == 0.
> 

Yes, actually, we use mec2 pipe1 queue0 for KIQ at current for this patch.

Thanks
Ray
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