* [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3)
@ 2018-01-23 3:06 Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 01/14] sdhci: add support for v3 capabilities Philippe Mathieu-Daudé
` (12 more replies)
0 siblings, 13 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
This series add minimum features required by Spec v3 to support UHS-I cards.
Since v7:
- we keep the 'capareg' property, this simplify a lot the series
- the ZynqMP uses the datasheet CAPAREG
- reset R-b/A-b
Note: https://www.google.com.ar/search?q=sdhci_imx0+caps show various console
output with i.MX6 capareg value of 0x0377c800
Since v6:
- rebased on upstream
- included spec v3 qtest back
Since v5:
- addressed Alistair reviews
- dropped "abstract generic-sdhci"
- dropped Linux Device Tree names
- split qtests in another series
- change the bcm2835 minimum blocksize to 1KB (Andrew Baumann)
- added Alistair R-b
- based on Alistair work:
- add SD tunning sequence via Host Control 2 to use UHS-I cards
- add CMD/DAT[] fields in the Present State (used in next series
to switch card voltage)
based on Alistair work:
- add SD tunning sequence via Host Control 2 to use UHS-I cards
- add CMD/DAT[] fields in the Present State (used in next series
to switch card voltage)
Since v4 ("SDHCI: add qtests and fix few issues"):
- spec_version default to v2 (current behaviour)
- addressed Alistair review (no v1, tell user about valid version)
Since v3:
- no change, but split back in 2 series, 1st part is "SDHCI: housekeeping v5",
Since v2:
- more detailed 'capabilities', all boards converted to use these properties
- since all qtests pass, removed the previous 'capareg' property
- added Stefan/Alistair R-b
- corrected 'access' LED behavior (Alistair's review)
- more uses of the registerfields API
- remove some dead code
- cosmetix:
- added more comments
- renamed a pair of registers
- reordered few struct members
Since v1:
- addressed Alistair Francis review comments, added some R-b
- only move register defines to "sd-internal.h"
- fixed deposit64() arguments
- dropped unuseful s->fifo_buffer = NULL
- use a qemu_irq for the LED, restrict the logging to ON/OFF
- fixed a trace format string error
- included Andrey Smirnov ACMD12ERRSTS write patch
- dropped few unuseful patches, and separate the Python polemical ones for later
>From the "SDHCI housekeeping" series:
- 1: we restrict part of "sd/sd.h" into local "sd-internal.h",
- 2,3: we somehow beautiful the code, no logical changes,
- 4-7: we refactor the common sysbus/pci qdev code,
- 8-10: we add plenty of trace events which will result useful later,
- 11: we finally expose a "dma-memory" property.
>From the "SDHCI: add a qtest and fix few issues" series:
- 12,13: fix registers
- 14,15: boards can specify which SDHCI Spec to use (v2 and v3 so far)
- 15-20: HCI qtest
Regards,
Phil.
$ git backport-diff
001/14:[down] 'sdhci: add support for v3 capabilities'
002/14:[----] [--] 'sdhci: rename the hostctl1 register'
003/14:[----] [--] 'sdhci: implement the Host Control 2 register (tuning sequence)'
004/14:[----] [--] 'sdbus: add trace events'
005/14:[0006] [FC] 'sdhci: implement UHS-I voltage switch'
006/14:[----] [--] 'sdhci: implement CMD/DAT[] fields in the Present State register'
007/14:[0015] [FC] 'hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3'
008/14:[0003] [FC] 'hw/arm/bcm2835_peripherals: change maximum block size to 1kB'
009/14:[0014] [FC] 'hw/arm/fsl-imx6: implement SDHCI Spec. v3'
010/14:[0017] [FC] 'hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet'
011/14:[down] 'hw/arm/xilinx_zynqmp: enable the UHS-I mode'
012/14:[0010] [FC] 'sdhci: check Spec v3 capabilities qtest'
013/14:[----] [--] 'sdhci: add a check_capab_v3() qtest'
014/14:[0019] [FC] 'sdhci: add Spec v4.2 register definitions'
Based-on: 20180123020820.1288-17-f4bug@amsat.org
Philippe Mathieu-Daudé (14):
sdhci: add support for v3 capabilities
sdhci: rename the hostctl1 register
sdhci: implement the Host Control 2 register (tuning sequence)
sdbus: add trace events
sdhci: implement UHS-I voltage switch
sdhci: implement CMD/DAT[] fields in the Present State register
hw/arm/bcm2835_peripherals: implement SDHCI Spec v3
hw/arm/bcm2835_peripherals: change maximum block size to 1kB
hw/arm/fsl-imx6: implement SDHCI Spec. v3
hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet
hw/arm/xilinx_zynqmp: enable the UHS-I mode
sdhci: check Spec v3 capabilities qtest
sdhci: add a check_capab_v3() qtest
sdhci: add Spec v4.2 register definitions
include/hw/sd/sd.h | 20 ++++++++
include/hw/sd/sdhci.h | 4 +-
hw/sd/sdhci-internal.h | 34 ++++++++++++
hw/arm/bcm2835_peripherals.c | 23 +++++----
hw/arm/fsl-imx6.c | 7 +++
hw/arm/xlnx-zynqmp.c | 30 +++++++----
hw/sd/core.c | 61 +++++++++++++++++++++-
hw/sd/sd.c | 29 +++++++++++
hw/sd/sdhci.c | 120 ++++++++++++++++++++++++++++++++++++++-----
hw/sd/trace-events | 8 +++
tests/sdhci-test.c | 29 +++++++++++
tests/Makefile.include | 1 +
12 files changed, 330 insertions(+), 36 deletions(-)
--
2.15.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 01/14] sdhci: add support for v3 capabilities
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 02/14] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
` (11 subsequent siblings)
12 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/sdhci-internal.h | 13 ++++++++++++
hw/sd/sdhci.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 4ed9727ec3..9111f6856a 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -43,6 +43,7 @@
#define SDHC_TRNS_DMA 0x0001
#define SDHC_TRNS_BLK_CNT_EN 0x0002
#define SDHC_TRNS_ACMD12 0x0004
+#define SDHC_TRNS_ACMD23 0x0008 /* since v3 */
#define SDHC_TRNS_READ 0x0010
#define SDHC_TRNS_MULTI 0x0020
#define SDHC_TRNMOD_MASK 0x0037
@@ -189,6 +190,7 @@ FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
FIELD(SDHC_CAPAB, TOUNIT, 7, 1);
FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8);
FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2);
+FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */
FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */
FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */
FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1);
@@ -198,6 +200,17 @@ FIELD(SDHC_CAPAB, V33, 24, 1);
FIELD(SDHC_CAPAB, V30, 25, 1);
FIELD(SDHC_CAPAB, V18, 26, 1);
FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */
+FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */
+FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */
+FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */
+FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */
+FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */
+FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */
+FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */
+FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3 */
+FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */
+FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */
+FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */
/* HWInit Maximum Current Capabilities Register 0x0 */
#define SDHC_MAXCURR 0x48
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index bc3a4f6e16..c32adc0f24 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -70,6 +70,9 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
uint8_t freq, Error **errp)
{
+ if (s->sd_spec_version >= 3) {
+ return false;
+ }
switch (freq) {
case 0:
case 10 ... 63:
@@ -89,6 +92,50 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
bool y;
switch (s->sd_spec_version) {
+ case 3:
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
+ trace_sdhci_capareg("async interrupt", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
+ if (val) {
+ error_setg(errp, "slot-type not supported");
+ return;
+ }
+ trace_sdhci_capareg("slot type", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
+
+ if (val != 0b10) {
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
+ trace_sdhci_capareg("8-bit bus", val);
+ }
+ msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
+ trace_sdhci_capareg("bus speed mask", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
+ trace_sdhci_capareg("driver strength mask", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
+ trace_sdhci_capareg("timer re-tuning", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
+ trace_sdhci_capareg("use SDR50 tuning", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
+ trace_sdhci_capareg("re-tuning mode", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
+ trace_sdhci_capareg("clock multiplier", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
+
+ /* fallback */
case 2: /* default version */
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
trace_sdhci_capareg("ADMA2", val);
@@ -1227,8 +1274,11 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
{
Error *local_err = NULL;
- if (s->sd_spec_version != 2) {
- error_setg(errp, "Only Spec v2 is supported");
+ switch (s->sd_spec_version) {
+ case 2 ... 3:
+ break;
+ default:
+ error_setg(errp, "Only Spec v2/v3 are supported");
return;
}
s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 02/14] sdhci: rename the hostctl1 register
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 01/14] sdhci: add support for v3 capabilities Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
` (10 subsequent siblings)
12 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
As per the Spec v3.00
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
include/hw/sd/sdhci.h | 2 +-
hw/sd/sdhci.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 96e07de2a2..5af9e0dc5a 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -57,7 +57,7 @@ typedef struct SDHCIState {
uint16_t cmdreg; /* Command Register */
uint32_t rspreg[4]; /* Response Registers 0-3 */
uint32_t prnsts; /* Present State Register */
- uint8_t hostctl; /* Host Control Register */
+ uint8_t hostctl1; /* Host Control Register */
uint8_t pwrcon; /* Power control Register */
uint8_t blkgap; /* Block Gap Control Register */
uint8_t wakcon; /* WakeUp Control Register */
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index c32adc0f24..013c35e585 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -691,7 +691,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
uint32_t adma1 = 0;
uint64_t adma2 = 0;
hwaddr entry_addr = (hwaddr)s->admasysaddr;
- switch (SDHC_DMA_TYPE(s->hostctl)) {
+ switch (SDHC_DMA_TYPE(s->hostctl1)) {
case SDHC_CTRL_ADMA2_32:
dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2,
sizeof(adma2));
@@ -880,7 +880,7 @@ static void sdhci_data_transfer(void *opaque)
SDHCIState *s = (SDHCIState *)opaque;
if (s->trnmod & SDHC_TRNS_DMA) {
- switch (SDHC_DMA_TYPE(s->hostctl)) {
+ switch (SDHC_DMA_TYPE(s->hostctl1)) {
case SDHC_CTRL_SDMA:
if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
sdhci_sdma_transfer_single_block(s);
@@ -989,7 +989,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
ret = s->prnsts;
break;
case SDHC_HOSTCTL:
- ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
+ ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
(s->wakcon << 24);
break;
case SDHC_CLKCON:
@@ -1107,7 +1107,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
MASKED_WRITE(s->sdmasysad, mask, value);
/* Writing to last byte of sdmasysad might trigger transfer */
if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
- s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
+ s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
if (s->trnmod & SDHC_TRNS_MULTI) {
sdhci_sdma_transfer_multi_blocks(s);
} else {
@@ -1159,7 +1159,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
if (!(mask & 0xFF0000)) {
sdhci_blkgap_write(s, value >> 16);
}
- MASKED_WRITE(s->hostctl, mask, value);
+ MASKED_WRITE(s->hostctl1, mask, value);
MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
@@ -1378,7 +1378,7 @@ const VMStateDescription sdhci_vmstate = {
VMSTATE_UINT16(cmdreg, SDHCIState),
VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
VMSTATE_UINT32(prnsts, SDHCIState),
- VMSTATE_UINT8(hostctl, SDHCIState),
+ VMSTATE_UINT8(hostctl1, SDHCIState),
VMSTATE_UINT8(pwrcon, SDHCIState),
VMSTATE_UINT8(blkgap, SDHCIState),
VMSTATE_UINT8(wakcon, SDHCIState),
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence)
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 01/14] sdhci: add support for v3 capabilities Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 02/14] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:37 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events Philippe Mathieu-Daudé
` (9 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
from qemu/xilinx tag xilinx-v2015.2]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/sdhci-internal.h | 10 ++++++++++
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 22 +++++++++++++++++++---
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 9111f6856a..e7cbea297f 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -184,6 +184,16 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1);
FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1);
FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
+/* Host Control Register 2 (since v3) */
+#define SDHC_HOSTCTL2 0x3E
+FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
+FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
+FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
+
/* HWInit Capabilities Register 0x05E80080 */
#define SDHC_CAPAB 0x40
FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 5af9e0dc5a..0fff941a98 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -71,6 +71,7 @@ typedef struct SDHCIState {
uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
uint16_t acmd12errsts; /* Auto CMD12 error status register */
+ uint16_t hostctl2; /* Host Control 2 */
uint64_t admasysaddr; /* ADMA System Address Register */
/* Read-only registers */
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 013c35e585..b7e69fbc22 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -408,14 +408,29 @@ static void sdhci_end_transfer(SDHCIState *s)
static void sdhci_read_block_from_card(SDHCIState *s)
{
int index = 0;
+ uint8_t data;
+ const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
if ((s->trnmod & SDHC_TRNS_MULTI) &&
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
return;
}
- for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
- s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
+ for (index = 0; index < blk_size; index++) {
+ data = sdbus_read_data(&s->sdbus);
+ if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
+ /* Device is not in tunning */
+ s->fifo_buffer[index] = data;
+ }
+ }
+
+ if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
+ /* Device is in tunning */
+ s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
+ s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
+ s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
+ SDHC_DATA_INHIBIT);
+ goto read_done;
}
/* New data now available for READ through Buffer Port Register */
@@ -440,6 +455,7 @@ static void sdhci_read_block_from_card(SDHCIState *s)
}
}
+read_done:
sdhci_update_irq(s);
}
@@ -1005,7 +1021,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
ret = s->norintsigen | (s->errintsigen << 16);
break;
case SDHC_ACMD12ERRSTS:
- ret = s->acmd12errsts;
+ ret = s->acmd12errsts | (s->hostctl2 << 16);
break;
case SDHC_CAPAB:
ret = (uint32_t)s->capareg;
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:34 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
` (8 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/core.c | 14 ++++++++++++--
hw/sd/trace-events | 5 +++++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/sd/core.c b/hw/sd/core.c
index 295dc44ab7..498284f109 100644
--- a/hw/sd/core.c
+++ b/hw/sd/core.c
@@ -23,6 +23,12 @@
#include "hw/qdev-core.h"
#include "sysemu/block-backend.h"
#include "hw/sd/sd.h"
+#include "trace.h"
+
+static inline const char *sdbus_name(SDBus *sdbus)
+{
+ return sdbus->qbus.name;
+}
static SDState *get_card(SDBus *sdbus)
{
@@ -39,6 +45,7 @@ int sdbus_do_command(SDBus *sdbus, SDRequest *req, uint8_t *response)
{
SDState *card = get_card(sdbus);
+ trace_sdbus_command(sdbus_name(sdbus), req->cmd, req->arg, req->crc);
if (card) {
SDCardClass *sc = SD_CARD_GET_CLASS(card);
@@ -52,6 +59,7 @@ void sdbus_write_data(SDBus *sdbus, uint8_t value)
{
SDState *card = get_card(sdbus);
+ trace_sdbus_write(sdbus_name(sdbus), value);
if (card) {
SDCardClass *sc = SD_CARD_GET_CLASS(card);
@@ -62,14 +70,16 @@ void sdbus_write_data(SDBus *sdbus, uint8_t value)
uint8_t sdbus_read_data(SDBus *sdbus)
{
SDState *card = get_card(sdbus);
+ uint8_t value = 0;
if (card) {
SDCardClass *sc = SD_CARD_GET_CLASS(card);
- return sc->read_data(card);
+ value = sc->read_data(card);
}
+ trace_sdbus_read(sdbus_name(sdbus), value);
- return 0;
+ return value;
}
bool sdbus_data_ready(SDBus *sdbus)
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index 78d8707669..ea2746c8b7 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -1,5 +1,10 @@
# See docs/devel/tracing.txt for syntax documentation.
+# hw/sd/core.c
+sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
+sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
+sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x"
+
# hw/sd/sdhci.c
sdhci_set_inserted(const char *level) "card state changed: %s"
sdhci_send_command(uint8_t cmd, uint32_t arg) "CMD%02u ARG[0x%08x]"
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:39 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
` (7 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
from qemu/xilinx tag xilinx-v2015.2]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/sd/sd.h | 16 ++++++++++++++++
include/hw/sd/sdhci.h | 1 +
hw/sd/core.c | 13 +++++++++++++
hw/sd/sd.c | 13 +++++++++++++
hw/sd/sdhci.c | 12 +++++++++++-
hw/sd/trace-events | 1 +
6 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
index 96caefe373..f086679493 100644
--- a/include/hw/sd/sd.h
+++ b/include/hw/sd/sd.h
@@ -55,6 +55,20 @@
#define AKE_SEQ_ERROR (1 << 3)
#define OCR_CCS_BITN 30
+typedef enum {
+ SD_VOLTAGE_0_4V = 400, /* currently not supported */
+ SD_VOLTAGE_1_8V = 1800,
+ SD_VOLTAGE_3_0V = 3000,
+ SD_VOLTAGE_3_3V = 3300,
+} sd_voltage_mv_t;
+
+typedef enum {
+ UHS_NOT_SUPPORTED = 0,
+ UHS_I = 1,
+ UHS_II = 2, /* currently not supported */
+ UHS_III = 3, /* currently not supported */
+} sd_uhs_mode_t;
+
typedef enum {
sd_none = -1,
sd_bc = 0, /* broadcast -- no response */
@@ -88,6 +102,7 @@ typedef struct {
void (*write_data)(SDState *sd, uint8_t value);
uint8_t (*read_data)(SDState *sd);
bool (*data_ready)(SDState *sd);
+ void (*set_voltage)(SDState *sd, uint16_t millivolts);
void (*enable)(SDState *sd, bool enable);
bool (*get_inserted)(SDState *sd);
bool (*get_readonly)(SDState *sd);
@@ -134,6 +149,7 @@ void sd_enable(SDState *sd, bool enable);
/* Functions to be used by qdevified callers (working via
* an SDBus rather than directly with SDState)
*/
+void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts);
int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
void sdbus_write_data(SDBus *sd, uint8_t value);
uint8_t sdbus_read_data(SDBus *sd);
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 0fff941a98..06e3784e54 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -93,6 +93,7 @@ typedef struct SDHCIState {
/* Configurable properties */
bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
uint8_t sd_spec_version;
+ uint8_t uhs_mode;
} SDHCIState;
#define TYPE_PCI_SDHCI "sdhci-pci"
diff --git a/hw/sd/core.c b/hw/sd/core.c
index 498284f109..6d198ea775 100644
--- a/hw/sd/core.c
+++ b/hw/sd/core.c
@@ -41,6 +41,19 @@ static SDState *get_card(SDBus *sdbus)
return SD_CARD(kid->child);
}
+void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts)
+{
+ SDState *card = get_card(sdbus);
+
+ trace_sdbus_set_voltage(sdbus_name(sdbus), millivolts);
+ if (card) {
+ SDCardClass *sc = SD_CARD_GET_CLASS(card);
+
+ assert(sc->set_voltage);
+ sc->set_voltage(card, millivolts);
+ }
+}
+
int sdbus_do_command(SDBus *sdbus, SDRequest *req, uint8_t *response)
{
SDState *card = get_card(sdbus);
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 35347a5bbc..609b2da14f 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -128,6 +128,18 @@ struct SDState {
bool enable;
};
+static void sd_set_voltage(SDState *sd, uint16_t millivolts)
+{
+ switch (millivolts) {
+ case 3001 ... 3600: /* SD_VOLTAGE_3_3V */
+ case 2001 ... 3000: /* SD_VOLTAGE_3_0V */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "SD card voltage not supported: %.3fV",
+ millivolts / 1000.f);
+ }
+}
+
static void sd_set_mode(SDState *sd)
{
switch (sd->state) {
@@ -1925,6 +1937,7 @@ static void sd_class_init(ObjectClass *klass, void *data)
dc->reset = sd_reset;
dc->bus_type = TYPE_SD_BUS;
+ sc->set_voltage = sd_set_voltage;
sc->do_command = sd_do_command;
sc->write_data = sd_write_data;
sc->read_data = sd_read_data;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index b7e69fbc22..aec6ca4d14 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1255,7 +1255,16 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
sdhci_update_irq(s);
break;
case SDHC_ACMD12ERRSTS:
- MASKED_WRITE(s->acmd12errsts, mask, value);
+ MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
+ if (s->uhs_mode >= UHS_I) {
+ MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
+
+ if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
+ sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
+ } else {
+ sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
+ }
+ }
break;
case SDHC_CAPAB:
@@ -1310,6 +1319,7 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
+ DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
\
/* Capabilities registers provide information on supported
* features of this specific host controller implementation */ \
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index ea2746c8b7..84d2f398b1 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -4,6 +4,7 @@
sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x"
+sdbus_set_voltage(const char *bus_name, uint16_t millivolts) "@%s %u (mV)"
# hw/sd/sdhci.c
sdhci_set_inserted(const char *level) "card state changed: %s"
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:44 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
` (6 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
from qemu/xilinx tag xilinx-v2015.2]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/sdhci-internal.h | 2 ++
include/hw/sd/sd.h | 4 ++++
hw/sd/core.c | 34 ++++++++++++++++++++++++++++++++++
hw/sd/sd.c | 16 ++++++++++++++++
hw/sd/sdhci.c | 4 ++++
hw/sd/trace-events | 2 ++
6 files changed, 62 insertions(+)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e7cbea297f..514ecd4841 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -82,6 +82,8 @@
#define SDHC_CARD_PRESENT 0x00010000
#define SDHC_CARD_DETECT 0x00040000
#define SDHC_WRITE_PROTECT 0x00080000
+FIELD(SDHC_PRNSTS, DAT_LVL, 20, 4);
+FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1);
#define TRANSFERRING_DATA(x) \
((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE))
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
index f086679493..bf1eb0713c 100644
--- a/include/hw/sd/sd.h
+++ b/include/hw/sd/sd.h
@@ -103,6 +103,8 @@ typedef struct {
uint8_t (*read_data)(SDState *sd);
bool (*data_ready)(SDState *sd);
void (*set_voltage)(SDState *sd, uint16_t millivolts);
+ uint8_t (*get_dat_lines)(SDState *sd);
+ bool (*get_cmd_line)(SDState *sd);
void (*enable)(SDState *sd, bool enable);
bool (*get_inserted)(SDState *sd);
bool (*get_readonly)(SDState *sd);
@@ -150,6 +152,8 @@ void sd_enable(SDState *sd, bool enable);
* an SDBus rather than directly with SDState)
*/
void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts);
+uint8_t sdbus_get_dat_lines(SDBus *sdbus);
+bool sdbus_get_cmd_line(SDBus *sdbus);
int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
void sdbus_write_data(SDBus *sd, uint8_t value);
uint8_t sdbus_read_data(SDBus *sd);
diff --git a/hw/sd/core.c b/hw/sd/core.c
index 6d198ea775..3c6eae6c88 100644
--- a/hw/sd/core.c
+++ b/hw/sd/core.c
@@ -41,6 +41,40 @@ static SDState *get_card(SDBus *sdbus)
return SD_CARD(kid->child);
}
+uint8_t sdbus_get_dat_lines(SDBus *sdbus)
+{
+ SDState *slave = get_card(sdbus);
+ uint8_t dat_lines = 0b1111; /* 4 bit bus width */
+
+ if (slave) {
+ SDCardClass *sc = SD_CARD_GET_CLASS(slave);
+
+ if (sc->get_dat_lines) {
+ dat_lines = sc->get_dat_lines(slave);
+ }
+ }
+ trace_sdbus_get_dat_lines(sdbus_name(sdbus), dat_lines);
+
+ return dat_lines;
+}
+
+bool sdbus_get_cmd_line(SDBus *sdbus)
+{
+ SDState *slave = get_card(sdbus);
+ bool cmd_line = true;
+
+ if (slave) {
+ SDCardClass *sc = SD_CARD_GET_CLASS(slave);
+
+ if (sc->get_cmd_line) {
+ cmd_line = sc->get_cmd_line(slave);
+ }
+ }
+ trace_sdbus_get_cmd_line(sdbus_name(sdbus), cmd_line);
+
+ return cmd_line;
+}
+
void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts)
{
SDState *card = get_card(sdbus);
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 609b2da14f..ab9be561d2 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -126,8 +126,20 @@ struct SDState {
BlockBackend *blk;
bool enable;
+ uint8_t dat_lines;
+ bool cmd_line;
};
+static uint8_t sd_get_dat_lines(SDState *sd)
+{
+ return sd->enable ? sd->dat_lines : 0;
+}
+
+static bool sd_get_cmd_line(SDState *sd)
+{
+ return sd->enable ? sd->cmd_line : false;
+}
+
static void sd_set_voltage(SDState *sd, uint16_t millivolts)
{
switch (millivolts) {
@@ -457,6 +469,8 @@ static void sd_reset(DeviceState *dev)
sd->blk_len = 0x200;
sd->pwd_len = 0;
sd->expecting_acmd = false;
+ sd->dat_lines = 0xf;
+ sd->cmd_line = true;
sd->multi_blk_cnt = 0;
}
@@ -1938,6 +1952,8 @@ static void sd_class_init(ObjectClass *klass, void *data)
dc->bus_type = TYPE_SD_BUS;
sc->set_voltage = sd_set_voltage;
+ sc->get_dat_lines = sd_get_dat_lines;
+ sc->get_cmd_line = sd_get_cmd_line;
sc->do_command = sd_do_command;
sc->write_data = sd_write_data;
sc->read_data = sd_read_data;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index aec6ca4d14..b7fb262750 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1003,6 +1003,10 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
break;
case SDHC_PRNSTS:
ret = s->prnsts;
+ ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
+ sdbus_get_dat_lines(&s->sdbus));
+ ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
+ sdbus_get_cmd_line(&s->sdbus));
break;
case SDHC_HOSTCTL:
ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index 84d2f398b1..0f8536db32 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -5,6 +5,8 @@ sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s
sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x"
sdbus_set_voltage(const char *bus_name, uint16_t millivolts) "@%s %u (mV)"
+sdbus_get_dat_lines(const char *bus_name, uint8_t dat_lines) "@%s dat_lines: %u"
+sdbus_get_cmd_line(const char *bus_name, bool cmd_line) "@%s cmd_line: %u"
# hw/sd/sdhci.c
sdhci_set_inserted(const char *level) "card state changed: %s"
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:45 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
` (5 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite, open list:ARM
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/bcm2835_peripherals.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 12e0dd11af..0570cc4ad3 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -254,14 +254,19 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->peri_mr, RNG_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));
- /* Extended Mass Media Controller */
- object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
- &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
-
+ /* Extended Mass Media Controller
+ *
+ * Compatible with:
+ * - SD Host Controller Specification Version 3.0 Draft 1.0
+ * - SDIO Specification Version 3.0
+ * - MMC Specification Version 4.4
+ *
+ * For the exact details please refer to the Arasan documentation:
+ * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf ¯\_(ツ)_/¯
+ */
+ object_property_set_uint(OBJECT(&s->sdhci), 3, "sd-spec-version", &err);
+ object_property_set_uint(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
+ &err);
object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk",
&err);
if (err) {
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:45 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
` (4 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite, open list:ARM
following the datasheet.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/bcm2835_peripherals.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 0570cc4ad3..6b86a99b14 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -19,7 +19,7 @@
#define BCM2835_VC_PERI_BASE 0x7e000000
/* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
-#define BCM2835_SDHC_CAPAREG 0x52034b4
+#define BCM2835_SDHC_CAPAREG 0x52134b4
static void bcm2835_peripherals_init(Object *obj)
{
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 09/14] hw/arm/fsl-imx6: implement SDHCI Spec. v3
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:46 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
` (3 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite, open list:ARM
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
various FreeBSD console output from google search show this register having
a value of 0x0377c800.
hw/arm/fsl-imx6.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index b0d4088290..1f4607f206 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -27,6 +27,8 @@
#include "chardev/char.h"
#include "qemu/error-report.h"
+#define IMX6_ESDHC_CAPABILITIES 0x057834b4
+
#define NAME_SIZE 20
static void fsl_imx6_init(Object *obj)
@@ -348,6 +350,11 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
{ FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
};
+ /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
+ &err);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
+ "capareg", &err);
object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 10/14] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:48 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 11/14] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
` (2 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite, Edgar E. Iglesias,
open list:Xilinx ZynqMP
checking Xilinx datasheet "UG1085" (v1.7)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/xlnx-zynqmp.c | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 325642058b..33d5fe53d8 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -50,6 +50,8 @@
#define DPDMA_ADDR 0xfd4c0000
#define DPDMA_IRQ 116
+#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
+
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
@@ -381,22 +383,27 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
- char *bus_name;
-
- object_property_set_bool(OBJECT(&s->sdhci[i]), true,
- "realized", &err);
+ char *bus_name = g_strdup_printf("sd-bus%d", i);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
+ Object *sdhci = OBJECT(&s->sdhci[i]);
+
+ /* Compatible with:
+ * - SD Host Controller Specification Version 3.00
+ * - SDIO Specification Version 3.0
+ * - eMMC Specification Version 4.51
+ */
+ object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
+ object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
+ object_property_set_bool(sdhci, true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
- sdhci_addr[i]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
- gic_spi[sdhci_intr[i]]);
+ sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
+ sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
+
/* Alias controller SD bus to the SoC itself */
- bus_name = g_strdup_printf("sd-bus%d", i);
- object_property_add_alias(OBJECT(s), bus_name,
- OBJECT(&s->sdhci[i]), "sd-bus",
+ object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
&error_abort);
g_free(bus_name);
}
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 11/14] hw/arm/xilinx_zynqmp: enable the UHS-I mode
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 22:47 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 12/14] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 13/14] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
12 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite, Edgar E. Iglesias,
open list:Xilinx ZynqMP
see the Xilinx datasheet "UG1085" (v1.7)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/xlnx-zynqmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 33d5fe53d8..bb4265a4ce 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -394,6 +394,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
*/
object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
+ object_property_set_uint(sdhci, UHS_I, "uhs", &err);
object_property_set_bool(sdhci, true, "realized", &err);
if (err) {
error_propagate(errp, err);
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 12/14] sdhci: check Spec v3 capabilities qtest
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 11/14] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 13/14] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
12 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
tests/sdhci-test.c | 12 ++++++++++++
tests/Makefile.include | 1 +
2 files changed, 13 insertions(+)
diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c
index aae2cfc1b5..56eefdafd8 100644
--- a/tests/sdhci-test.c
+++ b/tests/sdhci-test.c
@@ -42,10 +42,22 @@ static const struct sdhci_t {
{ "arm", "smdkc210",
{0x12510000, 2, 0, {1, 0x5e80080} } },
+ /* i.MX 6 */
+ { "arm", "sabrelite",
+ {0x02190000, 3, 0, {1, 0x057834b4} } },
+
+ /* BCM2835 */
+ { "arm", "raspi2",
+ {0x3f300000, 3, 52, {0, 0x052134b4} } },
+
/* Zynq-7000 */
{ "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */
{0xe0100000, 2, 0, {1, 0x69ec0080} } },
+ /* ZynqMP */
+ { "aarch64", "xlnx-zcu102", /* Datasheet: UG1085 (v1.7) */
+ {0xff160000, 3, 0, {1, 0x280737ec6481} } },
+
};
static struct {
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 756725b0f9..74cae947cb 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -367,6 +367,7 @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
check-qtest-arm-y += tests/sdhci-test$(EXESUF)
check-qtest-aarch64-y = tests/numa-test$(EXESUF)
+check-qtest-aarch64-y += tests/sdhci-test$(EXESUF)
check-qtest-microblazeel-y = $(check-qtest-microblaze-y)
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v8 13/14] sdhci: add a check_capab_v3() qtest
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 12/14] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
@ 2018-01-23 3:06 ` Philippe Mathieu-Daudé
12 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-23 3:06 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell
Cc: Philippe Mathieu-Daudé,
qemu-devel, Edgar E . Iglesias, Andrey Smirnov, Prasad J Pandit,
Sai Pavan Boddu, Peter Crosthwaite
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
---
tests/sdhci-test.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c
index 56eefdafd8..a8970da71a 100644
--- a/tests/sdhci-test.c
+++ b/tests/sdhci-test.c
@@ -16,6 +16,8 @@
#define SDHC_CAPAB 0x40
FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); /* since v2 */
FIELD(SDHC_CAPAB, SDMA, 22, 1);
+FIELD(SDHC_CAPAB, SDR, 32, 3); /* since v3 */
+FIELD(SDHC_CAPAB, DRIVER, 36, 3); /* since v3 */
#define SDHC_HCVER 0xFE
static const struct sdhci_t {
@@ -160,6 +162,20 @@ static void check_capab_sdma(uintptr_t addr, bool supported)
g_assert_cmpuint(capab_sdma, ==, supported);
}
+static void check_capab_v3(uintptr_t addr, uint8_t version)
+{
+ uint64_t capab, capab_v3;
+
+ if (version < 3) {
+ /* before v3 those fields are RESERVED */
+ capab = sdhci_readq(addr, SDHC_CAPAB);
+ capab_v3 = FIELD_EX64(capab, SDHC_CAPAB, SDR);
+ g_assert_cmpuint(capab_v3, ==, 0);
+ capab_v3 = FIELD_EX64(capab, SDHC_CAPAB, DRIVER);
+ g_assert_cmpuint(capab_v3, ==, 0);
+ }
+}
+
static void machine_start(const struct sdhci_t *test)
{
if (test->pci.vendor_id) {
@@ -202,6 +218,7 @@ static void test_machine(const void *data)
check_specs_version(test->sdhci.addr, test->sdhci.version);
check_capab_capareg(test->sdhci.addr, test->sdhci.capab.reg);
check_capab_readonly(test->sdhci.addr);
+ check_capab_v3(test->sdhci.addr, test->sdhci.version);
check_capab_sdma(test->sdhci.addr, test->sdhci.capab.sdma);
check_capab_baseclock(test->sdhci.addr, test->sdhci.baseclock);
--
2.15.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events Philippe Mathieu-Daudé
@ 2018-01-23 22:34 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> hw/sd/core.c | 14 ++++++++++++--
> hw/sd/trace-events | 5 +++++
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/hw/sd/core.c b/hw/sd/core.c
> index 295dc44ab7..498284f109 100644
> --- a/hw/sd/core.c
> +++ b/hw/sd/core.c
> @@ -23,6 +23,12 @@
> #include "hw/qdev-core.h"
> #include "sysemu/block-backend.h"
> #include "hw/sd/sd.h"
> +#include "trace.h"
> +
> +static inline const char *sdbus_name(SDBus *sdbus)
> +{
> + return sdbus->qbus.name;
> +}
>
> static SDState *get_card(SDBus *sdbus)
> {
> @@ -39,6 +45,7 @@ int sdbus_do_command(SDBus *sdbus, SDRequest *req, uint8_t *response)
> {
> SDState *card = get_card(sdbus);
>
> + trace_sdbus_command(sdbus_name(sdbus), req->cmd, req->arg, req->crc);
> if (card) {
> SDCardClass *sc = SD_CARD_GET_CLASS(card);
>
> @@ -52,6 +59,7 @@ void sdbus_write_data(SDBus *sdbus, uint8_t value)
> {
> SDState *card = get_card(sdbus);
>
> + trace_sdbus_write(sdbus_name(sdbus), value);
> if (card) {
> SDCardClass *sc = SD_CARD_GET_CLASS(card);
>
> @@ -62,14 +70,16 @@ void sdbus_write_data(SDBus *sdbus, uint8_t value)
> uint8_t sdbus_read_data(SDBus *sdbus)
> {
> SDState *card = get_card(sdbus);
> + uint8_t value = 0;
>
> if (card) {
> SDCardClass *sc = SD_CARD_GET_CLASS(card);
>
> - return sc->read_data(card);
> + value = sc->read_data(card);
> }
> + trace_sdbus_read(sdbus_name(sdbus), value);
>
> - return 0;
> + return value;
> }
>
> bool sdbus_data_ready(SDBus *sdbus)
> diff --git a/hw/sd/trace-events b/hw/sd/trace-events
> index 78d8707669..ea2746c8b7 100644
> --- a/hw/sd/trace-events
> +++ b/hw/sd/trace-events
> @@ -1,5 +1,10 @@
> # See docs/devel/tracing.txt for syntax documentation.
>
> +# hw/sd/core.c
> +sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
> +sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
> +sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x"
> +
> # hw/sd/sdhci.c
> sdhci_set_inserted(const char *level) "card state changed: %s"
> sdhci_send_command(uint8_t cmd, uint32_t arg) "CMD%02u ARG[0x%08x]"
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence)
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
@ 2018-01-23 22:37 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> [based on a patch from Alistair Francis <alistair.francis@xilinx.com>
> from qemu/xilinx tag xilinx-v2015.2]
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> hw/sd/sdhci-internal.h | 10 ++++++++++
> include/hw/sd/sdhci.h | 1 +
> hw/sd/sdhci.c | 22 +++++++++++++++++++---
> 3 files changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
> index 9111f6856a..e7cbea297f 100644
> --- a/hw/sd/sdhci-internal.h
> +++ b/hw/sd/sdhci-internal.h
> @@ -184,6 +184,16 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1);
> FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1);
> FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
>
> +/* Host Control Register 2 (since v3) */
> +#define SDHC_HOSTCTL2 0x3E
> +FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
> +FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
> +FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
> +
> /* HWInit Capabilities Register 0x05E80080 */
> #define SDHC_CAPAB 0x40
> FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> index 5af9e0dc5a..0fff941a98 100644
> --- a/include/hw/sd/sdhci.h
> +++ b/include/hw/sd/sdhci.h
> @@ -71,6 +71,7 @@ typedef struct SDHCIState {
> uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
> uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
> uint16_t acmd12errsts; /* Auto CMD12 error status register */
> + uint16_t hostctl2; /* Host Control 2 */
> uint64_t admasysaddr; /* ADMA System Address Register */
>
> /* Read-only registers */
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 013c35e585..b7e69fbc22 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -408,14 +408,29 @@ static void sdhci_end_transfer(SDHCIState *s)
> static void sdhci_read_block_from_card(SDHCIState *s)
> {
> int index = 0;
> + uint8_t data;
> + const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
>
> if ((s->trnmod & SDHC_TRNS_MULTI) &&
> (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
> return;
> }
>
> - for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
> - s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
> + for (index = 0; index < blk_size; index++) {
> + data = sdbus_read_data(&s->sdbus);
> + if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
> + /* Device is not in tunning */
> + s->fifo_buffer[index] = data;
> + }
> + }
> +
> + if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
> + /* Device is in tunning */
> + s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
> + s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
> + s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
> + SDHC_DATA_INHIBIT);
> + goto read_done;
> }
>
> /* New data now available for READ through Buffer Port Register */
> @@ -440,6 +455,7 @@ static void sdhci_read_block_from_card(SDHCIState *s)
> }
> }
>
> +read_done:
> sdhci_update_irq(s);
> }
>
> @@ -1005,7 +1021,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
> ret = s->norintsigen | (s->errintsigen << 16);
> break;
> case SDHC_ACMD12ERRSTS:
> - ret = s->acmd12errsts;
> + ret = s->acmd12errsts | (s->hostctl2 << 16);
> break;
> case SDHC_CAPAB:
> ret = (uint32_t)s->capareg;
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
@ 2018-01-23 22:39 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> [based on a patch from Alistair Francis <alistair.francis@xilinx.com>
> from qemu/xilinx tag xilinx-v2015.2]
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> include/hw/sd/sd.h | 16 ++++++++++++++++
> include/hw/sd/sdhci.h | 1 +
> hw/sd/core.c | 13 +++++++++++++
> hw/sd/sd.c | 13 +++++++++++++
> hw/sd/sdhci.c | 12 +++++++++++-
> hw/sd/trace-events | 1 +
> 6 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
> index 96caefe373..f086679493 100644
> --- a/include/hw/sd/sd.h
> +++ b/include/hw/sd/sd.h
> @@ -55,6 +55,20 @@
> #define AKE_SEQ_ERROR (1 << 3)
> #define OCR_CCS_BITN 30
>
> +typedef enum {
> + SD_VOLTAGE_0_4V = 400, /* currently not supported */
> + SD_VOLTAGE_1_8V = 1800,
> + SD_VOLTAGE_3_0V = 3000,
> + SD_VOLTAGE_3_3V = 3300,
> +} sd_voltage_mv_t;
> +
> +typedef enum {
> + UHS_NOT_SUPPORTED = 0,
> + UHS_I = 1,
> + UHS_II = 2, /* currently not supported */
> + UHS_III = 3, /* currently not supported */
> +} sd_uhs_mode_t;
> +
> typedef enum {
> sd_none = -1,
> sd_bc = 0, /* broadcast -- no response */
> @@ -88,6 +102,7 @@ typedef struct {
> void (*write_data)(SDState *sd, uint8_t value);
> uint8_t (*read_data)(SDState *sd);
> bool (*data_ready)(SDState *sd);
> + void (*set_voltage)(SDState *sd, uint16_t millivolts);
> void (*enable)(SDState *sd, bool enable);
> bool (*get_inserted)(SDState *sd);
> bool (*get_readonly)(SDState *sd);
> @@ -134,6 +149,7 @@ void sd_enable(SDState *sd, bool enable);
> /* Functions to be used by qdevified callers (working via
> * an SDBus rather than directly with SDState)
> */
> +void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts);
> int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
> void sdbus_write_data(SDBus *sd, uint8_t value);
> uint8_t sdbus_read_data(SDBus *sd);
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> index 0fff941a98..06e3784e54 100644
> --- a/include/hw/sd/sdhci.h
> +++ b/include/hw/sd/sdhci.h
> @@ -93,6 +93,7 @@ typedef struct SDHCIState {
> /* Configurable properties */
> bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
> uint8_t sd_spec_version;
> + uint8_t uhs_mode;
> } SDHCIState;
>
> #define TYPE_PCI_SDHCI "sdhci-pci"
> diff --git a/hw/sd/core.c b/hw/sd/core.c
> index 498284f109..6d198ea775 100644
> --- a/hw/sd/core.c
> +++ b/hw/sd/core.c
> @@ -41,6 +41,19 @@ static SDState *get_card(SDBus *sdbus)
> return SD_CARD(kid->child);
> }
>
> +void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts)
> +{
> + SDState *card = get_card(sdbus);
> +
> + trace_sdbus_set_voltage(sdbus_name(sdbus), millivolts);
> + if (card) {
> + SDCardClass *sc = SD_CARD_GET_CLASS(card);
> +
> + assert(sc->set_voltage);
> + sc->set_voltage(card, millivolts);
> + }
> +}
> +
> int sdbus_do_command(SDBus *sdbus, SDRequest *req, uint8_t *response)
> {
> SDState *card = get_card(sdbus);
> diff --git a/hw/sd/sd.c b/hw/sd/sd.c
> index 35347a5bbc..609b2da14f 100644
> --- a/hw/sd/sd.c
> +++ b/hw/sd/sd.c
> @@ -128,6 +128,18 @@ struct SDState {
> bool enable;
> };
>
> +static void sd_set_voltage(SDState *sd, uint16_t millivolts)
> +{
> + switch (millivolts) {
> + case 3001 ... 3600: /* SD_VOLTAGE_3_3V */
> + case 2001 ... 3000: /* SD_VOLTAGE_3_0V */
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "SD card voltage not supported: %.3fV",
> + millivolts / 1000.f);
> + }
> +}
> +
> static void sd_set_mode(SDState *sd)
> {
> switch (sd->state) {
> @@ -1925,6 +1937,7 @@ static void sd_class_init(ObjectClass *klass, void *data)
> dc->reset = sd_reset;
> dc->bus_type = TYPE_SD_BUS;
>
> + sc->set_voltage = sd_set_voltage;
> sc->do_command = sd_do_command;
> sc->write_data = sd_write_data;
> sc->read_data = sd_read_data;
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index b7e69fbc22..aec6ca4d14 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1255,7 +1255,16 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
> sdhci_update_irq(s);
> break;
> case SDHC_ACMD12ERRSTS:
> - MASKED_WRITE(s->acmd12errsts, mask, value);
> + MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
> + if (s->uhs_mode >= UHS_I) {
> + MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
> +
> + if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
> + sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
> + } else {
> + sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
> + }
> + }
> break;
>
> case SDHC_CAPAB:
> @@ -1310,6 +1319,7 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
>
> #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
> DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
> + DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
> \
> /* Capabilities registers provide information on supported
> * features of this specific host controller implementation */ \
> diff --git a/hw/sd/trace-events b/hw/sd/trace-events
> index ea2746c8b7..84d2f398b1 100644
> --- a/hw/sd/trace-events
> +++ b/hw/sd/trace-events
> @@ -4,6 +4,7 @@
> sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
> sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
> sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x"
> +sdbus_set_voltage(const char *bus_name, uint16_t millivolts) "@%s %u (mV)"
>
> # hw/sd/sdhci.c
> sdhci_set_inserted(const char *level) "card state changed: %s"
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
@ 2018-01-23 22:44 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> [based on a patch from Alistair Francis <alistair.francis@xilinx.com>
> from qemu/xilinx tag xilinx-v2015.2]
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> hw/sd/sdhci-internal.h | 2 ++
> include/hw/sd/sd.h | 4 ++++
> hw/sd/core.c | 34 ++++++++++++++++++++++++++++++++++
> hw/sd/sd.c | 16 ++++++++++++++++
> hw/sd/sdhci.c | 4 ++++
> hw/sd/trace-events | 2 ++
> 6 files changed, 62 insertions(+)
>
> diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
> index e7cbea297f..514ecd4841 100644
> --- a/hw/sd/sdhci-internal.h
> +++ b/hw/sd/sdhci-internal.h
> @@ -82,6 +82,8 @@
> #define SDHC_CARD_PRESENT 0x00010000
> #define SDHC_CARD_DETECT 0x00040000
> #define SDHC_WRITE_PROTECT 0x00080000
> +FIELD(SDHC_PRNSTS, DAT_LVL, 20, 4);
> +FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1);
> #define TRANSFERRING_DATA(x) \
> ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE))
>
> diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
> index f086679493..bf1eb0713c 100644
> --- a/include/hw/sd/sd.h
> +++ b/include/hw/sd/sd.h
> @@ -103,6 +103,8 @@ typedef struct {
> uint8_t (*read_data)(SDState *sd);
> bool (*data_ready)(SDState *sd);
> void (*set_voltage)(SDState *sd, uint16_t millivolts);
> + uint8_t (*get_dat_lines)(SDState *sd);
> + bool (*get_cmd_line)(SDState *sd);
> void (*enable)(SDState *sd, bool enable);
> bool (*get_inserted)(SDState *sd);
> bool (*get_readonly)(SDState *sd);
> @@ -150,6 +152,8 @@ void sd_enable(SDState *sd, bool enable);
> * an SDBus rather than directly with SDState)
> */
> void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts);
> +uint8_t sdbus_get_dat_lines(SDBus *sdbus);
> +bool sdbus_get_cmd_line(SDBus *sdbus);
> int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
> void sdbus_write_data(SDBus *sd, uint8_t value);
> uint8_t sdbus_read_data(SDBus *sd);
> diff --git a/hw/sd/core.c b/hw/sd/core.c
> index 6d198ea775..3c6eae6c88 100644
> --- a/hw/sd/core.c
> +++ b/hw/sd/core.c
> @@ -41,6 +41,40 @@ static SDState *get_card(SDBus *sdbus)
> return SD_CARD(kid->child);
> }
>
> +uint8_t sdbus_get_dat_lines(SDBus *sdbus)
> +{
> + SDState *slave = get_card(sdbus);
> + uint8_t dat_lines = 0b1111; /* 4 bit bus width */
> +
> + if (slave) {
> + SDCardClass *sc = SD_CARD_GET_CLASS(slave);
> +
> + if (sc->get_dat_lines) {
> + dat_lines = sc->get_dat_lines(slave);
> + }
> + }
> + trace_sdbus_get_dat_lines(sdbus_name(sdbus), dat_lines);
> +
> + return dat_lines;
> +}
> +
> +bool sdbus_get_cmd_line(SDBus *sdbus)
> +{
> + SDState *slave = get_card(sdbus);
> + bool cmd_line = true;
> +
> + if (slave) {
> + SDCardClass *sc = SD_CARD_GET_CLASS(slave);
> +
> + if (sc->get_cmd_line) {
> + cmd_line = sc->get_cmd_line(slave);
> + }
> + }
> + trace_sdbus_get_cmd_line(sdbus_name(sdbus), cmd_line);
> +
> + return cmd_line;
> +}
> +
> void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts)
> {
> SDState *card = get_card(sdbus);
> diff --git a/hw/sd/sd.c b/hw/sd/sd.c
> index 609b2da14f..ab9be561d2 100644
> --- a/hw/sd/sd.c
> +++ b/hw/sd/sd.c
> @@ -126,8 +126,20 @@ struct SDState {
> BlockBackend *blk;
>
> bool enable;
> + uint8_t dat_lines;
> + bool cmd_line;
> };
>
> +static uint8_t sd_get_dat_lines(SDState *sd)
> +{
> + return sd->enable ? sd->dat_lines : 0;
> +}
> +
> +static bool sd_get_cmd_line(SDState *sd)
> +{
> + return sd->enable ? sd->cmd_line : false;
> +}
> +
> static void sd_set_voltage(SDState *sd, uint16_t millivolts)
> {
> switch (millivolts) {
> @@ -457,6 +469,8 @@ static void sd_reset(DeviceState *dev)
> sd->blk_len = 0x200;
> sd->pwd_len = 0;
> sd->expecting_acmd = false;
> + sd->dat_lines = 0xf;
> + sd->cmd_line = true;
> sd->multi_blk_cnt = 0;
> }
>
> @@ -1938,6 +1952,8 @@ static void sd_class_init(ObjectClass *klass, void *data)
> dc->bus_type = TYPE_SD_BUS;
>
> sc->set_voltage = sd_set_voltage;
> + sc->get_dat_lines = sd_get_dat_lines;
> + sc->get_cmd_line = sd_get_cmd_line;
> sc->do_command = sd_do_command;
> sc->write_data = sd_write_data;
> sc->read_data = sd_read_data;
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index aec6ca4d14..b7fb262750 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1003,6 +1003,10 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
> break;
> case SDHC_PRNSTS:
> ret = s->prnsts;
> + ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
> + sdbus_get_dat_lines(&s->sdbus));
> + ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
> + sdbus_get_cmd_line(&s->sdbus));
> break;
> case SDHC_HOSTCTL:
> ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
> diff --git a/hw/sd/trace-events b/hw/sd/trace-events
> index 84d2f398b1..0f8536db32 100644
> --- a/hw/sd/trace-events
> +++ b/hw/sd/trace-events
> @@ -5,6 +5,8 @@ sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s
> sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
> sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x"
> sdbus_set_voltage(const char *bus_name, uint16_t millivolts) "@%s %u (mV)"
> +sdbus_get_dat_lines(const char *bus_name, uint8_t dat_lines) "@%s dat_lines: %u"
> +sdbus_get_cmd_line(const char *bus_name, bool cmd_line) "@%s cmd_line: %u"
>
> # hw/sd/sdhci.c
> sdhci_set_inserted(const char *level) "card state changed: %s"
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
@ 2018-01-23 22:45 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu, open list:ARM
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/arm/bcm2835_peripherals.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
> index 12e0dd11af..0570cc4ad3 100644
> --- a/hw/arm/bcm2835_peripherals.c
> +++ b/hw/arm/bcm2835_peripherals.c
> @@ -254,14 +254,19 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->peri_mr, RNG_OFFSET,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));
>
> - /* Extended Mass Media Controller */
> - object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
> - &err);
> - if (err) {
> - error_propagate(errp, err);
> - return;
> - }
> -
> + /* Extended Mass Media Controller
> + *
> + * Compatible with:
> + * - SD Host Controller Specification Version 3.0 Draft 1.0
> + * - SDIO Specification Version 3.0
> + * - MMC Specification Version 4.4
> + *
> + * For the exact details please refer to the Arasan documentation:
> + * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf ¯\_(ツ)_/¯
I don't think we need the shrugging face in the comments.
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> + */
> + object_property_set_uint(OBJECT(&s->sdhci), 3, "sd-spec-version", &err);
> + object_property_set_uint(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
> + &err);
> object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk",
> &err);
> if (err) {
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
@ 2018-01-23 22:45 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu, open list:ARM
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> following the datasheet.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> hw/arm/bcm2835_peripherals.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
> index 0570cc4ad3..6b86a99b14 100644
> --- a/hw/arm/bcm2835_peripherals.c
> +++ b/hw/arm/bcm2835_peripherals.c
> @@ -19,7 +19,7 @@
> #define BCM2835_VC_PERI_BASE 0x7e000000
>
> /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
> -#define BCM2835_SDHC_CAPAREG 0x52034b4
> +#define BCM2835_SDHC_CAPAREG 0x52134b4
>
> static void bcm2835_peripherals_init(Object *obj)
> {
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 09/14] hw/arm/fsl-imx6: implement SDHCI Spec. v3
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
@ 2018-01-23 22:46 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu, open list:ARM
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> various FreeBSD console output from google search show this register having
> a value of 0x0377c800.
>
> hw/arm/fsl-imx6.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
> index b0d4088290..1f4607f206 100644
> --- a/hw/arm/fsl-imx6.c
> +++ b/hw/arm/fsl-imx6.c
> @@ -27,6 +27,8 @@
> #include "chardev/char.h"
> #include "qemu/error-report.h"
>
> +#define IMX6_ESDHC_CAPABILITIES 0x057834b4
> +
> #define NAME_SIZE 20
>
> static void fsl_imx6_init(Object *obj)
> @@ -348,6 +350,11 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
> { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
> };
>
> + /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
> + object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
> + &err);
> + object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
> + "capareg", &err);
> object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
> if (err) {
> error_propagate(errp, err);
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 11/14] hw/arm/xilinx_zynqmp: enable the UHS-I mode
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 11/14] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
@ 2018-01-23 22:47 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:47 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu,
open list:Xilinx ZynqMP, Edgar E. Iglesias
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> see the Xilinx datasheet "UG1085" (v1.7)
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> hw/arm/xlnx-zynqmp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 33d5fe53d8..bb4265a4ce 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -394,6 +394,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> */
> object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
> object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
> + object_property_set_uint(sdhci, UHS_I, "uhs", &err);
> object_property_set_bool(sdhci, true, "realized", &err);
> if (err) {
> error_propagate(errp, err);
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH v8 10/14] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
@ 2018-01-23 22:48 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2018-01-23 22:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, Peter Maydell, Edgar E . Iglesias,
Prasad J Pandit, Peter Crosthwaite, Andrey Smirnov,
qemu-devel@nongnu.org Developers, Sai Pavan Boddu,
open list:Xilinx ZynqMP, Edgar E. Iglesias
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> checking Xilinx datasheet "UG1085" (v1.7)
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> hw/arm/xlnx-zynqmp.c | 29 ++++++++++++++++++-----------
> 1 file changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 325642058b..33d5fe53d8 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -50,6 +50,8 @@
> #define DPDMA_ADDR 0xfd4c0000
> #define DPDMA_IRQ 116
>
> +#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
> +
> static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
> 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
> };
> @@ -381,22 +383,27 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
> - char *bus_name;
> -
> - object_property_set_bool(OBJECT(&s->sdhci[i]), true,
> - "realized", &err);
> + char *bus_name = g_strdup_printf("sd-bus%d", i);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
> + Object *sdhci = OBJECT(&s->sdhci[i]);
> +
> + /* Compatible with:
> + * - SD Host Controller Specification Version 3.00
> + * - SDIO Specification Version 3.0
> + * - eMMC Specification Version 4.51
> + */
> + object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
> + object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
> + object_property_set_bool(sdhci, true, "realized", &err);
> if (err) {
> error_propagate(errp, err);
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
> - sdhci_addr[i]);
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
> - gic_spi[sdhci_intr[i]]);
> + sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
> + sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
> +
> /* Alias controller SD bus to the SoC itself */
> - bus_name = g_strdup_printf("sd-bus%d", i);
> - object_property_add_alias(OBJECT(s), bus_name,
> - OBJECT(&s->sdhci[i]), "sd-bus",
> + object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
> &error_abort);
> g_free(bus_name);
> }
> --
> 2.15.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-01-23 22:49 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-23 3:06 [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3) Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 01/14] sdhci: add support for v3 capabilities Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 02/14] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
2018-01-23 22:37 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events Philippe Mathieu-Daudé
2018-01-23 22:34 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
2018-01-23 22:39 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
2018-01-23 22:44 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
2018-01-23 22:45 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
2018-01-23 22:45 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 09/14] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
2018-01-23 22:46 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 10/14] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
2018-01-23 22:48 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 11/14] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
2018-01-23 22:47 ` Alistair Francis
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 12/14] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
2018-01-23 3:06 ` [Qemu-devel] [PATCH v8 13/14] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
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