From: Philippe Cornu <philippe.cornu@st.com>
To: Archit Taneja <architt@codeaurora.org>,
Andrzej Hajda <a.hajda@samsung.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
David Airlie <airlied@linux.ie>,
Philippe Cornu <philippe.cornu@st.com>,
Brian Norris <briannorris@chromium.org>,
Benjamin Gaignard <benjamin.gaignard@linaro.org>,
Bhumika Goyal <bhumirks@gmail.com>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
"Sandy Huang" <hjc@rock-chips.com>,
Heiko Stubner <heiko@sntech.de>,
<linux-arm-kernel@lists.infradead.org>,
<linux-rockchip@lists.infradead.org>
Cc: Yannick Fertre <yannick.fertre@st.com>,
Vincent Abriou <vincent.abriou@st.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
"Maxime Coquelin" <mcoquelin.stm32@gmail.com>,
Ludovic Barre <ludovic.barre@st.com>,
Mickael Reulier <mickael.reulier@st.com>
Subject: [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock
Date: Tue, 23 Jan 2018 18:08:06 +0100 [thread overview]
Message-ID: <20180123170806.5282-1-philippe.cornu@st.com> (raw)
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependant).
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Philippe Cornu <philippe.cornu@st.com>
---
Changes in v3: Simplify px_clk probing thanks to Andrzej Hajda comments
Changes in v2: Improve px_clk probing in case of ENOENT dt returned value
(thanks to Philipp Zabel & Andrzej Hajda comments)
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index ed8af32f8e52..9fb35385c348 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -217,6 +217,7 @@ struct dw_mipi_dsi {
void __iomem *base;
struct clk *pclk;
+ struct clk *px_clk;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -703,24 +704,28 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
void *priv_data = dsi->plat_data->priv_data;
+ struct drm_display_mode px_clk_mode = *mode;
int ret;
clk_prepare_enable(dsi->pclk);
- ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
+ if (dsi->px_clk)
+ px_clk_mode.clock = clk_get_rate(dsi->px_clk) / 1000;
+
+ ret = phy_ops->get_lane_mbps(priv_data, &px_clk_mode, dsi->mode_flags,
dsi->lanes, dsi->format, &dsi->lane_mbps);
if (ret)
DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
- dw_mipi_dsi_dpi_config(dsi, mode);
+ dw_mipi_dsi_dpi_config(dsi, &px_clk_mode);
dw_mipi_dsi_packet_handler_config(dsi);
dw_mipi_dsi_video_mode_config(dsi);
- dw_mipi_dsi_video_packet_config(dsi, mode);
+ dw_mipi_dsi_video_packet_config(dsi, &px_clk_mode);
dw_mipi_dsi_command_mode_config(dsi);
- dw_mipi_dsi_line_timer_config(dsi, mode);
- dw_mipi_dsi_vertical_timing_config(dsi, mode);
+ dw_mipi_dsi_line_timer_config(dsi, &px_clk_mode);
+ dw_mipi_dsi_vertical_timing_config(dsi, &px_clk_mode);
dw_mipi_dsi_dphy_init(dsi);
dw_mipi_dsi_dphy_timing_config(dsi);
@@ -734,7 +739,7 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
dw_mipi_dsi_dphy_enable(dsi);
- dw_mipi_dsi_wait_for_two_frames(mode);
+ dw_mipi_dsi_wait_for_two_frames(&px_clk_mode);
/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
dw_mipi_dsi_set_mode(dsi, 0);
@@ -828,6 +833,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
return ERR_PTR(ret);
}
+ dsi->px_clk = devm_clk_get(dev, "px_clk");
+ if (IS_ERR(dsi->px_clk)) {
+ ret = PTR_ERR(dsi->px_clk);
+ if (ret != ENOENT)
+ dev_err(dev, "Unable to get opt. px_clk: %d\n", ret);
+ dsi->px_clk = NULL;
+ }
+
/*
* Note that the reset was not defined in the initial device tree, so
* we have to be prepared for it not being found.
--
2.15.1
WARNING: multiple messages have this Message-ID (diff)
From: Philippe Cornu <philippe.cornu@st.com>
To: Archit Taneja <architt@codeaurora.org>,
Andrzej Hajda <a.hajda@samsung.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
David Airlie <airlied@linux.ie>,
Philippe Cornu <philippe.cornu@st.com>,
Brian Norris <briannorris@chromium.org>,
Benjamin Gaignard <benjamin.gaignard@linaro.org>,
Bhumika Goyal <bhumirks@gmail.com>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Sandy Huang <hjc@rock-chips.com>, Heiko Stubner <heiko@sntech.de>,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Cc: Alexandre Torgue <alexandre.torgue@st.com>,
Yannick Fertre <yannick.fertre@st.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Mickael Reulier <mickael.reulier@st.com>,
Vincent Abriou <vincent.abriou@st.com>,
Ludovic Barre <ludovic.barre@st.com>
Subject: [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock
Date: Tue, 23 Jan 2018 18:08:06 +0100 [thread overview]
Message-ID: <20180123170806.5282-1-philippe.cornu@st.com> (raw)
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependant).
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Philippe Cornu <philippe.cornu@st.com>
---
Changes in v3: Simplify px_clk probing thanks to Andrzej Hajda comments
Changes in v2: Improve px_clk probing in case of ENOENT dt returned value
(thanks to Philipp Zabel & Andrzej Hajda comments)
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index ed8af32f8e52..9fb35385c348 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -217,6 +217,7 @@ struct dw_mipi_dsi {
void __iomem *base;
struct clk *pclk;
+ struct clk *px_clk;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -703,24 +704,28 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
void *priv_data = dsi->plat_data->priv_data;
+ struct drm_display_mode px_clk_mode = *mode;
int ret;
clk_prepare_enable(dsi->pclk);
- ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
+ if (dsi->px_clk)
+ px_clk_mode.clock = clk_get_rate(dsi->px_clk) / 1000;
+
+ ret = phy_ops->get_lane_mbps(priv_data, &px_clk_mode, dsi->mode_flags,
dsi->lanes, dsi->format, &dsi->lane_mbps);
if (ret)
DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
- dw_mipi_dsi_dpi_config(dsi, mode);
+ dw_mipi_dsi_dpi_config(dsi, &px_clk_mode);
dw_mipi_dsi_packet_handler_config(dsi);
dw_mipi_dsi_video_mode_config(dsi);
- dw_mipi_dsi_video_packet_config(dsi, mode);
+ dw_mipi_dsi_video_packet_config(dsi, &px_clk_mode);
dw_mipi_dsi_command_mode_config(dsi);
- dw_mipi_dsi_line_timer_config(dsi, mode);
- dw_mipi_dsi_vertical_timing_config(dsi, mode);
+ dw_mipi_dsi_line_timer_config(dsi, &px_clk_mode);
+ dw_mipi_dsi_vertical_timing_config(dsi, &px_clk_mode);
dw_mipi_dsi_dphy_init(dsi);
dw_mipi_dsi_dphy_timing_config(dsi);
@@ -734,7 +739,7 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
dw_mipi_dsi_dphy_enable(dsi);
- dw_mipi_dsi_wait_for_two_frames(mode);
+ dw_mipi_dsi_wait_for_two_frames(&px_clk_mode);
/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
dw_mipi_dsi_set_mode(dsi, 0);
@@ -828,6 +833,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
return ERR_PTR(ret);
}
+ dsi->px_clk = devm_clk_get(dev, "px_clk");
+ if (IS_ERR(dsi->px_clk)) {
+ ret = PTR_ERR(dsi->px_clk);
+ if (ret != ENOENT)
+ dev_err(dev, "Unable to get opt. px_clk: %d\n", ret);
+ dsi->px_clk = NULL;
+ }
+
/*
* Note that the reset was not defined in the initial device tree, so
* we have to be prepared for it not being found.
--
2.15.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: philippe.cornu@st.com (Philippe Cornu)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock
Date: Tue, 23 Jan 2018 18:08:06 +0100 [thread overview]
Message-ID: <20180123170806.5282-1-philippe.cornu@st.com> (raw)
The pixel clock is optional. When available, it offers a better
preciseness for timing computations and allows to reduce the extra dsi
bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependant).
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Philippe Cornu <philippe.cornu@st.com>
---
Changes in v3: Simplify px_clk probing thanks to Andrzej Hajda comments
Changes in v2: Improve px_clk probing in case of ENOENT dt returned value
(thanks to Philipp Zabel & Andrzej Hajda comments)
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index ed8af32f8e52..9fb35385c348 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -217,6 +217,7 @@ struct dw_mipi_dsi {
void __iomem *base;
struct clk *pclk;
+ struct clk *px_clk;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -703,24 +704,28 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
void *priv_data = dsi->plat_data->priv_data;
+ struct drm_display_mode px_clk_mode = *mode;
int ret;
clk_prepare_enable(dsi->pclk);
- ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
+ if (dsi->px_clk)
+ px_clk_mode.clock = clk_get_rate(dsi->px_clk) / 1000;
+
+ ret = phy_ops->get_lane_mbps(priv_data, &px_clk_mode, dsi->mode_flags,
dsi->lanes, dsi->format, &dsi->lane_mbps);
if (ret)
DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
- dw_mipi_dsi_dpi_config(dsi, mode);
+ dw_mipi_dsi_dpi_config(dsi, &px_clk_mode);
dw_mipi_dsi_packet_handler_config(dsi);
dw_mipi_dsi_video_mode_config(dsi);
- dw_mipi_dsi_video_packet_config(dsi, mode);
+ dw_mipi_dsi_video_packet_config(dsi, &px_clk_mode);
dw_mipi_dsi_command_mode_config(dsi);
- dw_mipi_dsi_line_timer_config(dsi, mode);
- dw_mipi_dsi_vertical_timing_config(dsi, mode);
+ dw_mipi_dsi_line_timer_config(dsi, &px_clk_mode);
+ dw_mipi_dsi_vertical_timing_config(dsi, &px_clk_mode);
dw_mipi_dsi_dphy_init(dsi);
dw_mipi_dsi_dphy_timing_config(dsi);
@@ -734,7 +739,7 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
dw_mipi_dsi_dphy_enable(dsi);
- dw_mipi_dsi_wait_for_two_frames(mode);
+ dw_mipi_dsi_wait_for_two_frames(&px_clk_mode);
/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
dw_mipi_dsi_set_mode(dsi, 0);
@@ -828,6 +833,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
return ERR_PTR(ret);
}
+ dsi->px_clk = devm_clk_get(dev, "px_clk");
+ if (IS_ERR(dsi->px_clk)) {
+ ret = PTR_ERR(dsi->px_clk);
+ if (ret != ENOENT)
+ dev_err(dev, "Unable to get opt. px_clk: %d\n", ret);
+ dsi->px_clk = NULL;
+ }
+
/*
* Note that the reset was not defined in the initial device tree, so
* we have to be prepared for it not being found.
--
2.15.1
next reply other threads:[~2018-01-23 17:09 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-23 17:08 Philippe Cornu [this message]
2018-01-23 17:08 ` [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock Philippe Cornu
2018-01-23 17:08 ` Philippe Cornu
2018-01-23 20:49 ` Brian Norris
2018-01-23 20:49 ` Brian Norris
2018-01-23 20:49 ` Brian Norris
2018-01-24 9:24 ` Philippe CORNU
2018-01-24 9:24 ` Philippe CORNU
2018-01-24 9:24 ` Philippe CORNU
2018-01-24 18:09 ` Brian Norris
2018-01-24 18:09 ` Brian Norris
2018-01-24 18:09 ` Brian Norris
2018-01-25 11:34 ` Philippe CORNU
2018-01-25 11:34 ` Philippe CORNU
2018-01-25 11:34 ` Philippe CORNU
2018-01-25 16:06 ` Philippe CORNU
2018-01-25 16:06 ` Philippe CORNU
2018-01-25 16:06 ` Philippe CORNU
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180123170806.5282-1-philippe.cornu@st.com \
--to=philippe.cornu@st.com \
--cc=Laurent.pinchart@ideasonboard.com \
--cc=a.hajda@samsung.com \
--cc=airlied@linux.ie \
--cc=alexandre.torgue@st.com \
--cc=architt@codeaurora.org \
--cc=benjamin.gaignard@linaro.org \
--cc=bhumirks@gmail.com \
--cc=briannorris@chromium.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=heiko@sntech.de \
--cc=hjc@rock-chips.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=ludovic.barre@st.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=mickael.reulier@st.com \
--cc=vincent.abriou@st.com \
--cc=yannick.fertre@st.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.