[PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Rafael Antognolli]

Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
indirect context wa bb.

References: HSD#1939868

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 51e61b04a555..fd7e7ffde570 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1366,6 +1366,25 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
 	return batch;
 }
 
+static u32 *gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
+{
+	int i;
+
+	/* WaPipeControlBefore3DStateSamplePattern: cnl */
+	batch = gen8_emit_pipe_control(batch,
+				       PIPE_CONTROL_CS_STALL,
+				       0);
+	for (i = 0; i < 8; i++)
+		*batch++ = MI_NOOP;
+
+	/* Pad to end of cacheline */
+	while ((unsigned long)batch % CACHELINE_BYTES)
+		*batch++ = MI_NOOP;
+
+	return batch;
+}
+
+
 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
 
 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
@@ -1419,7 +1438,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 
 	switch (INTEL_GEN(engine->i915)) {
 	case 10:
-		return 0;
+		wa_bb_fn[0] = gen10_init_indirectctx_bb;
+		wa_bb_fn[1] = NULL;
+		break;
 	case 9:
 		wa_bb_fn[0] = gen9_init_indirectctx_bb;
 		wa_bb_fn[1] = NULL;
-- 
2.14.3

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✓ Fi.CI.BAT: success for drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern
URL   : https://patchwork.freedesktop.org/series/37148/
State : success

== Summary ==

Series 37148v1 drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern
https://patchwork.freedesktop.org/api/1.0/series/37148/revisions/1/mbox/

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test gem_ringfill:
        Subgroup basic-default-hang:
                pass       -> DMESG-WARN (fi-pnv-d510) fdo#101600

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:423s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:429s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:494s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:478s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:484s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:459s
fi-cnl-y2        total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:528s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:280s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:515s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:394s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:400s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:412s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:458s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:411s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:498s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:459s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:501s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:578s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:431s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:505s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:536s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:495s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:478s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:415s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:529s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:394s
Blacklisted hosts:
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:568s
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:475s

804d087465e907accca7a2631d8a9485729b9a48 drm-tip: 2018y-01m-25d-18h-22m-16s UTC integration manifest
ad0a749db7f8 drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7786/issues.html
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✗ Fi.CI.IGT: failure for drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern
URL   : https://patchwork.freedesktop.org/series/37148/
State : failure

== Summary ==

Test gem_softpin:
        Subgroup noreloc-s4:
                fail       -> SKIP       (shard-snb) fdo#103375
Test kms_flip:
        Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-rte:
                pass       -> FAIL       (shard-apl) fdo#101623 +1
Test perf:
        Subgroup enable-disable:
                pass       -> FAIL       (shard-apl) fdo#103715
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252
Test kms_plane_lowres:
        Subgroup pipe-b-tiling-x:
                pass       -> FAIL       (shard-apl)
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apl        total:2758 pass:1703 dwarn:1   dfail:0   fail:24  skip:1029 time:12435s
shard-hsw        total:2838 pass:1733 dwarn:1   dfail:0   fail:13  skip:1090 time:12071s
shard-snb        total:2838 pass:1329 dwarn:1   dfail:0   fail:10  skip:1498 time:6600s
Blacklisted hosts:
shard-kbl        total:2771 pass:1823 dwarn:6   dfail:0   fail:21  skip:920 time:9432s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7786/shards.html
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Re: [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Chris Wilson]

Quoting Rafael Antognolli (2018-01-26 01:26:34)
> Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> indirect context wa bb.

14 MI_NOOPS following? That isn't what you wrote in the code, but the
main thing you haven't explained is why. A normal batch will already
have a flush in its setup, but more to the point would be the only
reason this is required is because of an implicit 3DSTATE inside the
context image on preemption. Right? Otherwise it seems to be a purely
userspace problem.
-Chris
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Re: [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Rafael Antognolli]

On Fri, Jan 26, 2018 at 08:23:13AM +0000, Chris Wilson wrote:
> Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> > indirect context wa bb.
> 
> 14 MI_NOOPS following? That isn't what you wrote in the code, but the

Agreed, sorry. The workarounds says:

0x7a000004 0x00100000 + 14 dwords of 0. I counted 6 dwords from
gen8_emit_pipe_control() and figured "just 8 more to 14". I think I had
it right on my first version of this patch, but...

> main thing you haven't explained is why. A normal batch will already
> have a flush in its setup, but more to the point would be the only
> reason this is required is because of an implicit 3DSTATE inside the
> context image on preemption. Right? Otherwise it seems to be a purely
> userspace problem.

This is the text from the workaround:

"This bug can be hit on a context restore.  To avoid the issue the
following must be programmed by SW to ensure the engine is idle prior to
programming 3DSTATE_SAMPLE_PATTERN:

With RS context enabled: 0x21c8 = 0x000085c0

With RS context disabled:0x21c8 = 0x00001ac0

The above program specifes the offset to insert driver programmed
commands

0x21c4[31:6] = 0x<Addresses>

0x21c4[5:0] = 0x<N>

N=Size of CL needed to fit Workaround

The above programming is the GGTT address of the driver programmed
commands and the size(# of CL) to execute.

The address above needs to be a GGTT address and contain a pipe control
with CS stall(0x7a000004 0x00100000 0x00000000 0x00000000)followed by
12DW’s of NOOP(0x00000000)"

Since it needs to be in a GGTT address, and it's specifically talking
about the Indirect Context Pointer, we figured it should be in the
kernel. I can update the commit message with the above text if it helps.

I originally implemented this trying to fix my GPU hang, but it turns
out the issue was something else and this commit doesn't help at all.
Still, I see no reason to not have it there just in case it prevent any
future hangs...

Rafael
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Re: [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Rafael Antognolli]

On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote:
> On Fri, Jan 26, 2018 at 08:23:13AM +0000, Chris Wilson wrote:
> > Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> > > indirect context wa bb.
> > 
> > 14 MI_NOOPS following? That isn't what you wrote in the code, but the
> 
> Agreed, sorry. The workarounds says:
> 
> 0x7a000004 0x00100000 + 14 dwords of 0. I counted 6 dwords from
> gen8_emit_pipe_control() and figured "just 8 more to 14". I think I had
> it right on my first version of this patch, but...
> 
> > main thing you haven't explained is why. A normal batch will already
> > have a flush in its setup, but more to the point would be the only
> > reason this is required is because of an implicit 3DSTATE inside the
> > context image on preemption. Right? Otherwise it seems to be a purely
> > userspace problem.
> 
> This is the text from the workaround:
> 
> "This bug can be hit on a context restore.  To avoid the issue the
> following must be programmed by SW to ensure the engine is idle prior to
> programming 3DSTATE_SAMPLE_PATTERN:
> 
> With RS context enabled: 0x21c8 = 0x000085c0
> 
> With RS context disabled:0x21c8 = 0x00001ac0
> 
> The above program specifes the offset to insert driver programmed
> commands
> 
> 0x21c4[31:6] = 0x<Addresses>
> 
> 0x21c4[5:0] = 0x<N>
> 
> N=Size of CL needed to fit Workaround
> 
> The above programming is the GGTT address of the driver programmed
> commands and the size(# of CL) to execute.
> 
> The address above needs to be a GGTT address and contain a pipe control
> with CS stall(0x7a000004 0x00100000 0x00000000 0x00000000)followed by
> 12DW’s of NOOP(0x00000000)"
> 
> Since it needs to be in a GGTT address, and it's specifically talking
> about the Indirect Context Pointer, we figured it should be in the
> kernel. I can update the commit message with the above text if it helps.
> 
> I originally implemented this trying to fix my GPU hang, but it turns
> out the issue was something else and this commit doesn't help at all.
> Still, I see no reason to not have it there just in case it prevent any
> future hangs...

Oh, and this workaround is actually a little longer, and there is a part
that describe a similar PIPE_CONTROL before 3DSTATE_SAMPLE_PATTERN. That
part is already implemented in userspace.
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Re: [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Chris Wilson]

Quoting Rafael Antognolli (2018-01-26 17:58:29)
> On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote:
> > On Fri, Jan 26, 2018 at 08:23:13AM +0000, Chris Wilson wrote:
> > > Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > > > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> > > > indirect context wa bb.
> > > 
> > > 14 MI_NOOPS following? That isn't what you wrote in the code, but the
> > 
> > Agreed, sorry. The workarounds says:
> > 
> > 0x7a000004 0x00100000 + 14 dwords of 0. I counted 6 dwords from
> > gen8_emit_pipe_control() and figured "just 8 more to 14". I think I had
> > it right on my first version of this patch, but...
> > 
> > > main thing you haven't explained is why. A normal batch will already
> > > have a flush in its setup, but more to the point would be the only
> > > reason this is required is because of an implicit 3DSTATE inside the
> > > context image on preemption. Right? Otherwise it seems to be a purely
> > > userspace problem.
> > 
> > This is the text from the workaround:
> > 
> > "This bug can be hit on a context restore.  To avoid the issue the
> > following must be programmed by SW to ensure the engine is idle prior to
> > programming 3DSTATE_SAMPLE_PATTERN:
> > 
> > With RS context enabled: 0x21c8 = 0x000085c0
> > 
> > With RS context disabled:0x21c8 = 0x00001ac0
> > 
> > The above program specifes the offset to insert driver programmed
> > commands
> > 
> > 0x21c4[31:6] = 0x<Addresses>
> > 
> > 0x21c4[5:0] = 0x<N>
> > 
> > N=Size of CL needed to fit Workaround
> > 
> > The above programming is the GGTT address of the driver programmed
> > commands and the size(# of CL) to execute.
> > 
> > The address above needs to be a GGTT address and contain a pipe control
> > with CS stall(0x7a000004 0x00100000 0x00000000 0x00000000)followed by
> > 12DW’s of NOOP(0x00000000)"
> > 
> > Since it needs to be in a GGTT address, and it's specifically talking
> > about the Indirect Context Pointer, we figured it should be in the
> > kernel. I can update the commit message with the above text if it helps.
> > 
> > I originally implemented this trying to fix my GPU hang, but it turns
> > out the issue was something else and this commit doesn't help at all.
> > Still, I see no reason to not have it there just in case it prevent any
> > future hangs...
> 
> Oh, and this workaround is actually a little longer, and there is a part
> that describe a similar PIPE_CONTROL before 3DSTATE_SAMPLE_PATTERN. That
> part is already implemented in userspace.

Cool, I really just wanted confirmation that it was indeed required
before the context switch. Hence justifying placement in the
indirect_ctx bb, and explaining why it's not just a regular pre-batch
flush. Please do try and distill as much as the workaround
note into the changelog and a reminder inside the code; especially the
rationale on why it's in the indirect ctx bb.
-Chris
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