* [PATCH 0/9] ICL mergeable patches
@ 2018-01-30 13:49 Paulo Zanoni
2018-01-30 13:49 ` [PATCH 1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
` (11 more replies)
0 siblings, 12 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
These patches were part of the other ICL series that arrived on the
list a few days ago, they already received public reviews. They should
be good to go, but let's see what the CI system has to say about them
first.
James Ausmus (1):
drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
Kelvin Gardiner (1):
drm/i915/icl: Set graphics mode register for gen11
Mahesh Kumar (5):
drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
drm/i915/icl: Do not fix dbuf block size to 512
drm/i915/icl: Fail flip if ddb allocated are less than min display
buffer needed
drm/i915/icl: NV12 y-plane ddb is not in same plane
drm/i915/icl: Introduce MBus related registers
Paulo Zanoni (2):
drm/i915/gen11: fix the SAGV block time for gen11
drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP
register
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 5 ++-
drivers/gpu/drm/i915/intel_lrc.c | 18 ++++++++--
drivers/gpu/drm/i915/intel_pm.c | 69 +++++++++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
6 files changed, 112 insertions(+), 16 deletions(-)
--
2.14.3
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 2/9] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.
v2 (from Paulo):
- No need for a comment that says what the code already says.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1dbd40..11aac65d1543 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
- ddb_size -= 4; /* 4 blocks for bypass path allocation */
+ if (INTEL_GEN(dev_priv) < 11)
+ ddb_size -= 4; /* 4 blocks for bypass path allocation */
/*
* If the state doesn't change the active CRTC's, then there's
--
2.14.3
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/9] drm/i915/icl: Do not fix dbuf block size to 512
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
2018-01-30 13:49 ` [PATCH 1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 3/9] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2 (from Paulo):
- Make it compile.
- Fix a few coding style issues.
v3:
- Rebase on top of upstream patches
v4 (from Paulo):
- Bikeshed if statements (James).
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++-------
2 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 454d8f937fae..d93e784c3f14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1460,6 +1460,7 @@ struct skl_wm_params {
uint_fixed_16_16_t plane_blocks_per_line;
uint_fixed_16_16_t y_tile_minimum;
uint32_t linetime_us;
+ uint32_t dbuf_block_size;
};
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 11aac65d1543..985642cf1c9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
static uint_fixed_16_16_t
skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
- uint8_t cpp, uint32_t latency)
+ uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
{
uint32_t wm_intermediate_val;
uint_fixed_16_16_t ret;
@@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
return FP_16_16_MAX;
wm_intermediate_val = latency * pixel_rate * cpp;
- ret = div_fixed16(wm_intermediate_val, 1000 * 512);
+ ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
if (INTEL_GEN(dev_priv) >= 10)
ret = add_fixed16_u32(ret, 1);
@@ -4431,6 +4431,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+ wp->dbuf_block_size = 256;
+ else
+ wp->dbuf_block_size = 512;
+
if (drm_rotation_90_or_270(pstate->rotation)) {
switch (wp->cpp) {
@@ -4457,7 +4463,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_bytes_per_line = wp->width * wp->cpp;
if (wp->y_tiled) {
interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
- wp->y_min_scanlines, 512);
+ wp->y_min_scanlines,
+ wp->dbuf_block_size);
if (INTEL_GEN(dev_priv) >= 10)
interm_pbpl++;
@@ -4465,10 +4472,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
wp->y_min_scanlines);
} else if (wp->x_tiled && IS_GEN9(dev_priv)) {
- interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
+ interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+ wp->dbuf_block_size);
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
} else {
- interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
+ interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+ wp->dbuf_block_size) + 1;
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
}
@@ -4515,7 +4524,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
latency += 15;
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
- wp->cpp, latency);
+ wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
cstate->base.adjusted_mode.crtc_htotal,
latency,
@@ -4525,7 +4534,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
- 512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
+ wp->dbuf_block_size < 1) &&
+ (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
selected_result = method2;
else if (ddb_allocation >=
fixed16_to_u32_round_up(wp->plane_blocks_per_line))
--
2.14.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/9] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
2018-01-30 13:49 ` [PATCH 1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
2018-01-30 13:49 ` [PATCH 2/9] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 4/9] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes Since V2:
- Remove extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo):
- Coding style issue.
Changes since v5 (from Paulo):
- Do the final checks according to BSpec.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 985642cf1c9a..24421603e605 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4507,6 +4507,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+ uint32_t min_disp_buf_needed;
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
@@ -4565,7 +4566,31 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
- if (res_blocks >= ddb_allocation || res_lines > 31) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (wp->y_tiled) {
+ uint32_t extra_lines;
+ uint_fixed_16_16_t fp_min_disp_buf_needed;
+
+ if (res_lines % wp->y_min_scanlines == 0)
+ extra_lines = wp->y_min_scanlines;
+ else
+ extra_lines = wp->y_min_scanlines * 2 -
+ res_lines % wp->y_min_scanlines;
+
+ fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
+ extra_lines,
+ wp->plane_blocks_per_line);
+ min_disp_buf_needed = fixed16_to_u32_round_up(
+ fp_min_disp_buf_needed);
+ } else {
+ min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
+ }
+ } else {
+ min_disp_buf_needed = res_blocks;
+ }
+
+ if (res_blocks >= ddb_allocation || res_lines > 31 ||
+ min_disp_buf_needed >= ddb_allocation) {
*enabled = false;
/*
--
2.14.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/9] drm/i915/icl: NV12 y-plane ddb is not in same plane
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (2 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 3/9] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 5/9] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL.
This patch removes the PLANE_NV12_BUF_CFG write for ICL.
Changes Since V1:
- Improve commit message as per Paulo's comment
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 24421603e605..766f4fdd633b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4826,8 +4826,10 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
&ddb->plane[pipe][plane_id]);
- skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
- &ddb->y_plane[pipe][plane_id]);
+ if (INTEL_GEN(dev_priv) < 11)
+ skl_ddb_entry_write(dev_priv,
+ PLANE_NV12_BUF_CFG(pipe, plane_id),
+ &ddb->y_plane[pipe][plane_id]);
}
static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
--
2.14.3
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/9] drm/i915/icl: Introduce MBus related registers
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (3 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 4/9] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 6/9] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64933fd74cb6..9f1c4a6f6dd6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2648,6 +2648,31 @@ enum i915_power_well_id {
#define LM_FIFO_WATERMARK 0x0000001F
#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
+#define MBUS_ABOX_CTL _MMIO(0x45038)
+#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
+#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
+#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
+#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
+#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
+#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
+
+#define _PIPEA_MBUS_DBOX_CTL 0x7003C
+#define _PIPEB_MBUS_DBOX_CTL 0x7103C
+#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
+ _PIPEB_MBUS_DBOX_CTL)
+#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
+#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
+#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
+#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
+#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
+#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
+
+#define MBUS_UBOX_CTL _MMIO(0x4503C)
+#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
+#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
+
/* Make render/texture TLB fetches lower priorty than associated data
* fetches. This is not turned on by default
*/
--
2.14.3
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/9] drm/i915/gen11: fix the SAGV block time for gen11
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (4 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 5/9] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 7/9] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Paulo Zanoni
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 766f4fdd633b..6dc4677e6c3f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3694,11 +3694,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
struct intel_crtc_state *cstate;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
+ int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
+ if (IS_GEN9(dev_priv))
+ sagv_block_time_us = 30;
+ else if (IS_GEN10(dev_priv))
+ sagv_block_time_us = 20;
+ else
+ sagv_block_time_us = 10;
+
/*
* SKL+ workaround: bspec recommends we disable the SAGV when we have
* more then one pipe enabled
--
2.14.3
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 7/9] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (5 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 6/9] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 8/9] drm/i915/icl: Set graphics mode register for gen11 Paulo Zanoni
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: James Ausmus <james.ausmus@intel.com>
ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values. Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.
v2: No changes
v3: Change new definition name, drop comment (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_display.c | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f1c4a6f6dd6..05c57166eee3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6341,6 +6341,11 @@ enum {
#define _PLANE_CTL_3_A 0x70380
#define PLANE_CTL_ENABLE (1 << 31)
#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
#define PLANE_CTL_FORMAT_MASK (0xf << 24)
#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
@@ -6350,6 +6355,7 @@ enum {
#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
+#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 67e0ec4fb5e3..238bf7327fc5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8510,7 +8510,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
val = I915_READ(PLANE_CTL(pipe, plane_id));
- pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ if (INTEL_GEN(dev_priv) >= 11)
+ pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+ else
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
--
2.14.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 8/9] drm/i915/icl: Set graphics mode register for gen11
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (6 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 7/9] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 13:49 ` [PATCH 9/9] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register Paulo Zanoni
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Kelvin Gardiner <kelvin.gardiner@intel.com>
This patch clears a single bit. The bit is 0 by default but expected
not to be set. Explicitly clearing the bit in this patch is intended
to indicate some thinking has occurred, and that we want this bit
cleared and we are not just excepting the default value.
We also stop setting GFX_RUN_LIST_ENABLE, which is correct since that
bit is gone.
v2 (from Paulo): fix indentation.
v3: Changed GEN check to >= 11. Corrected author name.
v4 (from Paulo): improve commit message (Daniele).
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 18 ++++++++++++++++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05c57166eee3..3b457990b73c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2590,6 +2590,8 @@ enum i915_power_well_id {
#define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
#define GFX_FORWARD_VBLANK_COND (2<<5)
+#define GEN11_GFX_DISABLE_LEGACY_MODE (1<<3)
+
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2fa328d512fc..b298be8e5f20 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1443,8 +1443,22 @@ static void enable_execlists(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
- I915_WRITE(RING_MODE_GEN7(engine),
- _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
+ /*
+ * Make sure we're not enabling the new 12-deep CSB
+ * FIFO as that requires a slightly updated handling
+ * in the ctx switch irq. Since we're currently only
+ * using only 2 elements of the enhanced execlists the
+ * deeper FIFO it's not needed and it's not worth adding
+ * more statements to the irq handler to support it.
+ */
+ if (INTEL_GEN(dev_priv) >= 11)
+ I915_WRITE(RING_MODE_GEN7(engine),
+ _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+ else
+ I915_WRITE(RING_MODE_GEN7(engine),
+ _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
--
2.14.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 9/9] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (7 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 8/9] drm/i915/icl: Set graphics mode register for gen11 Paulo Zanoni
@ 2018-01-30 13:49 ` Paulo Zanoni
2018-01-30 18:08 ` ✓ Fi.CI.BAT: success for ICL mergeable patches Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paulo Zanoni @ 2018-01-30 13:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Anuj Phogat, Nanley Chery, Paulo Zanoni, Rodrigo Vivi
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the CNL patch by Nanley Chery.
v2: Rebase.
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Requested-by: Anuj Phogat <anuj.phogat@intel.com>
Tested-by: Anuj Phogat <anuj.phogat@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1c524ed1e1da..164dbb8cfa36 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1452,7 +1452,7 @@ static const struct reg_whitelist {
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .gen_mask = INTEL_GEN_MASK(4, 10),
+ .gen_mask = INTEL_GEN_MASK(4, 11),
.size = 8
} };
--
2.14.3
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for ICL mergeable patches
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (8 preceding siblings ...)
2018-01-30 13:49 ` [PATCH 9/9] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register Paulo Zanoni
@ 2018-01-30 18:08 ` Patchwork
2018-01-30 20:04 ` Patchwork
2018-01-30 22:02 ` ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-01-30 18:08 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : success
== Summary ==
Series 37341v1 ICL mergeable patches
https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> PASS (fi-elk-e7500) fdo#103989 +1
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:420s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:435s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:373s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:482s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:482s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:486s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:465s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:451s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:571s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:277s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:512s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:389s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:399s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:466s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:416s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:501s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:456s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:572s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:428s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:507s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:524s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:489s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:496s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:419s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:528s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:470s
9b156ad76b2e755bf527297486646cf27bbf1abd drm-tip: 2018y-01m-30d-17h-06m-58s UTC integration manifest
f201d711c601 drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register
38abda999cb7 drm/i915/icl: Set graphics mode register for gen11
89cd2c0d2904 drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
2e6e9693e51b drm/i915/gen11: fix the SAGV block time for gen11
8ace8f6de0c7 drm/i915/icl: Introduce MBus related registers
535f4ee60639 drm/i915/icl: NV12 y-plane ddb is not in same plane
3c21e9c2f822 drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
b6d79842f983 drm/i915/icl: Do not fix dbuf block size to 512
077d342cf3a0 drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7822/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for ICL mergeable patches
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (9 preceding siblings ...)
2018-01-30 18:08 ` ✓ Fi.CI.BAT: success for ICL mergeable patches Patchwork
@ 2018-01-30 20:04 ` Patchwork
2018-01-30 22:02 ` ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-01-30 20:04 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : success
== Summary ==
Series 37341v1 ICL mergeable patches
https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:419s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:374s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:485s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:487s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:486s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:462s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:579s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:279s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:518s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:391s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:416s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:457s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:498s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:426s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:508s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:530s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:486s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:418s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:435s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:516s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:395s
Blacklisted hosts:
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:474s
0edf4cc4e7c163fa61312f1708fc92284b855f8e drm-tip: 2018y-01m-30d-18h-33m-48s UTC integration manifest
c365fc5aa3af drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register
1861ab602593 drm/i915/icl: Set graphics mode register for gen11
867860d78dfa drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
1260564e0873 drm/i915/gen11: fix the SAGV block time for gen11
20736c45a449 drm/i915/icl: Introduce MBus related registers
f5744b4dca35 drm/i915/icl: NV12 y-plane ddb is not in same plane
3e5b32fd8481 drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
7a55f18d8fe1 drm/i915/icl: Do not fix dbuf block size to 512
8df166b08252 drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7830/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.IGT: failure for ICL mergeable patches
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
` (10 preceding siblings ...)
2018-01-30 20:04 ` Patchwork
@ 2018-01-30 22:02 ` Patchwork
11 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-01-30 22:02 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : failure
== Summary ==
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
dmesg-warn -> PASS (shard-snb)
Test perf_pmu:
Subgroup all-busy-check-all:
pass -> INCOMPLETE (shard-apl)
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
Subgroup oa-exponents:
fail -> PASS (shard-apl) fdo#102254
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip -> PASS (shard-snb)
Test kms_flip:
Subgroup wf_vblank-ts-check-interruptible:
pass -> FAIL (shard-snb) fdo#100368 +2
Test kms_plane_lowres:
Subgroup pipe-b-tiling-x:
pass -> FAIL (shard-apl)
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-apl total:2833 pass:1747 dwarn:1 dfail:0 fail:22 skip:1062 time:12464s
shard-hsw total:2838 pass:1735 dwarn:1 dfail:0 fail:11 skip:1090 time:12012s
shard-snb total:2838 pass:1330 dwarn:1 dfail:0 fail:11 skip:1496 time:6597s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7822/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-01-30 22:02 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-30 13:49 [PATCH 0/9] ICL mergeable patches Paulo Zanoni
2018-01-30 13:49 ` [PATCH 1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
2018-01-30 13:49 ` [PATCH 2/9] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
2018-01-30 13:49 ` [PATCH 3/9] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
2018-01-30 13:49 ` [PATCH 4/9] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
2018-01-30 13:49 ` [PATCH 5/9] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
2018-01-30 13:49 ` [PATCH 6/9] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
2018-01-30 13:49 ` [PATCH 7/9] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Paulo Zanoni
2018-01-30 13:49 ` [PATCH 8/9] drm/i915/icl: Set graphics mode register for gen11 Paulo Zanoni
2018-01-30 13:49 ` [PATCH 9/9] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register Paulo Zanoni
2018-01-30 18:08 ` ✓ Fi.CI.BAT: success for ICL mergeable patches Patchwork
2018-01-30 20:04 ` Patchwork
2018-01-30 22:02 ` ✗ Fi.CI.IGT: failure " Patchwork
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