[U-Boot] [PATCH 0/3] clk: at91: add usb and plladiv drivers

[U-Boot] [PATCH 0/3] clk: at91: add usb and plladiv drivers

[Wenyou Yang]

In order to provide the clocks UHP48MHz and UHP12MHz to the USB
Host OHCI, add the USB clock and PLLADIV clock driver.


Wenyou Yang (3):
  clk: at91: add USB Host clock driver
  clk: at91: add PLLADIV driver
  clk: at91: clk-system: add set/get_rate operations

 arch/arm/mach-at91/include/mach/at91_pmc.h |   6 ++
 drivers/clk/at91/Kconfig                   |   8 ++
 drivers/clk/at91/Makefile                  |   3 +-
 drivers/clk/at91/clk-plladiv.c             |  88 +++++++++++++++++
 drivers/clk/at91/clk-system.c              |  26 +++++
 drivers/clk/at91/clk-usb.c                 | 146 +++++++++++++++++++++++++++++
 6 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/at91/clk-plladiv.c
 create mode 100644 drivers/clk/at91/clk-usb.c

-- 
2.16.0.rc1

[U-Boot] [PATCH 1/3] clk: at91: add USB Host clock driver

[Wenyou Yang]

Add USB clock driver to configure the input clock and the divider
in the PMC_USB register to generate a 48MHz and a 12MHz signal to
the USB Host OHCI.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
---

 arch/arm/mach-at91/include/mach/at91_pmc.h |   6 ++
 drivers/clk/at91/Kconfig                   |   8 ++
 drivers/clk/at91/Makefile                  |   1 +
 drivers/clk/at91/clk-usb.c                 | 146 +++++++++++++++++++++++++++++
 4 files changed, 161 insertions(+)
 create mode 100644 drivers/clk/at91/clk-usb.c

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 08ad1bf2d0..fbda8d5f63 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -233,9 +233,15 @@ typedef struct at91_pmc {
 #define			AT91_PMC_PDIV_1			(0 << 12)
 #define			AT91_PMC_PDIV_2			(1 << 12)
 
+#define AT91_PMC_USB_USBS_MASK		0x1
+#define AT91_PMC_USB_USBS_OFFSET		0
+#define AT91_PMC_USB_USBS_(x)		(x & 0x1)
 #define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
 #define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
 #define		AT91_PMC_USBS_USB_PLLB		(0x1)		/* USB Clock Input is PLLB, AT91SAM9N12 only */
+#define AT91_PMC_USB_DIV_MASK		0xf
+#define AT91_PMC_USB_DIV_OFFSET		8
+#define AT91_PMC_USB_DIV_(x)		((x & 0xf) << 8)
 #define		AT91_PMC_USB_DIV_2		(0x1 <<  8)	/* USB Clock divided by 2 */
 #define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
 #define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index fd56f200b9..8d482a2752 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -27,6 +27,14 @@ config AT91_UTMI
 	  fast crystal oscillator to meet the frequency accuracy
 	  required by USB.
 
+config AT91_USB_CLK
+	bool "Support USB OHCI Input Clock"
+	depends on CLK_AT91
+	help
+	  This option is used to enable the USB Input Clock, from
+	  the device tree, configure the USBS bit (PLLA or UTMI PLL)
+	  and USBDIV field of the PMC_USB register.
+
 config AT91_H32MX
 	bool "Support H32MX 32-bit Matrix Clock"
 	depends on CLK_AT91
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index fbe3cb6581..8cac3f9e18 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -7,5 +7,6 @@ obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o
 obj-y += clk-system.o clk-peripheral.o
 
 obj-$(CONFIG_AT91_UTMI)		+= clk-utmi.o
+obj-$(CONFIG_AT91_USB_CLK)	+= clk-usb.o
 obj-$(CONFIG_AT91_H32MX)	+= clk-h32mx.o
 obj-$(CONFIG_AT91_GENERIC_CLK)	+= clk-generated.o
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 0000000000..36622c09dc
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2018 Microhip / Atmel Corporation
+ *               Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/io.h>
+#include <mach/at91_pmc.h>
+#include "pmc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AT91_USB_CLK_SOURCE_MAX	2
+#define AT91_USB_CLK_MAX_DIV	15
+
+struct at91_usb_clk_priv {
+	u32 num_clksource;
+};
+
+static ulong at91_usb_clk_get_rate(struct clk *clk)
+{
+	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+	struct at91_pmc *pmc = plat->reg_base;
+	struct clk source;
+	u32 tmp, usbdiv;
+	u8 source_index;
+	int ret;
+
+	tmp = readl(&pmc->pcr);
+	source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
+			AT91_PMC_USB_USBS_MASK;
+	usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
+
+	ret = clk_get_by_index(clk->dev, source_index, &source);
+	if (ret)
+		return 0;
+
+	return clk_get_rate(&source) / (usbdiv + 1);
+}
+
+static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+	struct at91_pmc *pmc = plat->reg_base;
+	struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
+	struct clk source, best_source;
+	ulong tmp_rate, best_rate = rate, source_rate;
+	int tmp_diff, best_diff = -1;
+	u32 div, best_div = 0;
+	u8 best_source_index = 0;
+	u8 i;
+	u32 tmp;
+	int ret;
+
+	for (i = 0; i < priv->num_clksource; i++) {
+		ret = clk_get_by_index(clk->dev, i, &source);
+		if (ret)
+			return ret;
+
+		source_rate = clk_get_rate(&source);
+		if (IS_ERR_VALUE(source_rate))
+			return source_rate;
+
+		for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
+			tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
+			tmp_diff = abs(rate - tmp_rate);
+
+			if (best_diff < 0 || best_diff > tmp_diff) {
+				best_rate = tmp_rate;
+				best_diff = tmp_diff;
+
+				best_div = div - 1;
+				best_source = source;
+				best_source_index = i;
+			}
+
+			if (!best_diff || tmp_rate < rate)
+				break;
+		}
+
+		if (!best_diff)
+			break;
+	}
+
+	debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
+	      best_source.dev->name, best_rate, best_div);
+
+	ret = clk_enable(&best_source);
+	if (ret)
+		return ret;
+
+	tmp = AT91_PMC_USB_USBS_(best_source_index) |
+	      AT91_PMC_USB_DIV_(best_div);
+	writel(tmp, &pmc->usb);
+
+	return 0;
+}
+
+static struct clk_ops at91_usb_clk_ops = {
+	.get_rate = at91_usb_clk_get_rate,
+	.set_rate = at91_usb_clk_set_rate,
+};
+
+static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct at91_usb_clk_priv *priv = dev_get_priv(dev);
+	u32 cells[AT91_USB_CLK_SOURCE_MAX];
+	u32 num_clksource;
+
+	num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
+						   dev_of_offset(dev),
+						   "clocks", cells,
+						   AT91_USB_CLK_SOURCE_MAX);
+
+	if (!num_clksource)
+		return -1;
+
+	priv->num_clksource = num_clksource;
+
+	return 0;
+}
+
+static int at91_usb_clk_probe(struct udevice *dev)
+{
+	return at91_pmc_core_probe(dev);
+}
+
+static const struct udevice_id at91_usb_clk_match[] = {
+	{ .compatible = "atmel,at91sam9x5-clk-usb" },
+	{}
+};
+
+U_BOOT_DRIVER(at91_usb_clk) = {
+	.name = "at91-usb-clk",
+	.id = UCLASS_CLK,
+	.of_match = at91_usb_clk_match,
+	.probe = at91_usb_clk_probe,
+	.ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
+	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+	.ops = &at91_usb_clk_ops,
+};
-- 
2.16.0.rc1

[U-Boot] [PATCH 2/3] clk: at91: add PLLADIV driver

[Wenyou Yang]

As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
---

 drivers/clk/at91/Makefile      |  2 +-
 drivers/clk/at91/clk-plladiv.c | 88 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/at91/clk-plladiv.c

diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 8cac3f9e18..8c197ff949 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
 #
 
 obj-y += pmc.o sckc.o
-obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o
+obj-y += clk-slow.o clk-main.o clk-plla.o clk-plladiv.o clk-master.o
 obj-y += clk-system.o clk-peripheral.o
 
 obj-$(CONFIG_AT91_UTMI)		+= clk-utmi.o
diff --git a/drivers/clk/at91/clk-plladiv.c b/drivers/clk/at91/clk-plladiv.c
new file mode 100644
index 0000000000..0599d2893b
--- /dev/null
+++ b/drivers/clk/at91/clk-plladiv.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2018 Microhip / Atmel Corporation
+ *               Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/io.h>
+#include <mach/at91_pmc.h>
+#include "pmc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int at91_plladiv_clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
+static ulong at91_plladiv_clk_get_rate(struct clk *clk)
+{
+	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+	struct at91_pmc *pmc = plat->reg_base;
+	struct clk source;
+	ulong clk_rate;
+	int ret;
+
+	ret = clk_get_by_index(clk->dev, 0, &source);
+	if (ret)
+		return -EINVAL;
+
+	clk_rate = clk_get_rate(&source);
+	if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
+		clk_rate /= 2;
+
+	return clk_rate;
+}
+
+static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+	struct at91_pmc *pmc = plat->reg_base;
+	struct clk source;
+	ulong parent_rate;
+	int ret;
+
+	ret = clk_get_by_index(clk->dev, 0, &source);
+	if (ret)
+		return -EINVAL;
+
+	parent_rate = clk_get_rate(&source);
+	if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
+		return -EINVAL;
+
+	if (parent_rate != rate) {
+		writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
+		       &pmc->mckr);
+	}
+
+	return 0;
+}
+
+static struct clk_ops at91_plladiv_clk_ops = {
+	.enable = at91_plladiv_clk_enable,
+	.get_rate = at91_plladiv_clk_get_rate,
+	.set_rate = at91_plladiv_clk_set_rate,
+};
+
+static int at91_plladiv_clk_probe(struct udevice *dev)
+{
+	return at91_pmc_core_probe(dev);
+}
+
+static const struct udevice_id at91_plladiv_clk_match[] = {
+	{ .compatible = "atmel,at91sam9x5-clk-plldiv" },
+	{}
+};
+
+U_BOOT_DRIVER(at91_plladiv_clk) = {
+	.name = "at91-plladiv-clk",
+	.id = UCLASS_CLK,
+	.of_match = at91_plladiv_clk_match,
+	.probe = at91_plladiv_clk_probe,
+	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+	.ops = &at91_plladiv_clk_ops,
+};
-- 
2.16.0.rc1

[U-Boot] [PATCH 3/3] clk: at91: clk-system: add set/get_rate operations

[Wenyou Yang]

To support set/get the clock rate, add set/get_rate operations.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
---

 drivers/clk/at91/clk-system.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index 24b271aa18..81fe47a9d7 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -44,6 +44,30 @@ static inline int is_pck(int id)
 	return (id >= 8) && (id <= 15);
 }
 
+static ulong system_clk_get_rate(struct clk *clk)
+{
+	struct clk clk_dev;
+	int ret;
+
+	ret = clk_get_by_index(clk->dev, 0, &clk_dev);
+	if (ret)
+		return -EINVAL;
+
+	return clk_get_rate(&clk_dev);
+}
+
+static ulong system_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk clk_dev;
+	int ret;
+
+	ret = clk_get_by_index(clk->dev, 0, &clk_dev);
+	if (ret)
+		return -EINVAL;
+
+	return clk_set_rate(&clk_dev, rate);
+}
+
 static int system_clk_enable(struct clk *clk)
 {
 	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
@@ -73,6 +97,8 @@ static int system_clk_enable(struct clk *clk)
 
 static struct clk_ops system_clk_ops = {
 	.of_xlate = at91_clk_of_xlate,
+	.get_rate = system_clk_get_rate,
+	.set_rate = system_clk_set_rate,
 	.enable = system_clk_enable,
 };
 
-- 
2.16.0.rc1

[U-Boot] [PATCH 0/3] clk: at91: add usb and plladiv drivers

[Wenyou Yang]

Hi,

Do you have any comments?


On 2/9/2018 11:34 AM, Wenyou Yang wrote:
> In order to provide the clocks UHP48MHz and UHP12MHz to the USB
> Host OHCI, add the USB clock and PLLADIV clock driver.
>
>
> Wenyou Yang (3):
>    clk: at91: add USB Host clock driver
>    clk: at91: add PLLADIV driver
>    clk: at91: clk-system: add set/get_rate operations
>
>   arch/arm/mach-at91/include/mach/at91_pmc.h |   6 ++
>   drivers/clk/at91/Kconfig                   |   8 ++
>   drivers/clk/at91/Makefile                  |   3 +-
>   drivers/clk/at91/clk-plladiv.c             |  88 +++++++++++++++++
>   drivers/clk/at91/clk-system.c              |  26 +++++
>   drivers/clk/at91/clk-usb.c                 | 146 +++++++++++++++++++++++++++++
>   6 files changed, 276 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/at91/clk-plladiv.c
>   create mode 100644 drivers/clk/at91/clk-usb.c
>

Best Regards,
Wenyou Yang

[U-Boot] [U-Boot,1/3] clk: at91: add USB Host clock driver

[Tom Rini]

On Fri, Feb 09, 2018 at 11:34:50AM +0800, Wenyou Yang wrote:

> Add USB clock driver to configure the input clock and the divider
> in the PMC_USB register to generate a 48MHz and a 12MHz signal to
> the USB Host OHCI.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,2/3] clk: at91: add PLLADIV driver

[Tom Rini]

On Fri, Feb 09, 2018 at 11:34:51AM +0800, Wenyou Yang wrote:

> As said in the SAMA5D2 datasheet, the PLLA clock must be divided
> by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
> PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 3/3] clk: at91: clk-system: add set/get_rate operations

[Tom Rini]

On Fri, Feb 09, 2018 at 11:34:52AM +0800, Wenyou Yang wrote:

> To support set/get the clock rate, add set/get_rate operations.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

Applied to u-boot/master, thanks!

-- 
Tom
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