* [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9
@ 2018-02-09 4:09 Vaibhav Jain
2018-02-09 8:25 ` christophe lombard
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Vaibhav Jain @ 2018-02-09 4:09 UTC (permalink / raw)
To: linuxppc-dev, Frederic Barrat
Cc: Vaibhav Jain, Andrew Donnellan, Christophe Lombard,
Philippe Bergheaud, Alastair D'Silva
We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.
Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
---
drivers/misc/cxl/pci.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 758842f65a1b..c983f23cc2ed 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
if (cxl_is_power9_dd1()) {
/* Disabling deadlock counter CAR */
cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
- } else
- cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
+ /* Enable NORST */
+ cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
+ } else {
+ /* Enable NORST and DD2 features */
+ cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
+ }
return 0;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9
2018-02-09 4:09 [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9 Vaibhav Jain
@ 2018-02-09 8:25 ` christophe lombard
2018-02-09 14:56 ` Frederic Barrat
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: christophe lombard @ 2018-02-09 8:25 UTC (permalink / raw)
To: Vaibhav Jain, linuxppc-dev, Frederic Barrat
Cc: Philippe Bergheaud, Alastair D'Silva, Andrew Donnellan,
Christophe Lombard
Le 09/02/2018 à 05:09, Vaibhav Jain a écrit :
> We enable the NORST bit by default for debug afu images to prevent
> reset of AFU trace-data on a PCI link drop. For production AFU images
> this bit is always ignored and PSL gets reconfigured anyways thereby
> resetting the trace data. So setting this bit for non-debug images
> doesn't have any impact.
>
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
> drivers/misc/cxl/pci.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index 758842f65a1b..c983f23cc2ed 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
> if (cxl_is_power9_dd1()) {
> /* Disabling deadlock counter CAR */
> cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
> - } else
> - cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
> + /* Enable NORST */
> + cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
> + } else {
> + /* Enable NORST and DD2 features */
> + cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
> + }
>
> return 0;
> }
>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9
2018-02-09 4:09 [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9 Vaibhav Jain
2018-02-09 8:25 ` christophe lombard
@ 2018-02-09 14:56 ` Frederic Barrat
2018-02-13 2:55 ` Andrew Donnellan
2018-03-14 9:27 ` Michael Ellerman
3 siblings, 0 replies; 5+ messages in thread
From: Frederic Barrat @ 2018-02-09 14:56 UTC (permalink / raw)
To: Vaibhav Jain, linuxppc-dev
Cc: Andrew Donnellan, Christophe Lombard, Philippe Bergheaud,
Alastair D'Silva
Le 09/02/2018 à 05:09, Vaibhav Jain a écrit :
> We enable the NORST bit by default for debug afu images to prevent
> reset of AFU trace-data on a PCI link drop. For production AFU images
> this bit is always ignored and PSL gets reconfigured anyways thereby
> resetting the trace data. So setting this bit for non-debug images
> doesn't have any impact.
>
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
btw, we should start removing dd1 code, it's not like anybody is going
to try that now.
Fred
> drivers/misc/cxl/pci.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index 758842f65a1b..c983f23cc2ed 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
> if (cxl_is_power9_dd1()) {
> /* Disabling deadlock counter CAR */
> cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
> - } else
> - cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
> + /* Enable NORST */
> + cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
> + } else {
> + /* Enable NORST and DD2 features */
> + cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
> + }
>
> return 0;
> }
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9
2018-02-09 4:09 [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9 Vaibhav Jain
2018-02-09 8:25 ` christophe lombard
2018-02-09 14:56 ` Frederic Barrat
@ 2018-02-13 2:55 ` Andrew Donnellan
2018-03-14 9:27 ` Michael Ellerman
3 siblings, 0 replies; 5+ messages in thread
From: Andrew Donnellan @ 2018-02-13 2:55 UTC (permalink / raw)
To: Vaibhav Jain, linuxppc-dev, Frederic Barrat
Cc: Christophe Lombard, Philippe Bergheaud, Alastair D'Silva
On 09/02/18 15:09, Vaibhav Jain wrote:
> We enable the NORST bit by default for debug afu images to prevent
> reset of AFU trace-data on a PCI link drop. For production AFU images
> this bit is always ignored and PSL gets reconfigured anyways thereby
> resetting the trace data. So setting this bit for non-debug images
> doesn't have any impact.
>
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
--
Andrew Donnellan OzLabs, ADL Canberra
andrew.donnellan@au1.ibm.com IBM Australia Limited
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: cxl: Enable NORST bit in PSL_DEBUG register for PSL9
2018-02-09 4:09 [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9 Vaibhav Jain
` (2 preceding siblings ...)
2018-02-13 2:55 ` Andrew Donnellan
@ 2018-03-14 9:27 ` Michael Ellerman
3 siblings, 0 replies; 5+ messages in thread
From: Michael Ellerman @ 2018-03-14 9:27 UTC (permalink / raw)
To: Vaibhav Jain, linuxppc-dev, Frederic Barrat
Cc: Philippe Bergheaud, Alastair D'Silva, Vaibhav Jain,
Andrew Donnellan, Christophe Lombard
On Fri, 2018-02-09 at 04:09:16 UTC, Vaibhav Jain wrote:
> We enable the NORST bit by default for debug afu images to prevent
> reset of AFU trace-data on a PCI link drop. For production AFU images
> this bit is always ignored and PSL gets reconfigured anyways thereby
> resetting the trace data. So setting this bit for non-debug images
> doesn't have any impact.
>
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/03ebb419b896e0fb2da3f34b57d45e
cheers
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-14 9:27 UTC | newest]
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2018-02-09 4:09 [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9 Vaibhav Jain
2018-02-09 8:25 ` christophe lombard
2018-02-09 14:56 ` Frederic Barrat
2018-02-13 2:55 ` Andrew Donnellan
2018-03-14 9:27 ` Michael Ellerman
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