[PATCH] drm/i915: Move EDRAM capability bits to intel_driver_caps

* [PATCH] drm/i915: Move EDRAM capability bits to intel_driver_caps
@ 2018-02-09 11:29 Chris Wilson
  2018-02-09 11:31 ` Chris Wilson
  2018-02-09 15:12 ` ✗ Fi.CI.BAT: failure for " Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Chris Wilson @ 2018-02-09 11:29 UTC (permalink / raw)
  To: intel-gfx

Move the storage of the runtime discovery of EDRAM to intel_driver_caps
so that we include it in all the relevant error state dumping and
debugging.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---

Or do we want to keep driver_caps only for driver related info, and move
this sort of runtime discovery to intel_runtime_info? With the intention
of killing off all remaining mkwrite_intel_info()
-Chris

---
 drivers/gpu/drm/i915/i915_drv.h          | 5 +----
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 drivers/gpu/drm/i915/intel_uncore.c      | 8 +++-----
 4 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7db3557b945c..b70803c3e4cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2040,9 +2040,6 @@ struct drm_i915_private {
 
 	struct intel_l3_parity l3_parity;
 
-	/* Cannot be determined by PCIID. You must always read a register. */
-	u32 edram_cap;
-
 	/*
 	 * Protects RPS/RC6 register access and PCU communication.
 	 * Must be taken after struct_mutex if nested. Note that
@@ -2746,7 +2743,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
 #define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
-#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
+#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->caps.edram & EDRAM_ENABLED))
 #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
 				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..dd1ade7479ce 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -590,5 +590,6 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 			     struct drm_printer *p)
 {
+	drm_printf(p, "EDRAM: %x\n", caps->edram);
 	drm_printf(p, "scheduler: %x\n", caps->scheduler);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 71fdfb0451ef..f5d09e5c5fb3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -168,6 +168,7 @@ struct intel_device_info {
 };
 
 struct intel_driver_caps {
+	u32 edram; /* Cannot be determined by PCIID, only from a register. */
 	unsigned int scheduler;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e09981a3113c..d3e642800bc3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -419,7 +419,7 @@ static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
 {
 	const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 	const unsigned int sets[4] = { 1, 1, 2, 2 };
-	const u32 cap = dev_priv->edram_cap;
+	const u32 cap = dev_priv->caps.edram;
 
 	return EDRAM_NUM_BANKS(cap) *
 		ways[EDRAM_WAYS_IDX(cap)] *
@@ -446,13 +446,11 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 	if (IS_HASWELL(dev_priv) ||
 	    IS_BROADWELL(dev_priv) ||
 	    INTEL_GEN(dev_priv) >= 9) {
-		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
-							HSW_EDRAM_CAP);
+		dev_priv->caps.edram =
+			__raw_i915_read32(dev_priv, HSW_EDRAM_CAP);
 
 		/* NB: We can't write IDICR yet because we do not have gt funcs
 		 * set up */
-	} else {
-		dev_priv->edram_cap = 0;
 	}
 
 	if (HAS_EDRAM(dev_priv))
-- 
2.16.1

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