From: Enric Balletbo i Serra <enric.balletbo@collabora.com> To: Rob Herring <robh+dt@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Brian Norris <briannorris@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de>, dianders@chromium.org, Chris Zhong <zyw@rock-chips.com>, William wu <wulf@rock-chips.com>, hl@rock-chips.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 3/6] phy: rockchip-typec: enable usb3 host during usb3 phy power on Date: Wed, 14 Feb 2018 17:54:44 +0100 [thread overview] Message-ID: <20180214165447.12181-3-enric.balletbo@collabora.com> (raw) In-Reply-To: <20180214165447.12181-1-enric.balletbo@collabora.com> From: William wu <wulf@rock-chips.com> We have forced usb3 to work in usb2 only mode in firmware by setting usb3tousb2_en (bit3 of GRF_USB3PHY0/1_CON0) to 1, and setting host_u3_port_disable (bit0 of GRF_USB3OTG0/1_CON1) to 1 and host_u3_port (bit15~12 of GRF_USB3OTG0/1_CON1) to 0. So we need to re-enable usb3 host. Note that the RK3399 TRM suggests that we should keep the whole usb3 controller in reset for the duration of the Type-C PHY initialization. However, it's hard to assert the reset in the current framework of reset. And according to the TRM, it doesn't require that we should clear the usb3tousb2 bit before pipe ready. So let's enable the usb3 host after pipe ready to avoid the Type-C PHY initialization failure. Signed-off-by: William wu <wulf@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> --- Changes since v1: - Use the registers offsets from the driver not the DT. drivers/phy/rockchip/phy-rockchip-typec.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 291493d9e9b6..40c5e7d6b5cb 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -363,6 +363,8 @@ struct rockchip_usb3phy_port_cfg { struct usb3phy_reg usb3tousb2_en; struct usb3phy_reg external_psm; struct usb3phy_reg pipe_status; + struct usb3phy_reg usb3_host_disable; + struct usb3phy_reg usb3_host_port; }; static const struct rockchip_usb3phy_port_cfg tcphy0_port_cfg = { @@ -370,6 +372,8 @@ static const struct rockchip_usb3phy_port_cfg tcphy0_port_cfg = { .usb3tousb2_en = { 0xe580, 3, 19 }, .external_psm = { 0xe588, 14, 30 }, .pipe_status = { 0xe5c0, 0, 0 }, + .usb3_host_disable = { 0x2434, 0, 16 }, + .usb3_host_port = { 0x2434, 12, 28 }, }; static const struct rockchip_usb3phy_port_cfg tcphy1_port_cfg = { @@ -377,6 +381,8 @@ static const struct rockchip_usb3phy_port_cfg tcphy1_port_cfg = { .usb3tousb2_en = { 0xe58c, 3, 19 }, .external_psm = { 0xe594, 14, 30 }, .pipe_status = { 0xe5c0, 16, 16 }, + .usb3_host_disable = { 0x2444, 0, 16 }, + .usb3_host_port = { 0x2444, 12, 28 }, }; struct rockchip_typec_phy { @@ -869,6 +875,9 @@ static int rockchip_usb3_phy_power_on(struct phy *phy) regmap_read(tcphy->grf_regs, reg->offset, &val); if (!(val & BIT(reg->enable_bit))) { tcphy->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB); + /* enable usb3 host */ + property_enable(tcphy, &cfg->usb3_host_disable, 0); + property_enable(tcphy, &cfg->usb3_host_port, 1); goto unlock_ret; } usleep_range(10, 20); -- 2.15.1
WARNING: multiple messages have this Message-ID (diff)
From: enric.balletbo@collabora.com (Enric Balletbo i Serra) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/6] phy: rockchip-typec: enable usb3 host during usb3 phy power on Date: Wed, 14 Feb 2018 17:54:44 +0100 [thread overview] Message-ID: <20180214165447.12181-3-enric.balletbo@collabora.com> (raw) In-Reply-To: <20180214165447.12181-1-enric.balletbo@collabora.com> From: William wu <wulf@rock-chips.com> We have forced usb3 to work in usb2 only mode in firmware by setting usb3tousb2_en (bit3 of GRF_USB3PHY0/1_CON0) to 1, and setting host_u3_port_disable (bit0 of GRF_USB3OTG0/1_CON1) to 1 and host_u3_port (bit15~12 of GRF_USB3OTG0/1_CON1) to 0. So we need to re-enable usb3 host. Note that the RK3399 TRM suggests that we should keep the whole usb3 controller in reset for the duration of the Type-C PHY initialization. However, it's hard to assert the reset in the current framework of reset. And according to the TRM, it doesn't require that we should clear the usb3tousb2 bit before pipe ready. So let's enable the usb3 host after pipe ready to avoid the Type-C PHY initialization failure. Signed-off-by: William wu <wulf@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> --- Changes since v1: - Use the registers offsets from the driver not the DT. drivers/phy/rockchip/phy-rockchip-typec.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 291493d9e9b6..40c5e7d6b5cb 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -363,6 +363,8 @@ struct rockchip_usb3phy_port_cfg { struct usb3phy_reg usb3tousb2_en; struct usb3phy_reg external_psm; struct usb3phy_reg pipe_status; + struct usb3phy_reg usb3_host_disable; + struct usb3phy_reg usb3_host_port; }; static const struct rockchip_usb3phy_port_cfg tcphy0_port_cfg = { @@ -370,6 +372,8 @@ static const struct rockchip_usb3phy_port_cfg tcphy0_port_cfg = { .usb3tousb2_en = { 0xe580, 3, 19 }, .external_psm = { 0xe588, 14, 30 }, .pipe_status = { 0xe5c0, 0, 0 }, + .usb3_host_disable = { 0x2434, 0, 16 }, + .usb3_host_port = { 0x2434, 12, 28 }, }; static const struct rockchip_usb3phy_port_cfg tcphy1_port_cfg = { @@ -377,6 +381,8 @@ static const struct rockchip_usb3phy_port_cfg tcphy1_port_cfg = { .usb3tousb2_en = { 0xe58c, 3, 19 }, .external_psm = { 0xe594, 14, 30 }, .pipe_status = { 0xe5c0, 16, 16 }, + .usb3_host_disable = { 0x2444, 0, 16 }, + .usb3_host_port = { 0x2444, 12, 28 }, }; struct rockchip_typec_phy { @@ -869,6 +875,9 @@ static int rockchip_usb3_phy_power_on(struct phy *phy) regmap_read(tcphy->grf_regs, reg->offset, &val); if (!(val & BIT(reg->enable_bit))) { tcphy->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB); + /* enable usb3 host */ + property_enable(tcphy, &cfg->usb3_host_disable, 0); + property_enable(tcphy, &cfg->usb3_host_port, 1); goto unlock_ret; } usleep_range(10, 20); -- 2.15.1
next prev parent reply other threads:[~2018-02-14 16:54 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-02-14 16:54 [PATCH v2 1/6] phy: rockchip-typec: deprecate some DT properties for various register fields Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-14 16:54 ` [PATCH v2 2/6] dt-bindings: phy-rockchip-typec: deprecate some register properties Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-15 16:10 ` Heiko Stuebner 2018-02-15 16:10 ` Heiko Stuebner 2018-02-15 16:10 ` Heiko Stuebner 2018-02-14 16:54 ` Enric Balletbo i Serra [this message] 2018-02-14 16:54 ` [PATCH v2 3/6] phy: rockchip-typec: enable usb3 host during usb3 phy power on Enric Balletbo i Serra 2018-02-14 16:54 ` [PATCH v2 4/6] phy: rockchip-typec: force to USB2 if DP at 4 lanes mode Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-14 16:54 ` [PATCH v2 5/6] phy: rockchip-typec: support DP phy switch Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-14 16:54 ` [PATCH v2 6/6] drm/rockchip: cdn-dp: remove the " Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-14 16:54 ` Enric Balletbo i Serra 2018-02-15 16:06 ` [PATCH v2 1/6] phy: rockchip-typec: deprecate some DT properties for various register fields Heiko Stuebner 2018-02-15 16:06 ` Heiko Stuebner
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20180214165447.12181-3-enric.balletbo@collabora.com \ --to=enric.balletbo@collabora.com \ --cc=briannorris@chromium.org \ --cc=devicetree@vger.kernel.org \ --cc=dianders@chromium.org \ --cc=heiko@sntech.de \ --cc=hl@rock-chips.com \ --cc=kernel@collabora.com \ --cc=kishon@ti.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-rockchip@lists.infradead.org \ --cc=robh+dt@kernel.org \ --cc=wulf@rock-chips.com \ --cc=zyw@rock-chips.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.