* [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir
@ 2018-02-15 7:37 Chris Wilson
2018-02-15 7:37 ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Chris Wilson @ 2018-02-15 7:37 UTC (permalink / raw)
To: intel-gfx
Keep the master iir and use it to reduce the number of reads and writes
to the GT iir array, i.e. only the bits marked as set by the master iir
are valid inside GT iir array and will be handled during the interrupt.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++----------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..b7b377ba7b6e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
u32 master_ctl, u32 gt_iir[4])
{
+#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
+ GEN8_GT_BCS_IRQ | \
+ GEN8_GT_VCS1_IRQ | \
+ GEN8_GT_VCS2_IRQ | \
+ GEN8_GT_VECS_IRQ | \
+ GEN8_GT_PM_IRQ | \
+ GEN8_GT_GUC_IRQ)
+
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
if (gt_iir[0])
@@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
}
static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
- u32 gt_iir[4])
+ u32 master_ctl, u32 gt_iir[4])
{
- if (gt_iir[0]) {
+ if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gen8_cs_irq_handler(dev_priv->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT);
gen8_cs_irq_handler(dev_priv->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT);
}
- if (gt_iir[1]) {
+ if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
gen8_cs_irq_handler(dev_priv->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
gen8_cs_irq_handler(dev_priv->engine[VCS2],
gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
}
- if (gt_iir[3])
+ if (master_ctl & GEN8_GT_VECS_IRQ) {
gen8_cs_irq_handler(dev_priv->engine[VECS],
gt_iir[3], GEN8_VECS_IRQ_SHIFT);
+ }
- if (gt_iir[2] & dev_priv->pm_rps_events)
- gen6_rps_irq_handler(dev_priv, gt_iir[2]);
+ if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+ if (gt_iir[2] & dev_priv->pm_rps_events)
+ gen6_rps_irq_handler(dev_priv, gt_iir[2]);
- if (gt_iir[2] & dev_priv->pm_guc_events)
- gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+ if (gt_iir[2] & dev_priv->pm_guc_events)
+ gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+ }
}
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
@@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
do {
u32 master_ctl, iir;
- u32 gt_iir[4] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 hotplug_status = 0;
+ u32 gt_iir[4];
u32 ier = 0;
master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
@@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
POSTING_READ(GEN8_MASTER_IRQ);
- gen8_gt_irq_handler(dev_priv, gt_iir);
+ gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
if (hotplug_status)
i9xx_hpd_irq_handler(dev_priv, hotplug_status);
@@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
- struct drm_device *dev = arg;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(arg);
u32 master_ctl;
- u32 gt_iir[4] = {};
+ u32 gt_iir[4];
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
- /* IRQs are synced during runtime_suspend, we don't require a wakeref */
- disable_rpm_wakeref_asserts(dev_priv);
-
/* Find, clear, then process each source of interrupt */
gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
- gen8_gt_irq_handler(dev_priv, gt_iir);
- gen8_de_irq_handler(dev_priv, master_ctl);
+
+ /* IRQs are synced during runtime_suspend, we don't require a wakeref */
+ if (master_ctl & ~GEN8_GT_IRQS) {
+ disable_rpm_wakeref_asserts(dev_priv);
+ gen8_de_irq_handler(dev_priv, master_ctl);
+ enable_rpm_wakeref_asserts(dev_priv);
+ }
I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
- POSTING_READ_FW(GEN8_MASTER_IRQ);
- enable_rpm_wakeref_asserts(dev_priv);
+ gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
return IRQ_HANDLED;
}
--
2.16.1
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
@ 2018-02-15 7:37 ` Chris Wilson
2018-02-15 16:57 ` Chris Wilson
2018-02-19 10:09 ` [PATCH v2] " Chris Wilson
2018-02-15 7:58 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir Patchwork
` (6 subsequent siblings)
7 siblings, 2 replies; 17+ messages in thread
From: Chris Wilson @ 2018-02-15 7:37 UTC (permalink / raw)
To: intel-gfx
The compiler is not automatically caching the i915->regs address inside
a register and emitting a load for every mmio access. For simple
functions like gen8_gt_irq_handler that are already using the raw
accessors, we can open-code them for substantial savings:
add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
Function old new delta
gen8_gt_irq_handler 290 266 -24
gen8_gt_irq_ack 181 122 -59
Total: Before=954637, After=954554, chg -0.01%
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
And so begins the long haul of de-I915_READ/WRITE-ing the driver...
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++----------------------
1 file changed, 27 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b7b377ba7b6e..10d62b33cb13 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1413,9 +1413,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
tasklet_hi_schedule(&execlists->tasklet);
}
-static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_ack(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
{
+ void __iomem * const regs = i915->regs;
+
#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
GEN8_GT_BCS_IRQ | \
GEN8_GT_VCS1_IRQ | \
@@ -1425,62 +1427,57 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
GEN8_GT_GUC_IRQ)
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
- if (gt_iir[0])
- I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
+ gt_iir[0] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
+ if (likely(gt_iir[0]))
+ writel(gt_iir[0], regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
}
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
- gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
- if (gt_iir[1])
- I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
+ gt_iir[1] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(1)));
+ if (likely(gt_iir[1]))
+ writel(gt_iir[1], regs + i915_mmio_reg_offset(GEN8_GT_IIR(1)));
}
- if (master_ctl & GEN8_GT_VECS_IRQ) {
- gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
- if (gt_iir[3])
- I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
+ if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+ gt_iir[2] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(2)));
+ if (likely(gt_iir[2] & (i915->pm_rps_events | i915->pm_guc_events)))
+ writel(gt_iir[2] & (i915->pm_rps_events |
+ i915->pm_guc_events),
+ regs + i915_mmio_reg_offset(GEN8_GT_IIR(2)));
}
- if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
- if (gt_iir[2] & (dev_priv->pm_rps_events |
- dev_priv->pm_guc_events)) {
- I915_WRITE_FW(GEN8_GT_IIR(2),
- gt_iir[2] & (dev_priv->pm_rps_events |
- dev_priv->pm_guc_events));
- }
+ if (master_ctl & GEN8_GT_VECS_IRQ) {
+ gt_iir[3] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(3)));
+ if (likely(gt_iir[3]))
+ writel(gt_iir[3], regs + i915_mmio_reg_offset(GEN8_GT_IIR(3)));
}
}
-static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_handler(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
{
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- gen8_cs_irq_handler(dev_priv->engine[RCS],
+ gen8_cs_irq_handler(i915->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT);
- gen8_cs_irq_handler(dev_priv->engine[BCS],
+ gen8_cs_irq_handler(i915->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT);
}
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
- gen8_cs_irq_handler(dev_priv->engine[VCS],
+ gen8_cs_irq_handler(i915->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
- gen8_cs_irq_handler(dev_priv->engine[VCS2],
+ gen8_cs_irq_handler(i915->engine[VCS2],
gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
}
if (master_ctl & GEN8_GT_VECS_IRQ) {
- gen8_cs_irq_handler(dev_priv->engine[VECS],
+ gen8_cs_irq_handler(i915->engine[VECS],
gt_iir[3], GEN8_VECS_IRQ_SHIFT);
}
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- if (gt_iir[2] & dev_priv->pm_rps_events)
- gen6_rps_irq_handler(dev_priv, gt_iir[2]);
-
- if (gt_iir[2] & dev_priv->pm_guc_events)
- gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+ gen6_rps_irq_handler(i915, gt_iir[2]);
+ gen9_guc_irq_handler(i915, gt_iir[2]);
}
}
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
2018-02-15 7:37 ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
@ 2018-02-15 7:58 ` Patchwork
2018-02-15 8:14 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 7:58 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
URL : https://patchwork.freedesktop.org/series/38314/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a62345821ea6 drm/i915: Track GT interrupt handling using the master iir
f67401a8f891 drm/i915: Prune gen8_gt_irq_handler
-:46: WARNING: line over 80 characters
#46: FILE: drivers/gpu/drm/i915/i915_irq.c:1432:
+ writel(gt_iir[0], regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
-:55: WARNING: line over 80 characters
#55: FILE: drivers/gpu/drm/i915/i915_irq.c:1438:
+ writel(gt_iir[1], regs + i915_mmio_reg_offset(GEN8_GT_IIR(1)));
-:64: WARNING: line over 80 characters
#64: FILE: drivers/gpu/drm/i915/i915_irq.c:1443:
+ if (likely(gt_iir[2] & (i915->pm_rps_events | i915->pm_guc_events)))
-:81: WARNING: line over 80 characters
#81: FILE: drivers/gpu/drm/i915/i915_irq.c:1452:
+ writel(gt_iir[3], regs + i915_mmio_reg_offset(GEN8_GT_IIR(3)));
total: 0 errors, 4 warnings, 0 checks, 98 lines checked
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
2018-02-15 7:37 ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
2018-02-15 7:58 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir Patchwork
@ 2018-02-15 8:14 ` Patchwork
2018-02-15 13:31 ` ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 8:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
URL : https://patchwork.freedesktop.org/series/38314/
State : success
== Summary ==
Series 38314v1 series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
https://patchwork.freedesktop.org/api/1.0/series/38314/revisions/1/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:428s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:428s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:376s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:486s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:287s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:481s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:488s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:457s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:576s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:416s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:284s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:515s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:389s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:460s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:491s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:592s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:426s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:508s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:526s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:493s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:475s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:418s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:397s
Blacklisted hosts:
fi-glk-dsi total:117 pass:104 dwarn:0 dfail:0 fail:0 skip:12
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s
bd16af128e78b302b3034fa85626cd15dcf5f038 drm-tip: 2018y-02m-15d-00h-22m-40s UTC integration manifest
f67401a8f891 drm/i915: Prune gen8_gt_irq_handler
a62345821ea6 drm/i915: Track GT interrupt handling using the master iir
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8038/issues.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
` (2 preceding siblings ...)
2018-02-15 8:14 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-02-15 13:31 ` Patchwork
2018-02-15 15:21 ` [PATCH 1/2] " Mika Kuoppala
` (3 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 13:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
URL : https://patchwork.freedesktop.org/series/38314/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-apl) fdo#99912
Test kms_fbcon_fbt:
Subgroup fbc-suspend:
pass -> SKIP (shard-hsw) fdo#105087
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-msflip-blt:
pass -> FAIL (shard-apl) fdo#101623
Test perf_pmu:
Subgroup semaphore-wait-vcs0:
pass -> FAIL (shard-apl) fdo#105011
Test gem_eio:
Subgroup in-flight-suspend:
pass -> FAIL (shard-hsw) fdo#104676
Test perf:
Subgroup enable-disable:
fail -> PASS (shard-apl) fdo#103715
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
pass -> DMESG-WARN (shard-snb) fdo#102365
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#105087 https://bugs.freedesktop.org/show_bug.cgi?id=105087
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#105011 https://bugs.freedesktop.org/show_bug.cgi?id=105011
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
shard-apl total:3342 pass:1728 dwarn:1 dfail:0 fail:20 skip:1592 time:13843s
shard-hsw total:3427 pass:1757 dwarn:1 dfail:0 fail:11 skip:1657 time:14574s
shard-snb total:3427 pass:1347 dwarn:2 dfail:0 fail:10 skip:2068 time:7552s
Blacklisted hosts:
shard-kbl total:3427 pass:1905 dwarn:3 dfail:0 fail:22 skip:1497 time:11107s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8038/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
` (3 preceding siblings ...)
2018-02-15 13:31 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-02-15 15:21 ` Mika Kuoppala
2018-02-15 16:00 ` Chris Wilson
2018-02-19 10:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2) Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Mika Kuoppala @ 2018-02-15 15:21 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Keep the master iir and use it to reduce the number of reads and writes
> to the GT iir array, i.e. only the bits marked as set by the master iir
> are valid inside GT iir array and will be handled during the interrupt.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++----------------
> 1 file changed, 31 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..b7b377ba7b6e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
> static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> u32 master_ctl, u32 gt_iir[4])
> {
> +#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> + GEN8_GT_BCS_IRQ | \
> + GEN8_GT_VCS1_IRQ | \
> + GEN8_GT_VCS2_IRQ | \
> + GEN8_GT_VECS_IRQ | \
> + GEN8_GT_PM_IRQ | \
> + GEN8_GT_GUC_IRQ)
> +
> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
> if (gt_iir[0])
> @@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> }
>
> static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> - u32 gt_iir[4])
> + u32 master_ctl, u32 gt_iir[4])
> {
> - if (gt_iir[0]) {
> + if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> gen8_cs_irq_handler(dev_priv->engine[RCS],
> gt_iir[0], GEN8_RCS_IRQ_SHIFT);
> gen8_cs_irq_handler(dev_priv->engine[BCS],
> gt_iir[0], GEN8_BCS_IRQ_SHIFT);
> }
>
> - if (gt_iir[1]) {
> + if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> gen8_cs_irq_handler(dev_priv->engine[VCS],
> gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
> gen8_cs_irq_handler(dev_priv->engine[VCS2],
> gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
> }
>
> - if (gt_iir[3])
> + if (master_ctl & GEN8_GT_VECS_IRQ) {
> gen8_cs_irq_handler(dev_priv->engine[VECS],
> gt_iir[3], GEN8_VECS_IRQ_SHIFT);
> + }
>
> - if (gt_iir[2] & dev_priv->pm_rps_events)
> - gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> + if (gt_iir[2] & dev_priv->pm_rps_events)
> + gen6_rps_irq_handler(dev_priv, gt_iir[2]);
>
> - if (gt_iir[2] & dev_priv->pm_guc_events)
> - gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> + if (gt_iir[2] & dev_priv->pm_guc_events)
> + gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> + }
> }
>
> static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> @@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>
> do {
> u32 master_ctl, iir;
> - u32 gt_iir[4] = {};
> u32 pipe_stats[I915_MAX_PIPES] = {};
> u32 hotplug_status = 0;
> + u32 gt_iir[4];
> u32 ier = 0;
>
> master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> @@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> POSTING_READ(GEN8_MASTER_IRQ);
>
> - gen8_gt_irq_handler(dev_priv, gt_iir);
> + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
>
> if (hotplug_status)
> i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> @@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>
> static irqreturn_t gen8_irq_handler(int irq, void *arg)
> {
> - struct drm_device *dev = arg;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(arg);
> u32 master_ctl;
> - u32 gt_iir[4] = {};
> + u32 gt_iir[4];
>
> if (!intel_irqs_enabled(dev_priv))
> return IRQ_NONE;
> @@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>
> I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
>
> - /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> - disable_rpm_wakeref_asserts(dev_priv);
> -
> /* Find, clear, then process each source of interrupt */
> gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
> - gen8_gt_irq_handler(dev_priv, gt_iir);
> - gen8_de_irq_handler(dev_priv, master_ctl);
> +
> + /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> + if (master_ctl & ~GEN8_GT_IRQS) {
> + disable_rpm_wakeref_asserts(dev_priv);
> + gen8_de_irq_handler(dev_priv, master_ctl);
> + enable_rpm_wakeref_asserts(dev_priv);
> + }
>
> I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> - POSTING_READ_FW(GEN8_MASTER_IRQ);
>
> - enable_rpm_wakeref_asserts(dev_priv);
> + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
You want to serve display first? Do you recommend the
same approach to gen11?
-Mika
>
> return IRQ_HANDLED;
> }
> --
> 2.16.1
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 15:21 ` [PATCH 1/2] " Mika Kuoppala
@ 2018-02-15 16:00 ` Chris Wilson
2018-02-15 18:35 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-02-15 16:00 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2018-02-15 15:21:33)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Keep the master iir and use it to reduce the number of reads and writes
> > to the GT iir array, i.e. only the bits marked as set by the master iir
> > are valid inside GT iir array and will be handled during the interrupt.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++----------------
> > 1 file changed, 31 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index b886bd459acc..b7b377ba7b6e 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
> > static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> > u32 master_ctl, u32 gt_iir[4])
> > {
> > +#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> > + GEN8_GT_BCS_IRQ | \
> > + GEN8_GT_VCS1_IRQ | \
> > + GEN8_GT_VCS2_IRQ | \
> > + GEN8_GT_VECS_IRQ | \
> > + GEN8_GT_PM_IRQ | \
> > + GEN8_GT_GUC_IRQ)
> > +
> > if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> > gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
> > if (gt_iir[0])
> > @@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> > }
> >
> > static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> > - u32 gt_iir[4])
> > + u32 master_ctl, u32 gt_iir[4])
> > {
> > - if (gt_iir[0]) {
> > + if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> > gen8_cs_irq_handler(dev_priv->engine[RCS],
> > gt_iir[0], GEN8_RCS_IRQ_SHIFT);
> > gen8_cs_irq_handler(dev_priv->engine[BCS],
> > gt_iir[0], GEN8_BCS_IRQ_SHIFT);
> > }
> >
> > - if (gt_iir[1]) {
> > + if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> > gen8_cs_irq_handler(dev_priv->engine[VCS],
> > gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
> > gen8_cs_irq_handler(dev_priv->engine[VCS2],
> > gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
> > }
> >
> > - if (gt_iir[3])
> > + if (master_ctl & GEN8_GT_VECS_IRQ) {
> > gen8_cs_irq_handler(dev_priv->engine[VECS],
> > gt_iir[3], GEN8_VECS_IRQ_SHIFT);
> > + }
> >
> > - if (gt_iir[2] & dev_priv->pm_rps_events)
> > - gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> > + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> > + if (gt_iir[2] & dev_priv->pm_rps_events)
> > + gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> >
> > - if (gt_iir[2] & dev_priv->pm_guc_events)
> > - gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> > + if (gt_iir[2] & dev_priv->pm_guc_events)
> > + gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> > + }
> > }
> >
> > static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> > @@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> >
> > do {
> > u32 master_ctl, iir;
> > - u32 gt_iir[4] = {};
> > u32 pipe_stats[I915_MAX_PIPES] = {};
> > u32 hotplug_status = 0;
> > + u32 gt_iir[4];
> > u32 ier = 0;
> >
> > master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> > @@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> > I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> > POSTING_READ(GEN8_MASTER_IRQ);
> >
> > - gen8_gt_irq_handler(dev_priv, gt_iir);
> > + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
> >
> > if (hotplug_status)
> > i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> > @@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> >
> > static irqreturn_t gen8_irq_handler(int irq, void *arg)
> > {
> > - struct drm_device *dev = arg;
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct drm_i915_private *dev_priv = to_i915(arg);
> > u32 master_ctl;
> > - u32 gt_iir[4] = {};
> > + u32 gt_iir[4];
> >
> > if (!intel_irqs_enabled(dev_priv))
> > return IRQ_NONE;
> > @@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> >
> > I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
> >
> > - /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> > - disable_rpm_wakeref_asserts(dev_priv);
> > -
> > /* Find, clear, then process each source of interrupt */
> > gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
> > - gen8_gt_irq_handler(dev_priv, gt_iir);
> > - gen8_de_irq_handler(dev_priv, master_ctl);
> > +
> > + /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> > + if (master_ctl & ~GEN8_GT_IRQS) {
> > + disable_rpm_wakeref_asserts(dev_priv);
> > + gen8_de_irq_handler(dev_priv, master_ctl);
> > + enable_rpm_wakeref_asserts(dev_priv);
> > + }
> >
> > I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> > - POSTING_READ_FW(GEN8_MASTER_IRQ);
> >
> > - enable_rpm_wakeref_asserts(dev_priv);
> > + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
>
> You want to serve display first? Do you recommend the
> same approach to gen11?
The idea is that having squirrel the iir and acked the secondary
sources, we re-enabled the primary interrupt so that we service the next
interrupt quicker; whilst we continue to process the previous irq on
this cpu. Not sure if it makes a big difference in the end, we have a
lot of serialisation to overcome, but it's a nice consequence of Ville's
cleanup of splitting the ack/processing of the sources.
-Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler
2018-02-15 7:37 ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
@ 2018-02-15 16:57 ` Chris Wilson
2018-02-15 17:04 ` Mika Kuoppala
2018-02-19 10:09 ` [PATCH v2] " Chris Wilson
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-02-15 16:57 UTC (permalink / raw)
To: intel-gfx
Quoting Chris Wilson (2018-02-15 07:37:13)
> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> - gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
> - if (gt_iir[0])
> - I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
> + gt_iir[0] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
> + if (likely(gt_iir[0]))
> + writel(gt_iir[0], regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
What do we feel about
#define raw_reg_read32(mmio, reg) readl(mmio + i915_mmio_reg_offset(reg))
#define raw_reg_write32(mmio, reg, value) writel(value, mmio + i915_mmio_reg_offset(reg))
for transitioning away from the implicit argument in I915_READ?
-Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler
2018-02-15 16:57 ` Chris Wilson
@ 2018-02-15 17:04 ` Mika Kuoppala
0 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2018-02-15 17:04 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Chris Wilson (2018-02-15 07:37:13)
>> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
>> - gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
>> - if (gt_iir[0])
>> - I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
>> + gt_iir[0] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
>> + if (likely(gt_iir[0]))
>> + writel(gt_iir[0], regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
>
> What do we feel about
>
> #define raw_reg_read32(mmio, reg) readl(mmio + i915_mmio_reg_offset(reg))
> #define raw_reg_write32(mmio, reg, value) writel(value, mmio + i915_mmio_reg_offset(reg))
I am in favour. Shorter versions would be even more pleasing.
reg_read and reg_write.
-Mika
>
> for transitioning away from the implicit argument in I915_READ?
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 16:00 ` Chris Wilson
@ 2018-02-15 18:35 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2018-02-15 18:35 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Feb 15, 2018 at 04:00:04PM +0000, Chris Wilson wrote:
> Quoting Mika Kuoppala (2018-02-15 15:21:33)
> > Chris Wilson <chris@chris-wilson.co.uk> writes:
> >
> > > Keep the master iir and use it to reduce the number of reads and writes
> > > to the GT iir array, i.e. only the bits marked as set by the master iir
> > > are valid inside GT iir array and will be handled during the interrupt.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++----------------
> > > 1 file changed, 31 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index b886bd459acc..b7b377ba7b6e 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
> > > static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> > > u32 master_ctl, u32 gt_iir[4])
> > > {
> > > +#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> > > + GEN8_GT_BCS_IRQ | \
> > > + GEN8_GT_VCS1_IRQ | \
> > > + GEN8_GT_VCS2_IRQ | \
> > > + GEN8_GT_VECS_IRQ | \
> > > + GEN8_GT_PM_IRQ | \
> > > + GEN8_GT_GUC_IRQ)
> > > +
> > > if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> > > gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
> > > if (gt_iir[0])
> > > @@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> > > }
> > >
> > > static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> > > - u32 gt_iir[4])
> > > + u32 master_ctl, u32 gt_iir[4])
> > > {
> > > - if (gt_iir[0]) {
> > > + if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> > > gen8_cs_irq_handler(dev_priv->engine[RCS],
> > > gt_iir[0], GEN8_RCS_IRQ_SHIFT);
> > > gen8_cs_irq_handler(dev_priv->engine[BCS],
> > > gt_iir[0], GEN8_BCS_IRQ_SHIFT);
> > > }
> > >
> > > - if (gt_iir[1]) {
> > > + if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> > > gen8_cs_irq_handler(dev_priv->engine[VCS],
> > > gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
> > > gen8_cs_irq_handler(dev_priv->engine[VCS2],
> > > gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
> > > }
> > >
> > > - if (gt_iir[3])
> > > + if (master_ctl & GEN8_GT_VECS_IRQ) {
> > > gen8_cs_irq_handler(dev_priv->engine[VECS],
> > > gt_iir[3], GEN8_VECS_IRQ_SHIFT);
> > > + }
> > >
> > > - if (gt_iir[2] & dev_priv->pm_rps_events)
> > > - gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> > > + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> > > + if (gt_iir[2] & dev_priv->pm_rps_events)
> > > + gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> > >
> > > - if (gt_iir[2] & dev_priv->pm_guc_events)
> > > - gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> > > + if (gt_iir[2] & dev_priv->pm_guc_events)
> > > + gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> > > + }
> > > }
> > >
> > > static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > @@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> > >
> > > do {
> > > u32 master_ctl, iir;
> > > - u32 gt_iir[4] = {};
> > > u32 pipe_stats[I915_MAX_PIPES] = {};
> > > u32 hotplug_status = 0;
> > > + u32 gt_iir[4];
> > > u32 ier = 0;
> > >
> > > master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> > > @@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> > > I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> > > POSTING_READ(GEN8_MASTER_IRQ);
> > >
> > > - gen8_gt_irq_handler(dev_priv, gt_iir);
> > > + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
> > >
> > > if (hotplug_status)
> > > i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> > > @@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> > >
> > > static irqreturn_t gen8_irq_handler(int irq, void *arg)
> > > {
> > > - struct drm_device *dev = arg;
> > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct drm_i915_private *dev_priv = to_i915(arg);
> > > u32 master_ctl;
> > > - u32 gt_iir[4] = {};
> > > + u32 gt_iir[4];
> > >
> > > if (!intel_irqs_enabled(dev_priv))
> > > return IRQ_NONE;
> > > @@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> > >
> > > I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
> > >
> > > - /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> > > - disable_rpm_wakeref_asserts(dev_priv);
> > > -
> > > /* Find, clear, then process each source of interrupt */
> > > gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
> > > - gen8_gt_irq_handler(dev_priv, gt_iir);
> > > - gen8_de_irq_handler(dev_priv, master_ctl);
> > > +
> > > + /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> > > + if (master_ctl & ~GEN8_GT_IRQS) {
> > > + disable_rpm_wakeref_asserts(dev_priv);
> > > + gen8_de_irq_handler(dev_priv, master_ctl);
> > > + enable_rpm_wakeref_asserts(dev_priv);
> > > + }
> > >
> > > I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> > > - POSTING_READ_FW(GEN8_MASTER_IRQ);
> > >
> > > - enable_rpm_wakeref_asserts(dev_priv);
> > > + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
> >
> > You want to serve display first? Do you recommend the
> > same approach to gen11?
>
> The idea is that having squirrel the iir and acked the secondary
> sources, we re-enabled the primary interrupt so that we service the next
> interrupt quicker; whilst we continue to process the previous irq on
> this cpu. Not sure if it makes a big difference in the end, we have a
> lot of serialisation to overcome, but it's a nice consequence of Ville's
> cleanup of splitting the ack/processing of the sources.
I've occasionally pondered about moving the processing part to a thread,
with maybe leaving some super duper critical execlist stuff in the hard
irq part. Though I'm not sure if that would be siginificantly different
to just moving the entire thing into a thread, or just leaving it all
where it is now. Would need to collect some hard data I suppose.
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915: Prune gen8_gt_irq_handler
2018-02-15 7:37 ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
2018-02-15 16:57 ` Chris Wilson
@ 2018-02-19 10:09 ` Chris Wilson
2018-02-19 13:59 ` Mika Kuoppala
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-02-19 10:09 UTC (permalink / raw)
To: intel-gfx
The compiler is not automatically caching the i915->regs address inside
a register and emitting a load for every mmio access. For simple
functions like gen8_gt_irq_handler that are already using the raw
accessors, we can open-code them for substantial savings:
add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
Function old new delta
gen8_gt_irq_handler 290 266 -24
gen8_gt_irq_ack 181 122 -59
Total: Before=954637, After=954554, chg -0.01%
v2: Add raw_reg_read/raw_reg_write.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
And so begins the long haul of de-I915_READ/WRITE-ing the driver...
---
drivers/gpu/drm/i915/i915_irq.c | 58 ++++++++++++++++++-------------------
drivers/gpu/drm/i915/intel_uncore.h | 5 ++++
2 files changed, 33 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c7f6b719e86d..17de6cef2a30 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1413,9 +1413,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
tasklet_hi_schedule(&execlists->tasklet);
}
-static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_ack(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
{
+ void __iomem * const regs = i915->regs;
+
#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
GEN8_GT_BCS_IRQ | \
GEN8_GT_VCS1_IRQ | \
@@ -1425,62 +1427,58 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
GEN8_GT_GUC_IRQ)
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
- if (gt_iir[0])
- I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
+ gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
+ if (likely(gt_iir[0]))
+ raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
}
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
- gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
- if (gt_iir[1])
- I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
+ gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
+ if (likely(gt_iir[1]))
+ raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
}
- if (master_ctl & GEN8_GT_VECS_IRQ) {
- gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
- if (gt_iir[3])
- I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
+ if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+ gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
+ if (likely(gt_iir[2] & (i915->pm_rps_events |
+ i915->pm_guc_events)))
+ raw_reg_write(regs, GEN8_GT_IIR(2),
+ gt_iir[2] & (i915->pm_rps_events |
+ i915->pm_guc_events));
}
- if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
- if (gt_iir[2] & (dev_priv->pm_rps_events |
- dev_priv->pm_guc_events)) {
- I915_WRITE_FW(GEN8_GT_IIR(2),
- gt_iir[2] & (dev_priv->pm_rps_events |
- dev_priv->pm_guc_events));
- }
+ if (master_ctl & GEN8_GT_VECS_IRQ) {
+ gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
+ if (likely(gt_iir[3]))
+ raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
}
}
-static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_handler(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
{
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- gen8_cs_irq_handler(dev_priv->engine[RCS],
+ gen8_cs_irq_handler(i915->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT);
- gen8_cs_irq_handler(dev_priv->engine[BCS],
+ gen8_cs_irq_handler(i915->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT);
}
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
- gen8_cs_irq_handler(dev_priv->engine[VCS],
+ gen8_cs_irq_handler(i915->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
- gen8_cs_irq_handler(dev_priv->engine[VCS2],
+ gen8_cs_irq_handler(i915->engine[VCS2],
gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
}
if (master_ctl & GEN8_GT_VECS_IRQ) {
- gen8_cs_irq_handler(dev_priv->engine[VECS],
+ gen8_cs_irq_handler(i915->engine[VECS],
gt_iir[3], GEN8_VECS_IRQ_SHIFT);
}
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- if (gt_iir[2] & dev_priv->pm_rps_events)
- gen6_rps_irq_handler(dev_priv, gt_iir[2]);
-
- if (gt_iir[2] & dev_priv->pm_guc_events)
- gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+ gen6_rps_irq_handler(i915, gt_iir[2]);
+ gen9_guc_irq_handler(i915, gt_iir[2]);
}
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index bed019ef000f..53ef77d0c97c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -198,4 +198,9 @@ int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2, timeout_ms, NULL);
}
+#define raw_reg_read(base, reg) \
+ readl(base + i915_mmio_reg_offset(reg))
+#define raw_reg_write(base, reg, value) \
+ writel(value, base + i915_mmio_reg_offset(reg))
+
#endif /* !__INTEL_UNCORE_H__ */
--
2.16.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
` (4 preceding siblings ...)
2018-02-15 15:21 ` [PATCH 1/2] " Mika Kuoppala
@ 2018-02-19 10:31 ` Patchwork
2018-02-19 11:41 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-19 13:47 ` [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Mika Kuoppala
7 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-19 10:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)
URL : https://patchwork.freedesktop.org/series/38314/
State : success
== Summary ==
Series 38314v2 series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir
https://patchwork.freedesktop.org/api/1.0/series/38314/revisions/2/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (fi-skl-6700k2) fdo#104108
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
pass -> INCOMPLETE (fi-bxt-dsi) fdo#103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:429s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:488s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:286s
fi-bxt-dsi total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:26
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:470s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:456s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:570s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:410s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:284s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:510s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:389s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:419s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:463s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:490s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:499s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:427s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:527s
fi-skl-6700k2 total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:494s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:483s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:416s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:431s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:398s
ff949b5b7de75e1344f5c2cfd1d72f9c10ab446e drm-tip: 2018y-02m-19d-09h-45m-51s UTC integration manifest
09bd9565b659 drm/i915: Prune gen8_gt_irq_handler
bbb6073d44cd drm/i915: Track GT interrupt handling using the master iir
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8064/issues.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
` (5 preceding siblings ...)
2018-02-19 10:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2) Patchwork
@ 2018-02-19 11:41 ` Patchwork
2018-02-19 15:51 ` Chris Wilson
2018-02-19 13:47 ` [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Mika Kuoppala
7 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2018-02-19 11:41 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)
URL : https://patchwork.freedesktop.org/series/38314/
State : success
== Summary ==
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-atomic:
pass -> FAIL (shard-hsw) fdo#104873
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> SKIP (shard-snb) fdo#103375
Test kms_plane_multiple:
Subgroup atomic-pipe-c-tiling-x:
fail -> PASS (shard-apl) fdo#103831
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Test gem_eio:
Subgroup in-flight:
fail -> PASS (shard-hsw) fdo#104676
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103831 https://bugs.freedesktop.org/show_bug.cgi?id=103831
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-apl total:3370 pass:1757 dwarn:1 dfail:0 fail:13 skip:1598 time:12431s
shard-hsw total:3434 pass:1761 dwarn:1 dfail:0 fail:3 skip:1668 time:11878s
shard-snb total:3434 pass:1351 dwarn:1 dfail:0 fail:2 skip:2080 time:6601s
Blacklisted hosts:
shard-kbl total:3375 pass:1900 dwarn:1 dfail:0 fail:13 skip:1460 time:9352s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8064/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
` (6 preceding siblings ...)
2018-02-19 11:41 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-02-19 13:47 ` Mika Kuoppala
7 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2018-02-19 13:47 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Keep the master iir and use it to reduce the number of reads and writes
> to the GT iir array, i.e. only the bits marked as set by the master iir
> are valid inside GT iir array and will be handled during the interrupt.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
It does what it promises and the writes are reduced.
The ack/handle symmetry needs more thought now
on reading but if that becomes a problem we can split
gt iir's for per engine functions.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++----------------
> 1 file changed, 31 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..b7b377ba7b6e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
> static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> u32 master_ctl, u32 gt_iir[4])
> {
> +#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> + GEN8_GT_BCS_IRQ | \
> + GEN8_GT_VCS1_IRQ | \
> + GEN8_GT_VCS2_IRQ | \
> + GEN8_GT_VECS_IRQ | \
> + GEN8_GT_PM_IRQ | \
> + GEN8_GT_GUC_IRQ)
> +
> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
> if (gt_iir[0])
> @@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> }
>
> static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> - u32 gt_iir[4])
> + u32 master_ctl, u32 gt_iir[4])
> {
> - if (gt_iir[0]) {
> + if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> gen8_cs_irq_handler(dev_priv->engine[RCS],
> gt_iir[0], GEN8_RCS_IRQ_SHIFT);
> gen8_cs_irq_handler(dev_priv->engine[BCS],
> gt_iir[0], GEN8_BCS_IRQ_SHIFT);
> }
>
> - if (gt_iir[1]) {
> + if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> gen8_cs_irq_handler(dev_priv->engine[VCS],
> gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
> gen8_cs_irq_handler(dev_priv->engine[VCS2],
> gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
> }
>
> - if (gt_iir[3])
> + if (master_ctl & GEN8_GT_VECS_IRQ) {
> gen8_cs_irq_handler(dev_priv->engine[VECS],
> gt_iir[3], GEN8_VECS_IRQ_SHIFT);
> + }
>
> - if (gt_iir[2] & dev_priv->pm_rps_events)
> - gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> + if (gt_iir[2] & dev_priv->pm_rps_events)
> + gen6_rps_irq_handler(dev_priv, gt_iir[2]);
>
> - if (gt_iir[2] & dev_priv->pm_guc_events)
> - gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> + if (gt_iir[2] & dev_priv->pm_guc_events)
> + gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> + }
> }
>
> static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> @@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>
> do {
> u32 master_ctl, iir;
> - u32 gt_iir[4] = {};
> u32 pipe_stats[I915_MAX_PIPES] = {};
> u32 hotplug_status = 0;
> + u32 gt_iir[4];
> u32 ier = 0;
>
> master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> @@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> POSTING_READ(GEN8_MASTER_IRQ);
>
> - gen8_gt_irq_handler(dev_priv, gt_iir);
> + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
>
> if (hotplug_status)
> i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> @@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>
> static irqreturn_t gen8_irq_handler(int irq, void *arg)
> {
> - struct drm_device *dev = arg;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(arg);
> u32 master_ctl;
> - u32 gt_iir[4] = {};
> + u32 gt_iir[4];
>
> if (!intel_irqs_enabled(dev_priv))
> return IRQ_NONE;
> @@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>
> I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
>
> - /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> - disable_rpm_wakeref_asserts(dev_priv);
> -
> /* Find, clear, then process each source of interrupt */
> gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
> - gen8_gt_irq_handler(dev_priv, gt_iir);
> - gen8_de_irq_handler(dev_priv, master_ctl);
> +
> + /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> + if (master_ctl & ~GEN8_GT_IRQS) {
> + disable_rpm_wakeref_asserts(dev_priv);
> + gen8_de_irq_handler(dev_priv, master_ctl);
> + enable_rpm_wakeref_asserts(dev_priv);
> + }
>
> I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> - POSTING_READ_FW(GEN8_MASTER_IRQ);
>
> - enable_rpm_wakeref_asserts(dev_priv);
> + gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
>
> return IRQ_HANDLED;
> }
> --
> 2.16.1
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915: Prune gen8_gt_irq_handler
2018-02-19 10:09 ` [PATCH v2] " Chris Wilson
@ 2018-02-19 13:59 ` Mika Kuoppala
2018-02-19 14:12 ` Chris Wilson
0 siblings, 1 reply; 17+ messages in thread
From: Mika Kuoppala @ 2018-02-19 13:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> The compiler is not automatically caching the i915->regs address inside
> a register and emitting a load for every mmio access. For simple
> functions like gen8_gt_irq_handler that are already using the raw
> accessors, we can open-code them for substantial savings:
>
> add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
> Function old new delta
> gen8_gt_irq_handler 290 266 -24
> gen8_gt_irq_ack 181 122 -59
> Total: Before=954637, After=954554, chg -0.01%
>
> v2: Add raw_reg_read/raw_reg_write.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> And so begins the long haul of de-I915_READ/WRITE-ing the driver...
> ---
> drivers/gpu/drm/i915/i915_irq.c | 58 ++++++++++++++++++-------------------
> drivers/gpu/drm/i915/intel_uncore.h | 5 ++++
> 2 files changed, 33 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c7f6b719e86d..17de6cef2a30 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1413,9 +1413,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
> tasklet_hi_schedule(&execlists->tasklet);
> }
>
> -static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> +static void gen8_gt_irq_ack(struct drm_i915_private *i915,
> u32 master_ctl, u32 gt_iir[4])
> {
> + void __iomem * const regs = i915->regs;
> +
> #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> GEN8_GT_BCS_IRQ | \
> GEN8_GT_VCS1_IRQ | \
> @@ -1425,62 +1427,58 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> GEN8_GT_GUC_IRQ)
>
> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> - gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
> - if (gt_iir[0])
> - I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
> + gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
> + if (likely(gt_iir[0]))
> + raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
> }
>
> if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> - gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
> - if (gt_iir[1])
> - I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
> + gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
> + if (likely(gt_iir[1]))
> + raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
> }
>
> - if (master_ctl & GEN8_GT_VECS_IRQ) {
> - gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
> - if (gt_iir[3])
> - I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
> + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> + gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
> + if (likely(gt_iir[2] & (i915->pm_rps_events |
> + i915->pm_guc_events)))
> + raw_reg_write(regs, GEN8_GT_IIR(2),
> + gt_iir[2] & (i915->pm_rps_events |
> + i915->pm_guc_events));
I would gone as far as reg_read reg_write but that might be too far :)
We leave te events hanging what are of no interest. As we are doing
the masks with these so I find it peculiar that we dont ack
everything as the masks should be in place and perhaps notify on
events appearing without order in place for them.
Well it is not in a scope for this patch tho. So,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> }
>
> - if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> - gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
> - if (gt_iir[2] & (dev_priv->pm_rps_events |
> - dev_priv->pm_guc_events)) {
> - I915_WRITE_FW(GEN8_GT_IIR(2),
> - gt_iir[2] & (dev_priv->pm_rps_events |
> - dev_priv->pm_guc_events));
> - }
> + if (master_ctl & GEN8_GT_VECS_IRQ) {
> + gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
> + if (likely(gt_iir[3]))
> + raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
> }
> }
>
> -static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> +static void gen8_gt_irq_handler(struct drm_i915_private *i915,
> u32 master_ctl, u32 gt_iir[4])
> {
> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> - gen8_cs_irq_handler(dev_priv->engine[RCS],
> + gen8_cs_irq_handler(i915->engine[RCS],
> gt_iir[0], GEN8_RCS_IRQ_SHIFT);
> - gen8_cs_irq_handler(dev_priv->engine[BCS],
> + gen8_cs_irq_handler(i915->engine[BCS],
> gt_iir[0], GEN8_BCS_IRQ_SHIFT);
> }
>
> if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> - gen8_cs_irq_handler(dev_priv->engine[VCS],
> + gen8_cs_irq_handler(i915->engine[VCS],
> gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
> - gen8_cs_irq_handler(dev_priv->engine[VCS2],
> + gen8_cs_irq_handler(i915->engine[VCS2],
> gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
> }
>
> if (master_ctl & GEN8_GT_VECS_IRQ) {
> - gen8_cs_irq_handler(dev_priv->engine[VECS],
> + gen8_cs_irq_handler(i915->engine[VECS],
> gt_iir[3], GEN8_VECS_IRQ_SHIFT);
> }
>
> if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> - if (gt_iir[2] & dev_priv->pm_rps_events)
> - gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> -
> - if (gt_iir[2] & dev_priv->pm_guc_events)
> - gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> + gen6_rps_irq_handler(i915, gt_iir[2]);
> + gen9_guc_irq_handler(i915, gt_iir[2]);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index bed019ef000f..53ef77d0c97c 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -198,4 +198,9 @@ int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
> 2, timeout_ms, NULL);
> }
>
> +#define raw_reg_read(base, reg) \
> + readl(base + i915_mmio_reg_offset(reg))
> +#define raw_reg_write(base, reg, value) \
> + writel(value, base + i915_mmio_reg_offset(reg))
> +
> #endif /* !__INTEL_UNCORE_H__ */
> --
> 2.16.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915: Prune gen8_gt_irq_handler
2018-02-19 13:59 ` Mika Kuoppala
@ 2018-02-19 14:12 ` Chris Wilson
0 siblings, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-02-19 14:12 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2018-02-19 13:59:43)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > The compiler is not automatically caching the i915->regs address inside
> > a register and emitting a load for every mmio access. For simple
> > functions like gen8_gt_irq_handler that are already using the raw
> > accessors, we can open-code them for substantial savings:
> >
> > add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
> > Function old new delta
> > gen8_gt_irq_handler 290 266 -24
> > gen8_gt_irq_ack 181 122 -59
> > Total: Before=954637, After=954554, chg -0.01%
> >
> > v2: Add raw_reg_read/raw_reg_write.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > - if (master_ctl & GEN8_GT_VECS_IRQ) {
> > - gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
> > - if (gt_iir[3])
> > - I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
> > + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> > + gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
> > + if (likely(gt_iir[2] & (i915->pm_rps_events |
> > + i915->pm_guc_events)))
> > + raw_reg_write(regs, GEN8_GT_IIR(2),
> > + gt_iir[2] & (i915->pm_rps_events |
> > + i915->pm_guc_events));
>
> I would gone as far as reg_read reg_write but that might be too far :)
Yeah, I went back to raw_ prefixes so that it has the reminder that
these do bypass all the niceties we have in our mmio vfuncs (tracing,
HW debugging, automatic handling of fw, locking, w/a handling etc).
> We leave te events hanging what are of no interest. As we are doing
> the masks with these so I find it peculiar that we dont ack
> everything as the masks should be in place and perhaps notify on
> events appearing without order in place for them.
It does seem odd indeed, I think we should just clear it as well. Can be
done later so that we don't rush headlong into a regression.
-Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)
2018-02-19 11:41 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-02-19 15:51 ` Chris Wilson
0 siblings, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-02-19 15:51 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
Quoting Patchwork (2018-02-19 11:41:15)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)
> URL : https://patchwork.freedesktop.org/series/38314/
> State : success
>
> == Summary ==
>
> Test kms_cursor_legacy:
> Subgroup 2x-long-flip-vs-cursor-atomic:
> pass -> FAIL (shard-hsw) fdo#104873
> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-a:
> pass -> SKIP (shard-snb) fdo#103375
> Test kms_plane_multiple:
> Subgroup atomic-pipe-c-tiling-x:
> fail -> PASS (shard-apl) fdo#103831
> Test perf:
> Subgroup oa-exponents:
> pass -> FAIL (shard-apl) fdo#102254
> Test gem_eio:
> Subgroup in-flight:
> fail -> PASS (shard-hsw) fdo#104676
> Test kms_setmode:
> Subgroup basic:
> fail -> PASS (shard-hsw) fdo#99912
Thanks for the review, pushed. Plenty more irq functions to trim :)
-Chris
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^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-02-19 15:51 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-15 7:37 [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Chris Wilson
2018-02-15 7:37 ` [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler Chris Wilson
2018-02-15 16:57 ` Chris Wilson
2018-02-15 17:04 ` Mika Kuoppala
2018-02-19 10:09 ` [PATCH v2] " Chris Wilson
2018-02-19 13:59 ` Mika Kuoppala
2018-02-19 14:12 ` Chris Wilson
2018-02-15 7:58 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir Patchwork
2018-02-15 8:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-15 13:31 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-15 15:21 ` [PATCH 1/2] " Mika Kuoppala
2018-02-15 16:00 ` Chris Wilson
2018-02-15 18:35 ` Ville Syrjälä
2018-02-19 10:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2) Patchwork
2018-02-19 11:41 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-19 15:51 ` Chris Wilson
2018-02-19 13:47 ` [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir Mika Kuoppala
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